111111111111111111111111111111111111111111111111111111111111111111111111111
`US005459683A
`[Ill Patent Number:
`[ 45] Date of Patent:
`
`5,459,683
`Oct. 17, 1995
`
`United States Patent [19]
`U esugi et al.
`
`[54] APPARATUS FOR CALCULATING THE
`SQUARE ROOT OF THE SUM OF TWO
`SQUARES
`
`[75]
`
`Inventors: Mitsuru Uesugi; Kouichi Honma, both
`of Yokohama, Japan
`
`[73] Assignee: Matsushita Electric Industrial Co.,
`Ltd., Osaka, Japan
`
`[21] Appl. No.: 277,826
`
`[22] Filed:
`
`Jul. 20, 1994
`
`[30]
`
`Foreign Application Priority Data
`
`[JP]
`
`Japan .................................... 5-191099
`
`Aug. 2, 1993
`Int. Cl.6
`........................................................ G06F 7/38
`[51]
`[52] u.s. c1 . .............................................................. 364n52
`[58] Field of Search ............................................... 3641752
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`3,829,671
`3,829,672
`3,858,036
`4,503,549
`4,553,260
`4,599,701
`4,694,417
`4,736,334
`4,747,067
`5,159,567
`
`811974 Gathright et al ....................... 3641752
`811974 Sather ..................................... 3641752
`1211974 Lunsford ................................. 3641752
`311985 Slabinski ................................. 3641752
`11/1985 Belt et al ................................ 3641752
`711986 Vojir et al ............................... 3641752
`9/1987 Cantwell ................................. 3641752
`4/1988 Mebrgardt ............................... 3641752
`5/1988 Jagodnik, Jr. et al. ................. 3641752
`10/1992 Gobert .................................... 3641757
`
`FOREIGN PATENT DOCUMENTS
`
`0238300
`
`9/1987 European Pat. Off ..
`
`0437876
`2146200
`
`711991 European Pat. Off ..
`411985 United Kingdom.
`
`OTHER PUBLICATIONS
`
`Electronics Letters, vol. 10, No. 13, 27 Jun. 1974, Engage
`GB, pp. 255-256, Braun et al. 'Digital hardware for approxi(cid:173)
`mating to the amplitude of quadrature pairs'.
`Electronics, vol. 56, No. 17, 25 Aug. 1983, New York US,
`pp. 138-139, Ho et al. 'Comparator compares 2's comple(cid:173)
`ment numbers'.
`
`Primary Examiner-Tan V. Mai
`Attorney, Agent, or Firm-Lowe, Price, LeBlanc & Becker
`
`[57]
`
`ABSTRACT
`
`A first digital signal of a serial form is processed into a
`second digital signal of a serial form. The second digital
`signal represents an absolute value of a value represented by
`the first digital signal. A third digital signal of a serial form
`is processed into a fourth digital signal of a serial form. The
`fourth digital signal represents an absolute value of a value
`represented by the third digital signal. The values repre(cid:173)
`sented by the first and third digital signals are compared to
`generate a comparison-result digital signal representing a
`result of the comparison. A calculation-result digital signal
`of a serial form is generated in response to the second digital
`signal, the fourth digital signal, and the comparison-result
`digital signal. The calculation-result digital signal represents
`a value which is approximate to a square root of a sum of a
`square of the value represented by the first digital signal and
`a square of the value represented by the third digital signal.
`
`4 Claims, 9 Drawing Sheets
`
`Sa
`
`Sb
`
`I
`
`l
`
`.....
`
`..
`
`I
`
`...
`
`20
`JV
`ABSOLUTE
`VALUE
`-• COHPA
`...
`
`fr21
`.. ABSOLUTE
`..
`VALUE
`CALC
`...
`
`I
`
`JV
`
`I
`
`MUL
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`- 1 .
`
`So
`
`.. ...
`
`.. ...
`
`...
`
`.~
`
`...
`
`I
`
`L __ --~
`
`Petitioner Apple Inc.
`Ex. 1015, p. 1
`
`

`

`U.S. Patent
`
`Oct. 17, 1995
`
`Sheet 1 of 9
`
`5,459,683
`
`,-
`
`N
`
`Sa
`
`Sb
`
`N
`
`FIG. 1 PRIOR ART
`
`2
`
`N-BIT
`HUL
`
`N-BIT
`HUL
`
`4
`
`H+l
`
`5
`
`SQUARE
`ROOT
`
`So
`
`I
`
`_ _j
`
`FIG. 2 PRIOR ART
`
`-
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`fo'6
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`p.)
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`
`N-BIT ~ N-BIT
`HPX
`HUL
`L+
`
`Sa N
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`~ LATCH ~ H+l
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`H
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`I
`
`SQUARE
`ROOT
`I
`
`So
`
`I
`
`I
`
`Petitioner Apple Inc.
`Ex. 1015, p. 2
`
`

`

`U.S. Patent
`
`Oct. 17, 1995
`
`Sheet 2 of 9
`
`5,459,683
`
`FIG. 3
`
`_.,
`
`r+
`
`N-BIT
`SUB
`
`13
`~
`-
`
`I
`
`'"',11
`Sa N N-BIT
`N
`/, ABSOLUTE ~
`VALUE
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`yr
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`I
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`Sb N N-BIT
`r. ABSOLUTE
`VALUE
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`F
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`N
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`/
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`F
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`N-BIT ~ H-BIT
`ADO
`HPX
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`I
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`--,4 N-BIT
`HUL
`HPX
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`
`FIXED
`VALUE
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`--
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`I
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`I
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`-
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`f
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`
`FIG. 4
`
`20
`,IV
`ABSOLUTE
`VALUE
`COHPA
`
`Sa
`Sb
`
`I
`I
`
`I
`
`JV' 21
`_., ABSOLUTE
`VALUE
`----+ CALC
`
`I
`
`;v
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`HUL ~
`
`...
`
`I
`
`L _____ ~
`
`Petitioner Apple Inc.
`Ex. 1015, p. 3
`
`

`

`U.S. Patent
`
`Oct. 17, 1995
`
`Sheet 3 of 9
`
`5,459,683
`
`FIG. 5
`
`j\/23
`
`E24
`
`r
`
`EX-OR r--. LATCH
`
`1>20
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`ADD
`l ! l> 27
`
`LATCH
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`528
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`1-BIT
`~NOT J-. ADD
`T ! l529
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`I
`
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`
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`
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`
`LATCH
`L__ _______ ------- ------- --~
`
`I
`
`Petitioner Apple Inc.
`Ex. 1015, p. 4
`
`

`

`U.S. Patent
`
`Oct. 17, 1995
`
`Sheet 4 of 9
`
`5,459,683
`
`FIG. 6
`
`Sa
`
`~
`
`I
`
`I
`
`34A
`
`N
`SHIFT
`REGISTER
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`36A
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`EX-OR
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`1535A
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`;1/348
`SHIFT
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`Sb
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`. EX-OR
`358
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`~ ...
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`ADD
`
`...
`
`388
`
`"7
`
`I
`
`I
`
`LATCH
`
`Petitioner Apple Inc.
`Ex. 1015, p. 5
`
`

`

`~
`
`"" Q()
`
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`Ut
`~
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`Ut
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`FIG. 7
`
`Petitioner Apple Inc.
`Ex. 1015, p. 6
`
`'
`
`'
`
`I
`
`I
`
`Se
`
`Sd
`
`Sc
`
`

`

`U.S. Patent
`
`Oct. 17, 1995
`
`Sheet 6 of 9
`
`5,459,683
`
`FIG. 8
`
`SIGNAL Sa
`SIGNAL Sb
`
`1
`0
`
`I
`I
`
`0 I 1
`0 I 1
`
`I
`I
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`1
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`1
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`I 1 I 0 I 0
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`
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`
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`
`:o:o o:1 1 1 1
`
`I
`
`I
`
`I
`
`1 1 . 1 1 1 0 I 0 0 0
`
`EX-OR 23
`
`LATCH 24
`
`ADDER 26
`
`LATCH 27
`
`ADDER 28
`
`LATCH 29
`
`HUL TIPLEXER 30
`
`EX-OR 31
`
`FIG. 9
`SIGNAL
`SIGNAL
`Sa
`Sb
`o~
`0~
`
`o~
`
`0~
`
`0~
`NEGATIVE
`NEGATIVE
`0~
`
`o~
`NEGATIVE
`NEGATIVE
`0~
`NEGATIVE NEGATIVE
`NEGATIVE NEGATIVE
`
`RELATION BETWEEN MULTIPLEXER
`Sa AND Sb
`OUTPUT
`0
`ISai~ISbl
`ISai<ISbl
`1
`0
`ISai~ISbl
`ISai<ISbl
`1
`ISai>ISbl
`1
`0
`ISai~ISbl
`ISai>ISbl
`1
`0
`ISai~ISbl
`
`..
`
`TIME
`
`Petitioner Apple Inc.
`Ex. 1015, p. 7
`
`

`

`U.S. Patent
`
`Oct. 17, 1995
`
`Sheet 7 of 9
`
`5,459,683
`
`SIGNAL
`Sb
`0~
`
`SIGNAL
`Sa
`0~
`
`0~
`
`0~
`
`0~
`NEGATIVE
`NEGATIVE
`0~
`
`0~
`NEGATIVE
`NEGATIVE
`0~
`NEGATIVE NEGATIVE
`NEGATIVE NEGATIVE
`
`FIG. 10
`
`RELATION BETWEEN
`Sa AND Sb
`ISai~ISbl
`ISai<ISbl
`ISai~ISbl
`ISai<ISbl
`ISai>ISbl
`ISai~ISbl
`ISai>ISbl
`ISai~ISbl
`
`SIGNAL Sc
`0
`1
`0
`1
`0
`1
`0
`1
`
`FIG. 11
`
`SIGNAL Sa
`
`SHIFT REGISTER
`34A
`
`LATCH 35A
`
`EX-OR 36A
`
`LATCH 37A
`
`SIGNAL Sd
`
`1 0 0 1 : 1 :
`
`I
`
`I
`
`- I
`
`1
`
`I
`- I
`I
`
`1
`
`:o
`
`o:
`
`!O
`
`..
`
`TIME
`
`Petitioner Apple Inc.
`Ex. 1015, p. 8
`
`

`

`U.S. Patent
`
`Oct. 17, 1995
`
`Sheet 8 of 9
`
`5,459,683
`
`FIG. 12
`
`SIGNAL Sc
`
`1
`
`SIGNAL Sd
`
`1 0 I 1 0 0
`
`SIGNAL Se
`
`0 1 1 1 0
`
`MULTIPLEXER 43
`
`MULTIPLEXER 44
`
`SIGNAL Sg
`
`SIGNAL Sh
`
`SIGNAL Si
`
`0
`
`SIGNAL Sj
`
`SIGNAL Sk
`
`ADDER 62
`
`0
`
`ADDER 65
`
`ADDER 68
`
`'0
`
`0
`
`ADDER 70
`
`iO
`
`0
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`0
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`0
`
`0
`
`0
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`0
`
`0
`
`0
`
`o:
`
`:o
`
`.0
`
`1
`
`~
`
`TIME
`
`Petitioner Apple Inc.
`Ex. 1015, p. 9
`
`

`

`INVA}|JIN0SEV
`
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`
`U.S. Patent
`U.S. Patent
`
`Oct. 17, 1995
`Oct. 17, 1995
`
`Sheet 9 of 9
`Sheet 9 of 9
`
`5,459,683
`5,459,683
`
`('Y)
`CJ)
`
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`
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`.....
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`
`Petitioner Apple Inc.
`Petitioner Apple Inc.
`Ex. 1015, p. 10
`Ex. 1015, p. 10
`
`
`
`

`

`5,459,683
`
`1
`APPARATUS FOR CALCULATING THE
`SQUARE ROOT OF THE SUM OF TWO
`SQUARES
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`This invention relates to an apparatus for calculating the
`square root of the sum ofthe square of the value represented
`by a first digital signal and the square of the value repre(cid:173)
`sented by a second digital signal.
`2. Description of the Prior Art
`In digital signal processing, some calculations are
`intended to derive the square root So of the sum of the square
`of a first value represented by a first digital signal and the
`square of a second value represented by a second digital
`signal. Specifically, the square root So is expressed as So=
`= A2+B 2 where "A" denotes the value represented by the 20
`first digital signal and "B" denotes the value represented by
`the second digital signal.
`As will be described later, prior-art apparatuses for such
`calculations tend to be complicated in structure.
`
`15
`
`SUMMARY OF THE INVENTION
`
`2
`1-bit adder for adding an output signal from the Exclusive(cid:173)
`OR circuit and an output signal from the second latch, and
`generating the fourth digital signal; wherein the second latch
`is operative for latching a carry signal generated by the
`5 adder.
`It is preferable that the third means comprises a first
`Exclusive-OR circuit for executing Exclusive-OR operation
`between the first digital signal and the third digital signal; a
`first latch for latching an output signal from the first Exclu-
`10 sive-OR circuit; an inverter for inverting the third digital
`signal; a first 1-bit adder for adding the first digital signal
`and the second digital signal; a second latch for latching a
`carry signal generated by the first adder; a second 1-bit adder
`for adding the first digital signal an output signal from the
`inverter; a third latch for latching a carry signal generated by
`the second adder; a multiplexer for selecting one of an
`output signal from the first adder and an output signal from
`the second adder in response to an output signal from the
`first latch; and a second Exclusive-OR circuit for executing
`Exclusive-OR operation between the first digital signal and
`an output signal from the multiplexer, and for generating the
`comparison-result signal in response to the first digital signal
`and the output signal from the multiplexer.
`It is preferable that the fourth means comprises a first
`25 multiplexer for selecting one of the second digital signal and
`the fourth digital signal in response to the comparison-result
`signal; a second multiplexer for selecting one of the second
`digital signal and the fourth digital signal in response to the
`comparison-result signal; a first series combination of flip-
`30 flops successively storing an output signal from the first
`multiplexer; a second series combination of flip-flops suc(cid:173)
`cessively storing an output signal from the second multi(cid:173)
`plexer; a first 1-bit adder for adding am output signal from
`the first combination of the flip-flops and the output signal
`from the second multiplexer; a first latch for latching a carry
`signal generated by the first adder; a second 1-bit adder for
`adding output signals from given flip-flops in the second
`combination; a second latch for latching a carry signal
`generated by the second adder; a third 1-bit adder for adding
`40 an output signal from the second combination of the flip-
`flops and an output signal from the second adder; a third
`latch for latching a carry signal generated by the third adder;
`a fourth 1-bit adder for adding an output signal from the first
`adder and an output signal from the third adder; and a fourth
`latch for latching a carry signal generated by the fourth
`adder.
`
`35
`
`45
`
`It is an object of this invention to provide an improved
`calculation apparatus.
`This invention provides a calculation apparatus compris(cid:173)
`ing first means for processing a first digital signal of a serial
`form into a second digital signal of a serial form, the second
`digital signal representing an absolute value of a value
`represented by the first digital signal; second means for
`processing a third digital signal of a serial form into a fourth
`digital signal of a serial form, the fourth digital signal
`representing an absolute value of a value represented by the
`third digital signal; third means for comparing the values
`represented by the first and third digital signals, and gener(cid:173)
`ating a comparison-result digital signal representing a result
`of said comparing; and fourth means for generating a
`calculation-result digital signal of a serial form in response
`to the second digital signal, the fourth digital signal, and the
`comparison-result digital signal, the calculation-result digi(cid:173)
`tal signal representing a value which is approximate to a
`square root of a sum of a square of the value represented by
`the first digital signal and a square of the value represented
`by the third digital signal.
`It is preferable that the first means comprises a shift
`register for temporarily storing the first digital signal; a first 50
`latch for latching an MSB of the first digital signal; an
`Exclusive-OR circuit for executing Exclusive-OR operation
`between an output signal from the shift register and an
`output signal from the first latch; a second latch for latching
`the MSB of the first digital signal as an initial value; and a 55
`1-bit adder for adding an output signal from the Exclusive(cid:173)
`OR circuit and an output signal from the second latch, and
`generating the second digital signal; wherein the second
`latch is operative for latching a carry signal generated by the
`adder.
`It is preferable that the second means comprises a shift
`register for temporarily storing the third digital signal; a first
`latch for latching an MSB of the third digital signal; an
`Exclusive-OR circuit for executing Exclusive-OR operation
`between an output signal from the shift register and an 65
`output signal from the first latch; a second latch for latching
`the MSB of the third digital signal as an initial value; and a
`
`60
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a first prior-art calculation
`apparatus.
`FIG. 2 is a block diagram of a second prior-art calculation
`apparatus.
`FIG. 3 is a block diagram of an approximate calculation
`apparatus.
`FIG. 4 is a block diagram of a calculation apparatus
`according to a first embodiment of this invention.
`FIG. 5 is a block diagram of an absolute-value comparator
`in FIG. 4.
`FIG. 6 is a block diagram of an absolute-value calculator
`in FIG. 4.
`FIG. 7 is a block diagram of a multiplier in FIG. 4.
`FIG. 8 is a time-domain diagram of various signals in the
`absolute-value comparator of FIG. 5.
`FIG. 9 is a diagram of the relation among the values
`
`Petitioner Apple Inc.
`Ex. 1015, p. 11
`
`

`

`5,459,683
`
`3
`represented by input digital signals Sa and Sb, and the logic
`state of the output signal from a multiplexer 30 in the
`absolute-value comparator of FIG. 5.
`FIG. 10 is a diagram of the relation among the values
`represented by the input digital signals Sa and Sb, and the 5
`logic state of the output signal Sc from an Exclusive-OR
`circuit 31 in the absolute-value comparator of FIG. 5.
`FIG. 11 is a time-domain diagram of various signals in the
`absolute-value calculator of FIG. 6.
`FIG.12 is a time-domain diagram of various signals in the
`multiplier of FIG. 7.
`FIG. 13 is a block diagram of a calculation apparatus
`according to a second embodiment of this invention.
`
`4
`square "Sb2
`" of the value represented by the digital signal Sb
`and outputs an M-bit digital signal indicating the calculated
`square "Sb2
`". In this case, the adder 9 receives the output
`signal from the multiplier 7 which represents the calculated
`square "Sb2
`". At the same time, the adder 9 receives the
`output signal from the latch 8 which represents the calcu(cid:173)
`lated square "Sa2
`".
`The adder 9 calculates the sum "Sa2+Sb2
`" of the values
`"Sa2 " and "Sb2
`" represented by the output signals from the
`10 multiplier 7 and the latch 8. The adder 9 outputs an (M+l)(cid:173)
`bit digital signal indicating the calculated sum "Sa2+Sb2
`".
`The square root calculator 10 receives the output signal
`the square root
`from ~dder 9, and calculates
`"= Sa2+Sb2
`" of the value "Sa2+Sb2
`" represented by the
`15 output signal from the adder 9. The square root calculator 10
`outputs a digital signal So indicating the calculated square
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`20
`
`FIG. 3 shows an approximate calculation apparatus which
`is not prior art against this invention. As shown in FIG. 3, the
`approximate calculation apparatus includes N-bit absolute(cid:173)
`value calculators 11 and 12, an N-bit subtracter 13, N-bit
`multiplexers 14 and 15, anN-bit multiplier 16, and an M-bit
`adder 17, where "N" and "M" denote given natural numbers
`25 respectively.
`The approximate calculation apparatus of FIG. 3 is
`designed to operate on input N-bit digital signals Sa and Sb
`of a parallel form which represent an in-phase component
`and a quadrature component of a constant-envelope analog
`signal respectively. In this case, the square root of the sum
`of the square of the value "A" represented by the digital
`signal Sa and the square of the value "B" represented by the
`digital signal Sb is approximately given by the following
`equation.
`
`35
`
`Prior-art calculation apparatuses will now be described
`for a better understanding of this invention.
`FIG. 1 shows a first prior-art calculation apparatus. As
`shown in FIG. 1, the first prior-art calculation apparatus
`includes N-bit multipliers 2 and 3, an M-bit adder 4, and a
`square root calculator 5, where "N" and "M" denote given
`natural numbers respectively.
`An input N-bit digital signal Sa having a parallel form is
`applied to the multiplier 2 while another input N-bit digital
`signal Sb having a parallel form is applied to the other
`multiplier 3. The multiplier 2 calculates the square "Sa2
`" of
`the value represented by the digital signal Sa, and outputs an 30
`M-bit digital signal indicating the calculated square "Sa2
`".
`The multiplier 3 calculates the square "Sb2
`" of the value
`represented by the digital signal Sb, and outputs an M-bit
`digital signal indicating the calculated square "Sb2
`".
`The adder 4 receives the output signals from the multi(cid:173)
`pliers 2 and 3, and calculates the sum "Sa2+Sb2
`" of the
`" and '.'Sb2
`values "Sa2
`" represented by the output signals
`from the multipliers 2 and 3. The adder 4 outputs an
`(M+ 1)-bit digital signal indicating the calculated sum "Sa2+ 40
`Sb2
`".
`The square root calculator 5 receives the output signal
`the square root
`from ~dder 4, and calculates
`"= Sa2+Sb2
`" of the value "Sa2+Sb2
`" represented by the
`output signal from the adder 4. The square root calculator 5
`outputs a digital signal So indicating the calculated square
`
`FIG. 2 shows a second prior-art calculation apparatus. As
`shown in FIG. 2, the second prior-art calculation apparatus
`includes an N-bit multiplexer 6, an N-bit multiplier 7, an
`M-bit latch 8, an M-bit adder 9, and a square root calculator
`10, where "N' and "M" denote given natural numbers
`respectively.
`An input N-bit digital signal Sa having a parallel form,
`and an input N-bit digital signal Sb having a parallel form
`are applied to the multiplexer 6. The multiplexer 6 sequen(cid:173)
`tially selects the digital signal Sa or the digital signal Sb, and
`passes the selected signal to the multiplier 7. When the
`multiplexer 6 selects the digital signal Sa and passes it to the 60
`multiplier 7, the multiplier 7 calculates the square "Sa2
`" of
`the value represented by the digital signal Sa and outputs an
`M-bit digital signal indicating the calculated square "Sa2
`".
`The latch 8 receives and holds the output signal from the
`multiplier 7 which represents the calculated square "Sa2
`".
`When the multiplexer 6 selects the digital signal Sb and
`passes it to the multiplier 7, the multiplier 7 calculates the
`
`z MAX(IAI, IBI) + MIN(IAI, IBI) x (\f2 - 1)
`where MAX denotes an operator for selecting the greatest of
`two in the following parentheses, and MIN denotes an
`operator for selecting the smallest of two in the following
`parentheses.
`The input N-bit digital signal Sa is applied to the absolute(cid:173)
`value calculator 11 while the other input N-bit digital signal
`45 Sb is applied to the absolute-value calculator 12. The device
`11 calculates the absolute value "IAI" of the value "A"
`represented by the digital signal Sa, and outputs an N-bit
`digital signal indicating the calculated absolute value "IAI".
`The device 12 calculates the absolute value "IBI" of the value
`50 "B" represented by the digital signal Sb, and outputs an
`N-bit digital signal indicating the calculated absolute value
`"IBI".
`The subtracter 13 receives the output signals from the
`absolute-value calculators 11 and 12, and calculates a dif-
`55 ference between the values "IAI" and "IBI" represented by
`the received signals. The subtracter 13 decides which of the
`values "IAI" and "IBI" is greater, and outputs a digital signal
`representing the result of the decision. The subtracter 13
`may be replaced by a comparator.
`The multiplexer 14 receives the output signals from the
`absolute-value calculators 11 and 12. Also, the multiplexer
`14 receives the output signal from the subtracter 13. The
`multiplexer 14 selects one of the output signals from the
`absolute-value calculators 11 and 12 in response to the
`65 output signal from the subtracter 13, and passes the selected
`signal to the adder 17. Specifically, the multiplexer 14
`selects one of the output signals from the absolute-value
`
`(1)
`
`Petitioner Apple Inc.
`Ex. 1015, p. 12
`
`

`

`5,459,683
`
`5
`calculators 11 and 12 which corresponds to the greater of the
`values "IAI" and "IBI". Thus, the multiplexer 14 has the
`function corresponding to the term "MAX(IAI, IBI)" in the
`equation (1).
`The multiplexer 15 receives the output signals from the 5
`absolute-value calculators 11 and 12. Also, the multiplexer
`15 receives the output signal from the subtracter 13. The
`multiplexer 15 selects one of the output signals from the
`absolute-value calculators 11 and 12 in response to the
`output signal from the subtracter 13, and passes the selected 10
`signal to the multiplier 16. Specifically, the multiplexer 15
`selects one of the output signals from the absolute-value
`calculators 11 and 12 which corresponds to the smaller of the
`values "IAI" and "IBI". Thus, the multiplexer 15 has the
`function corresponding to the term "MIN(IAI, IBI)" in the 15
`equation ( 1).
`The multiplier 16 receives the output signal from the
`multiplexer 15 which represents the value "MlN(IAI, IBI)".
`Also, the multiplier 16 receives an output digital signal from
`a register or memory (not shown) which represents a fixed 20
`value of = 2-1. The multiplier 16 calculates the product of
`the value "MIN(IAI, IBI)" and the value "= 2-1", and
`outputs a digital signal indicating the calculated product
`"MIN(IAI, IBI)X(= 2-1)".
`The adder 17 receives the output signal from the multi- 25
`plexer 14 which represents the value "MAX(IAI, IBI)". Also,
`the adder 17 receives the output signal from the multiplier 16
`which represents the value "MIN(IAI, IBI)X(= 2-1)". The
`adder 17 calculates the sum of the values represented by the
`output signals from the multiplexer 14 and the multiplier 16, 30
`and outputs a digital signal So indicating the calculated sum
`"MAX(IAI, IBI)+MIN(IAI, IBI)x(= 2-1)". In this way, the
`adder 17 outputs a digital signal So representing the right(cid:173)
`hand side of the equation (1) which is approximate to the
`value"= A2+B 2
`".
`In cases where the bit number "N' of the input digital
`signals Sa and Sb is great, the prior-art calculation appara(cid:173)
`tuses of FIGS. 1 and 2 and the approximate calculation
`apparatus of FIG. 3 tend to be complicated in structure since
`the adders and the multipliers therein need large numbers of 40
`gates.
`FIG. 4 shows a calculation apparatus according to a first
`embodiment of this invention. As shown in FIG. 4, the
`calculation apparatus includes an absolute-value comparator
`20, an absolute-value calculator 21, and a multiplier 22.
`The absolute-value comparator 20 and the absolute-value
`calculator 21 are connected to the multiplier 22. Input digital
`signals Sa and Sb having a serial form are applied to the
`absolute-value comparator 20 and the absolute-value calcu(cid:173)
`lator 21. The absolute-value comparator 20 generates a 50
`digital signal Sc in response to the input digital signals Sa
`and Sb, and outputs the generated signal Sc to the multiplier
`22. The absolute-value calculator 21 generates digital sig(cid:173)
`nals Sd and Se in response to the input digital signals Sa and
`Sb, and outputs the generated signals Sd and Se to the 55
`multiplier 22. The multiplier 22 generates a digital signal So
`in response to the digital signals Sc, Sd, and Se, and outputs
`the generated digital signal So.
`As shown in FIG. 5, the absolute-value comparator 20
`includes an Exclusive-OR circuit 23, a latch 24, a NOT 60
`circuit (an inverter) 25, a 1-bit adder 26, a latch 27, a 1-bit
`adder 28, a latch 29, a multiplexer 30, and an Exclusive-OR
`circuit 31.
`The input digital signals Sa and Sb are applied to first and
`second input sides of the Exclusive-OR circuit 23 respec- 65
`tively. The output side of the Exclusive-OR circuit 23 is
`connected to the input side of the latch 24. The output side
`
`6
`of the latch 24 is connected to a control terminal of the
`multiplexer 30. The input digital signals Sa and Sb are
`applied to first and second input sides of the adder 26
`respectively. The output side of the adder 26 is connected to
`a first input side of the multiplexer 30. A carry terminal of
`the adder 26 is connected to the latch 27. The input digital
`signal Sa is applied to a first input side of the adder 28. The
`input digital signal Sb is applied to the input side of the NOT
`circuit 25. The output side of the NOT circuit 25 is con(cid:173)
`nected to a second input side of the adder 28. The output side
`of the adder 28 is connected to a second input side of the
`multiplexer 30. A carry terminal of the adder 28 is connected
`to the latch 29. The output side of the multiplexer 30 is
`connected to a first input side of the Exclusive-OR circuit
`31. A second input side of the Exclusive-OR circuit 31 is
`subjected to the input digital signal Sa. The output side of the
`Exclusive-OR circuit 31 is followed by the multiplier 22 of
`FIG. 4.
`The circuit 23 executes Exclusive-OR operation between
`the input digital signals Sa and Sb. The output signal from
`the Exclusive-OR circuit 23 is held by the latch 24 before
`being transmitted to the multiplexer 30. The device 26 adds
`the input digital signals Sa and Sb. The output signal from
`the adder 26 is fed to the multiplexer 30. The latch 27 holds
`a carry signal generated by the adder 26. The input digital
`signal Sb is inverted by the NOT circuit 25. The output
`signal from the NOT circuit 25 is applied to the adder 28.
`The device 28 adds the input digital signal Sa and the output
`signal from the NOT circuit 25. The output signal from the
`adder 28 is fed to the multiplexer 30. The latch 29 holds a
`carry signal generated by the adder 28. The multiplexer 30
`selects one of the output signals from the adders 26 and 28
`in response to the output signal from the latch 24, and passes
`the selected signal to the Exclusive-OR circuit 31. The
`35 circuit 31 executes Exclusive-OR operation between the
`input digital signal Sa and the output signal from the
`multiplexer 30. The output signal from the Exclusive-OR
`circuit 31 is used as a signal Sc fed to the multiplier 22 of
`FIG. 4.
`As shown in FIG. 6, the absolute-value calculator 21 is
`separated into first and second portions 21A and 21B which
`operate on the input digital signals Sa and Sb respectively.
`The first portion 21A of the absolute-value calculator 21
`includes a shift register 34A, a latch 35A, an Exclusive-OR
`circuit 36A, a 1-bit adder 37A, and a latch 38A.
`The input digital signal Sa is applied to the input side of
`the shift register 34A. The output side of the shift register
`34A is connected to a first input side of the Exclusive-OR
`circuit 36A. The input digital signal Sa is applied to the input
`side of the latch 35A. The output side of the latch 35A is
`connected to a second input side of the Exclusive-OR circuit
`36A. The output side of the Exclusive-OR circuit 36A is
`connected to the input side of the adder 37 A. The output side
`of the adder 37 A is followed by the multiplier 22 of FIG. 4.
`A carry terminal of the adder 37 A is connected to the latch
`38A. The input digital signal Sa is applied to the latch 38A.
`Sequential bits of the input digital signal Sa are written
`into the shift register 34A one by one, being shifted from
`storage segments to subsequent storage segments in the shift
`register 34A before being outputted from the shift register
`34A one by one. Thus, the shift register 34A delays the input
`digital signal Sa by a predetermined time. The output signal
`from the shift register 34A, that is, the delay-resultant signal,
`is fed to the Exclusive-OR circuit 36A. The highest bit (sign
`bit, MSB) of the input digital signal Sa is held by the latch
`35A before being fed to the Exclusive-OR circuit 36A. The
`circuit 36A executes Exclusive-OR operation between the
`
`45
`
`Petitioner Apple Inc.
`Ex. 1015, p. 13
`
`

`

`5,459,683
`
`15
`
`7
`output signals from the shift register 34A and the latch 35A.
`The output signal from the Exclusive-OR circuit 36A is fed
`to the adder 37 A. The highest bit (sign bit, MSB) ofthe input
`digital signal Sa is stored into the latch 38A to initialize the
`latch 38A. The device 37 A adds the output signals from the 5
`Exclusive-OR circuit 36A and the latch 38A. The latch 38A
`holds a carry signal generated by the adder 37 A. The output
`signal from the adder 37 A is used as a signal Sd fed to the
`multiplier 22 of FIG. 4.
`The second portion 21B of the absolute-value calculator 10
`21 includes a shift register 34B, a latch 35B, an Exclusive(cid:173)
`OR circuit 36B, a 1-bit adder 37B, and a latch 38B.
`The input digital signal Sb is applied to the input side of
`the shift register 34B. The output side of the shift register
`34B is connected to a first input side of the Exclusive-OR
`circuit 36B. The input digital signal Sb is applied to the input
`side of the latch 35B. The output side of the latch 35B is
`connected to a second input side of the Exclusive-OR circuit
`36B. The output side of the Exclusive-OR circuit 36B is
`connected to the input side of the adder 37B. The output side
`of the adder 37B is followed by the multiplier 22 of FIG. 4.
`A carry terminal of the adder 37B is connected to the latch
`38B. The input digital signal Sb is applied to the latch 38B.
`Sequential bits of the input digital signal Sb are written
`into the shift register 34B one by one, being shifted from
`storage segments to subsequent storage segments in the shift
`register 34B before being outputted from the shift register
`34B one by one. Thus, the shift register 34B delays the input
`digital signal Sb by a predetermined time. The output signal
`from the shift register 34B, that is, the delay-resultant signal,
`is fed to the Exclusive-OR circuit 36B. The highest bit (sign
`bit, MSB) of the input digital signal Sb is held by the latch
`35B before being fed to the Exclusive-OR circuit 36B. The
`circuit 36B executes Exclusive-OR operation between the
`output signals from the shift register 34B and the latch 35B. 35
`The output signal from the Exclusive-OR circuit 36B is fed
`to the adder 37B. The highest bit (sign bit, MSB) of the input
`digital signal Sb is stored into the latch 38B to initialize the
`latch 38B. The device 37B adds the output signals from the
`Exclusive-OR circuit 36B and the latch 38B. The latch 38B 40
`holds a carry signal generated by the adder 37B. The output
`signal from the adder 37B is used as a signal Se fe