UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`SONY CORPORATION,
`Petitioner,
`
`v.
`
`AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
`Patent Owner.
`______________________
`
`Case IPR2017-____
`Patent 5,870,087
`__________________________________________________________________
`
`PETITION FOR INTER PARTES REVIEW UNDER 37 C.F.R. § 42.100
`
`
`
`

`
`
`
`TABLE OF CONTENTS
`
`I. Mandatory Notices Under 37 C.F.R. § 42.8 ................................................ 1
`
`A.
`
`B.
`
`C.
`
`D.
`
`37 C.F.R. § 42.8(b)(1): Real Party-in-Interest ...................................... 1
`
`37 C.F.R. § 42.8(b)(2): Related Matters ............................................... 1
`
`37 C.F.R. § 42.8(b)(3): Counsel Information ........................................ 2
`
`37 C.F.R. § 42.8(b)(4): Service Information ......................................... 3
`
`II.
`
`Payment of Fees Under 37 C.F.R. § 42.103 ................................................. 3
`
`III. Grounds for Standing Under 37 C.F.R. § 42.104(a) ................................... 3
`
`IV.
`
`Identification of Challenge Under 37 C.F.R. § 42.104(b) .......................... 4
`
`A.
`
`B.
`
`C.
`
`D.
`
`E.
`
`37 C.F.R. § 42.104(b)(1): Claims for Which IPR Is Requested ........... 4
`
`37 C.F.R. § 42.104(b)(2): Grounds for Challenge ................................ 4
`
`37 C.F.R. § 42.104(b)(3): Claim Construction ..................................... 6
`
`37 C.F.R. § 42.104(b)(4): How the Claims Are Unpatentable ............. 6
`
`37 C.F.R. § 42.104(b)(5): Evidence Supporting Challenge .................. 6
`
`V.
`
`Background .................................................................................................... 7
`
`A. Overview of the ’087 Patent .................................................................. 7
`
`B.
`
`C.
`
`Overview of the Prior Art ...................................................................... 9
`
`Level of Ordinary Skill ....................................................................... 13
`
`VI. How the Challenged Claims Are Unpatentable ........................................ 13
`
`A. Ground 1: Claims 1, 7, 10-11, and 16 Are Anticipated By Fujii ........ 13
`
`1.
`
`2.
`
`3.
`
`Independent Claims 1, 10, and 16 ............................................. 13
`
`Dependent Claim 7 ................................................................... 28
`
`Dependent Claim 11 ................................................................. 29
`
`
`
`i
`
`

`
`
`
`B.
`
`Ground 2: Claims 1-3, 7, 10-13, and 16-18 are Obvious in view
`of Fujii and Bheda ............................................................................... 30
`
`1.
`
`2.
`
`3.
`
`Dependent Claims 2, 12, and 17 ............................................... 31
`
`Dependent Claims 3 and 18 ...................................................... 34
`
`Dependent Claim 13 ................................................................. 35
`
`C.
`
`Ground 3: Claim 5 is Obvious in view of Fujii and Lam .................. 36
`
`1.
`
`Dependent Claim 5 ................................................................... 37
`
`D. Ground 4: Claims 1, 7, 10-11, and 16 are Obvious in View of
`Maturi and Yao .................................................................................... 39
`
`1.
`
`2.
`
`3.
`
`4.
`
`The Combination of Maturi and Yao ........................................ 39
`
`Independent Claims 1, 10, and 16 ............................................. 41
`
`Dependent Claim 7 ................................................................... 51
`
`Dependent Claim 11 ................................................................. 53
`
`E.
`
`Ground 5: Claims 1-3, 7, 10-13, and 16-18 are Obvious in view
`of Maturi, Yao, and Bheda .................................................................. 54
`
`1.
`
`2.
`
`3.
`
`Dependent Claims 2, 12, and 17 ............................................... 55
`
`Dependents Claim 3 and 18 ...................................................... 57
`
`Dependent Claim 13 ................................................................. 58
`
`F.
`
`Ground 6: Claim 5 is Obvious in view of Maturi, Yao, and
`Lam ...................................................................................................... 58
`
`1.
`
`Dependent Claim 5 ................................................................... 59
`
`VII. Conclusion .................................................................................................... 60
`
`
`
`
`
`
`
`ii
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`

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`
`
`LIST OF EXHIBITS
`
`Description
`
`Exhibit
`1001 U.S. Patent No. 5,870,087
`1002
`File History of U.S. Patent No. 5,870,087
`1003 Declaration of Dr. Chandrajit Bajaj
`1004 U.S. Patent No. 5,898,695 (“Fujii”), filed on March 27, 1996
`
`1005 U.S. Patent No. 6,002,441 (“Bheda”), filed on October 28, 1996
`
`1006 U.S. Patent No. 5,960,464 (“Lam”), filed on August 23, 1996
`
`1007 U.S. Patent No. 5,559,999 (“Maturi”), filed on September 9, 1994 and
`issued on September 24, 1996
`
`“Unified Memory Architecture Cuts PC Cost” is an article by Yong Yao
`(“Yao”) published on June 19, 1995 in Volume 9, Issue No. 8 of
`Microprocessor Report
`
`1009 Business Wire, VESA Announces Release of Unified Memory
`Architecture Standard (March 8, 1996)
`
`1010 H.262 Standard
`
`“Fast computer memories” is an article by Ray Ng (“Ng”) published in
`October 1992 in IEEE Spectrum
`
`1008
`
`1011
`
`
`
`iii
`
`

`
`
`
`Sony Corporation (“Sony”) requests inter partes review (“IPR”) of claims 1-
`
`3, 5, 7, 10-13, and 16-18 (the “Challenged Claims”) of U.S. Patent No. 5,870,087
`
`(the “’087 Patent”), attached hereto as Exhibit 1001.
`
`I. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`A. 37 C.F.R. § 42.8(b)(1): Real Party-in-Interest
`Sony identifies the following real parties-in-interest in addition to Sony
`
`Corporation: Sony Corporation of America, Sony Interactive Entertainment
`
`America LLC, Sony Interactive Entertainment Inc., Sony Interactive Entertainment
`
`LLC, Sony Electronics, Inc., Sony Creative Software Inc., Sony Pictures Home
`
`Entertainment Inc., Sony Video & Sound Products Inc., and Sony Visual Products
`
`Inc.
`
`B. 37 C.F.R. § 42.8(b)(2): Related Matters
`Patent Owner has asserted the ’087 Patent in Broadcom Corp. et al. v. Sony
`
`Corp. et al., Case No. 16-cv-1052 (C.D. Cal. 2016). The ’087 Patent is also
`
`asserted against entities unrelated to Petitioner in Avago Techs. Gen. IP
`
`(Singapore) PTE Ltd. v. ASUSTeK Computer, Inc. et al., Case Nos. 3:15-cv- 04525
`
`(N.D. Cal., transferred from E.D. Tex) and 3:16-cv-00451 (N.D. Cal.), and in
`
`Avago Techs. Gen. IP (Singapore) PTE Ltd. v. Acer Inc., et al., Case No. 3:15- cv-
`
`05427 (N.D. Cal.). Further, the Board has instituted an IPR trial of challenged
`
`claims 1, 5, 7-11, and 16 of the ’087 Patent in IPR2016-00646. These cases may
`
`affect, or be affected by, decisions in this proceeding.
`
`1
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`

`
`
`
`C. 37 C.F.R. § 42.8(b)(3): Counsel Information
`Sony provides the following designation of counsel:
`
`Lead Counsel
`Gregory S. Arovas, P.C.
`Reg. No. 38,818
`greg.arovas@kirkland.com
`Postal and Hand-Delivery Address:
`KIRKLAND & ELLIS LLP
`601 Lexington Avenue
`New York, New York 10022
`Telephone: (212) 446-4800
`Facsimile: (212) 446-4900
`
`
`
`Backup Counsel
`F. Christopher Mizzo
`Reg. No. 73,156
`chris.mizzo@kirkland.com
`Postal and Hand-Delivery Address:
`KIRKLAND & ELLIS LLP
`655 15th Street NW
`Washington, D.C. 20005
`Telephone: (202) 879-5000
`Facsimile: (202) 879-5200
`
`Robert A. Appleby, P.C.
`Reg. No. 40,897
`robert.appleby@kirkland.com
`Postal and Hand-Delivery Address:
`KIRKLAND & ELLIS LLP
`601 Lexington Avenue
`New York, New York 10022
`Telephone: (212) 446-4800
`Facsimile: (212) 446-4900
`
`Eugene Goryunov
`Reg. No. 61,579
`eugene.goryunov@kirkland.com
`Postal and Hand-Delivery Address:
`KIRKLAND & ELLIS LLP
`300 North LaSalle Street
`Chicago, IL 60654
`Telephone: (312) 862-2000
`Facsimile: (312) 862-2200
`
`Craig T. Murray
`Reg. No. 72,978
`chris.mizzo@kirkland.com
`Postal and Hand-Delivery Address:
`KIRKLAND & ELLIS LLP
`2
`
`

`
`
`
`655 15th Street NW
`Washington, D.C. 20005
`Telephone: (202) 879-5000
`Facsimile: (202) 879-5200
`
`D. 37 C.F.R. § 42.8(b)(4): Service Information
`Sony concurrently submits a Power of Attorney, 37 C.F.R. § 42.10(b), and
`
`
`
`consents to electronic service directed to the following email addresses:
`
`
`• greg.arovas@kirkland.com,
`• chris.mizzo@kirkland.com,
`• robert.appleby@kirkland.com,
`• david.rokach@kirkland.com,
`• eugene.goryunov@kirkland.com,
`• craig.murray@kirkland.com.
`PAYMENT OF FEES UNDER 37 C.F.R. § 42.103
`
`II.
`
`The undersigned authorizes the Office to charge the fee set forth in 37
`
`C.F.R. § 42.15(a)(1) for this Petition to Deposit Account No. 506092. Review of
`
`twelve (12) claims is requested, and no claim excess fee is paid. The undersigned
`
`further authorizes payment for any additional fees that may be due in connection
`
`with this Petition to be charged to this deposit account.
`
`III. GROUNDS FOR STANDING UNDER 37 C.F.R. § 42.104(A)
`Sony certifies that the ’087 Patent is available for IPR and that Sony is not
`
`barred or estopped from requesting IPR of the Challenged Claims on the grounds
`
`identified in this Petition. Sony certifies: (1) Sony is not the owner of the ’087
`
`3
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`

`
`
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`Patent; (2) Sony (or any real party-in-interest) has not filed a civil action
`
`challenging the validity of any claim of the ’087 Patent; (3) Sony files this Petition
`
`within one year of the date it was served with a complaint asserting infringement
`
`of the ’087 Patent; (4) the estoppel provisions of 35 U.S.C. § 315(e)(1) do not
`
`prohibit this IPR; and (5) this Petition is filed after the ’087 Patent was granted.
`
`IV.
`IDENTIFICATION OF CHALLENGE UNDER 37 C.F.R. § 42.104(B)
`A. 37 C.F.R. § 42.104(b)(1): Claims for Which IPR Is Requested
`Sony requests IPR of claims 1-3, 5, 7, 10-13, and 16-18 of the ’087 Patent.
`
`B. 37 C.F.R. § 42.104(b)(2): Grounds for Challenge
`This Petition relies upon the following prior art:
`
`• Ex. 1004, U.S. Patent No. 5,898,695 (“Fujii”), filed on March 27, 1996;
`
`• Ex. 1005, U.S. Patent No. 6,002,441 (“Bheda”), filed on October 28, 1996;
`
`• Ex. 1006, U.S. Patent No. 5,960,464 (“Lam”), filed on August 23, 1996;
`
`• Ex. 1007, U.S. Patent No. 5,559,999 (“Maturi”), filed on September 9, 1994
`
`and issued on September 24, 1996;
`
`• Ex. 1008, “Unified Memory Architecture Cuts PC Cost,” an article by Yong
`
`Yao (“Yao”) published on June 19, 1995 in Volume 9, Issue No. 8 of
`
`Microprocessor Report;
`
`
`
`4
`
`

`
`
`
`• Ex. 1009, Business Wire, VESA Announces Release of Unified Memory
`
`Architecture Standard (March 8, 1996);
`
`• Ex. 1010, H.262 Standard;
`
`• Ex. 1011, “Fast computer memories,” an article by Ray Ng (“Ng”) published
`
`in October 1992 in IEEE Spectrum.
`
`IPR is requested on the following grounds:
`
`Ground Claims
`1
`1, 7, 10-11,
`16
`1-3, 7, 10-
`13, 16-18
`5
`1, 7, 10-11,
`16
`1-3, 7, 10-
`13, 16-18
`5
`
`2
`
`3
`4
`
`5
`
`Proposed Statutory Rejection
`Anticipated under 35 U.S.C. § 102 by Fujii.
`
`Obvious under 35 U.S.C. § 103 in view of Fujii and
`Bheda
`Obvious under 35 U.S.C. § 103 in view of Fujii and Lam
`Obvious under 35 U.S.C. § 103 in view of Maturi and
`Yao
`Obvious under 35 U.S.C. § 103 in view of Maturi, Yao,
`and Bheda
`Obvious under 35 U.S.C. § 103 in view of Maturi, Yao,
`and Lam
`
`6
`
`
`
`Proposed grounds 1-6 are not redundant. Ground 1, unlike grounds 2-6, is
`
`based on § 102. Likewise, grounds 2-3 and 4-6 focus on different prior art
`
`combinations and approaches to arrive at the Challenged Claims. For instance,
`
`grounds 1-3 focus on Fujii, which is directed towards using the system controller’s
`
`memory for demultiplexing and decoding. Ex. 1004 at 3:60-64; Ex. 1003 ¶ 43. On
`
`the other hand, grounds 4-6 focus on Maturi, which is directed towards a method
`
`of synchronizing video and audio decoding using a single memory. Ex. 1003 ¶ 46.
`
`
`
`5
`
`

`
`
`
`Petitioner’s proposed grounds 1-6 are also not redundant with the instituted
`
`grounds in IPR 2016-00646. None of the art in grounds 4-6 are at issue in IPR
`
`2016-00646. Likewise, Yao, Bheda and dependent claims 2-3, 12-13, and 17-18
`
`(grounds 2 and 5) are not at issue in IPR 2016-00646. While Fujii and Lam are at
`
`issue in IPR 2016-00646, Petitioner has no involvement in that IPR and is not a
`
`part of the related district court litigation. Moreover, Fujii forms the basis of
`
`Petitioner’s challenge to dependent claims 2-3, 12-13, and 17-18 in ground 2,
`
`requiring consideration of Fujii’s disclosure of independent claims 1, 10, and 16
`
`and negating any efficiencies in a redundancy denial.
`
`C. 37 C.F.R. § 42.104(b)(3): Claim Construction
`With regard to invalidity of the Challenged Claims on the proposed
`
`Grounds, no claim construction is required.
`
`D. 37 C.F.R. § 42.104(b)(4): How the Claims Are Unpatentable
`A detailed explanation of how the Challenged Claims are unpatentable is
`
`provided below in Section VI.
`
`E. 37 C.F.R. § 42.104(b)(5): Evidence Supporting Challenge
`A list of exhibits is provided above. The relevance of this evidence and the
`
`specific portions supporting the challenge is provided below in Section VI. Sony
`
`submits the declaration of Dr. Chandrajit Bajaj, Ex. 1003, in support of this
`
`Petition under 37 C.F.R. § 1.68.
`
`
`
`6
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`

`
`
`
`V. BACKGROUND
`A. Overview of the ’087 Patent
`The ’087 Patent generally relates to a single unified memory for decoding,
`
`or decompressing, video and audio data. Ex. 1001 at 1:30-34. The patent
`
`acknowledges that decoders for the Moving Pictures Experts Group (“MPEG”)-1
`
`and MPEG-2 standards existed in the art. Id. at 4:14-28; see also id. at 2:31-32
`
`(“The two predominant MPEG standards are referred to as MPEG-1 and MPEG-
`
`2.”). Such decoders “typical[ly]” included on-chip and external memory (id. at
`
`4:14-17), “transport logic which operates to demultiplex received data into a
`
`plurality of individual multimedia streams” (id. at 4:22-24), and “a system
`
`controller which controls operations in the system and executes programs or
`
`applets.” Id. at 4:25-27. The patent asserts that such “[p]rior art MPEG video
`
`decoder systems have generally” used “separate memory” for the decoder, on the
`
`one hand, and the transport and system controller logic, on the other. Id. at 4:28-
`
`35. The patent contends that it was “generally not [] possible to combine these
`
`memories, due to size limitations” and cost. Id. at 4:35-43.
`
`The patent purports to address this issue by use of a “unified memory for
`
`multiple functions” including “for the transport logic, system controller, and
`
`MPEG decoder functions.” Id. at 4:67-5:6 The claims, however, do not provide a
`
`
`
`7
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`

`
`
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`way of overcoming the memory size and cost limitations that, in the specification’s
`
`words, made it impractical or impossible to combine the separate memories.
`
`Representative independent claim 1 reads:
`
`As seen, claim 1 contains multiple limitations that are very similar to each other,
`
`such as “wherein the memory is used by the MPEG decoder during MPEG
`
`decoding operations” and “wherein the MPEG decoder is operable to access the
`
`
`
`
`
`8
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`

`
`
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`memory during MPEG decoding operations.” Petitioner’s detailed analysis of the
`
`independent claims groups limitations where appropriate.
`
`B. Overview of the Prior Art
`U.S. Patent No. 5,898,695 (“Fujii”) is entitled “Decoder for Compressed and
`
`Multiplexed Video and Audio Data” and was filed on March 27, 1996. Ex. 1004 at
`
`[22]. It claims priority to two Japanese patent applications, both filed on March
`
`29, 1995. Id. at [30]. Fujii is prior art under 35 U.S.C. § 102(e).1 Fujii “provide[s]
`
`a decoder for compressed and multiplexed video and audio data, wherein packet
`
`landing buffers are allocated in a RAM used by a CPU for the system control to
`
`thereby reduce the number of components and lower the cost of components.” Id.
`
`at 3:60-64. Annotated Figure 11 of Fujii shows the transport logic (turquoise),
`
`system controller (green), decoder (orange), and single memory (red):
`
`
`1 Because the ’087 Patent has a filing date before March 16, 2013, the pre-AIA
`
`versions of §§ 102 and 103 apply to this petition.
`
`
`
`9
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`

`
`
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`
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`Id. at Fig. 11 (annotated). In IPR2016-00646 the Board instituted an IPR of claims
`
`1, 7, 10, 11, and 16 of the ’087 Patent based on Fujii. IPR 2016-00646 Institution
`
`Decision at 21.
`
`U.S. Patent No. 5,559,999 (“Maturi”) is entitled “MPEG Decoding System
`
`Including Tag List for Associating Presentation Time Stamps with Encoded Data
`
`Units.” Ex. 1007 at [54]. Maturi was filed on September 9, 1994 and issued on
`
`September 24, 1996. It is therefore prior art under 35 U.S.C. § 102(a).2 Maturi
`
`discloses “a decoding system for a [MPEG] multiplexed audio/video bitstream”
`
`that includes a “host microcontroller” and a “decoder.” Ex. 1007 at 2:47-54.
`
`
`2 While Maturi and the ’087 Patent share the same assignee, Maturi was invented
`
`“by another”—G. Maturi, D. Auld, and D. Neuman (Ex. 1007 at [75])—while the
`
`’087 Patent’s inventor is Kwok Kit Chau. Ex. 1001 at [75].
`
`
`
`10
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`

`
`
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`Maturi discloses the “decoder 16 and the microcontroller 18 have access” to the
`
`same “Dynamic Random Access Memory (DRAM) 20.” Id. at 4:55-60; id. at Figs.
`
`1, 3. Annotated Figure 3 of Maturi depicts the claimed transport logic (turquoise),
`
`system controller (green), decoder (orange), and single memory (red):
`
`
`
`Ex. 1007 at Fig. 3.
`
`U.S. Patent No. 5,960,464 (“Lam”) was filed on August 23, 1996 and is
`
`prior art to the ’087 Patent under 35 U.S.C. § 102(e). Ex. 1006 at [22]. Lam is
`
`entitled “Memory Sharing Architecture for a Decoding In a Computer System.”
`
`Id. at [75]. Lam recognizes that prior art MPEG decoders included “a large
`
`amount (e.g., 2 megabytes) of memory” and that “[s]uch chip sets can be
`
`expensive.” Id. a 2:19-22. Lam states that “it would be desirable to employ the
`
`main memory of the computer” for decoding. Id. at 2:22-23.
`
`U.S. Patent No. 6,002,441 (“Bheda”) was filed on October 28, 1996 and is
`
`
`
`11
`
`

`
`
`
`prior art to the ’087 Patent under 35 U.S.C. § 102(e). Ex. 1005 at [22]. Bheda is
`
`entitled “Audio/Video Subprocessor Method and Structure” (id. at [54]) and relates
`
`to a “novel apparatus and method for decompressing or ‘decoding’ compressed
`
`digital audio/video signals in a highly efficient manner.” Id. at 1:6-9. It discloses
`
`a host processor that performs “pre-processing tasks” such as “demultiplexing” (id.
`
`at 3:46-55) and a subprocessor that performs post-processing tasks such as
`
`decoding.
`
` Id. at 5:11-19 (performs discrete cosine
`
`transform, motion
`
`compensation, and more); see also Ex. 1003 ¶ 25 (those algorithms are part of
`
`MPEG decoding). Each can use system memory 140 (Ex. 1005 at 5:59-66), and
`
`the subprocessor includes a memory controller to also access external DRAM. Id.
`
`at 7:28-30. Notably, Bheda also discloses that system memory and DRAM can be
`
`“combined as a single memory unit” (id. at 11:20-22), at which point the DRAM
`
`controller 174 would be used by the host processor to access DRAM.
`
`“Unified Memory Architecture Cuts PC Cost” is an article by Yong Yao
`
`(“Yao”) published on June 19, 1995 in Volume 9, Issue No. 8 of Microprocessor
`
`Report and is prior art under 35 U.S.C. § 102(b). Yao describes the many benefits
`
`of a “unified memory architecture (UMA)”, such as lower cost, power
`
`
`
`12
`
`

`
`
`
`consumption, and chip size. Ex. 1008 at 33. Yao explains that UMA “will soon
`
`become a dominant PC approach” (id. at 4) and “that, 18 months from now, the
`
`UMA approach will be dominant for all PCs but high-end desktops.” Id. at 5.
`
`C. Level of Ordinary Skill
`A person of ordinary skill in the art (“POSA”) at the time of the alleged
`
`invention would have had at least a bachelor’s degree in Electrical Engineering,
`
`Computer Engineering, or Computer Science, and at least two years of experience
`
`in the design and development of multimedia processor systems utilizing memory.
`
`Ex. 1003 ¶ 35.
`
`VI. HOW THE CHALLENGED CLAIMS ARE UNPATENTABLE
`A. Ground 1: Claims 1, 7, 10-11, and 16 Are Anticipated By Fujii
`1.
`Independent Claims 1, 10, and 16
`a. Claim 1, preamble: “An MPEG decoder system which
`includes a single memory for use by transport, decode and
`system controller functions, comprising:”
`
`Claim 10, preamble: “A method for performing video
`decoding in an MPEG decoder system which includes a
`single memory for use by transport, decode and system
`controller functions, the method comprising:”
`Claim 16, preamble: “A video decoder system which
`includes a single memory for use by transport, decode and
`system controller functions, comprising:”
`
`3 Petitioner’s citations to non-patent Exhibits refer to the sequential numbers added
`
`by Petitioner for purposes of this Petition.
`
`
`
`13
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`

`
`
`
`The preambles of claims 1, 10, and 16 are not limiting as they fail to give
`
`life, meaning, or vitality to the claims. Intirtool Ltd. v. Texar Corp., 369 F.3d
`
`1289, 1295 (Fed. Cir. 2004) (“In general, a claim preamble is limiting if it recites
`
`essential structure or steps, or if it is necessary to give life, meaning, and vitality to
`
`the claim.”) (internal quotations omitted); Ex. 1003 ¶ 52. However, to the extent
`
`they are limiting, the preambles are satisfied. Ex. 1003 ¶ 53. Fujii discloses an
`
`MPEG decoder system, which is a specific type of video decoder, that includes a
`
`single memory (RAM) for use by transport, decode, and system controller
`
`functions. Fujii notes that the MPEG standard is a “well known” method of
`
`encoding video, Ex. 1004 at 1:13-18, and explains that its invention is intended to
`
`address the “problems of an increased number of system components and an
`
`increased cost” in prior art MPEG decoder systems. Id. at 2:58-63. That solution
`
`includes a single RAM for use by the transport, decode, and system controller. Id.
`
`at 3:60-64; see also id. at Fig. 11 (depicting single RAM 7). How the transport,
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`decode, and system controller modules use this RAM is described further below.
`
`b. Claim 1[a]4: “a channel receiver for receiving and MPEG
`encoded stream;”
`
`Claim 10[a]: “receiving an MPEG encoded stream”
`Claim 16[a]: “a channel receiver for receiving an encoded
`video stream;”
`
`4 Element letters are added for ease of reference.
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`
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`14
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`

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`
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`Fujii discloses a channel receiver for receiving an MPEG encoded stream.
`
`Specifically, Fujii discloses a “tuner” that “selects data of one channel transmitted
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`from a communications medium such as a CATV and a communications satellite,
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`and supplies the selected channel data to a demodulator.” Ex. 1004 at 6:1-5; id. at
`
`Fig. 1 (box 1), Fig. 11 (box 1). That data stream includes “TS packet[s]” (id. at
`
`6:9-10) defined by the MPEG standard. Id. at 1:31-36; Ex. 1003 ¶¶ 54-55.
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`c. Claim 1[b]: “transport logic coupled to the channel receiver
`which demultiplexes one or more multimedia data streams
`from the encoded stream;”
`
`Claim 10[b]: “demultiplexing one or more multimedia data
`streams from the encoded stream,”
`Claim 16[b]: “transport logic coupled to the channel receiver
`which demultiplexes one or more multimedia data streams
`from the encoded stream;”
`Fujii discloses transport logic coupled to the channel receiver which
`
`demultiplexes one or more multimedia data streams from the encoded stream.
`
`Fujii’s “transport logic” is the Program Packet Filter (box 15) and Interface Unit
`
`(box 14) of Figure 11. Ex. 1003 ¶¶ 56-58. Fujii’s tuner (“channel receiver”)
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`transmits the encoded stream to the demodulator (Ex. 1004 at 6:2-5), than to RAM
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`(Ex. 1003 ¶ 73) where it is sent to “program packet filter 15.” Ex. 1004 at 9:14-16.
`
`The “program packet filter 15 derives from transmitted TS [transport stream]
`
`packets a PSI packet and a TS packet containing an element of the user selected
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`program . . . and supplies the filtered packets to the interface unit.” Id. at 9:16-19.
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`
`
`15
`
`

`
`
`
`The Program Packet Filter performs the algorithm of Figure 15 (id. at 10:8-13),
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`using a PID stored in RAM (S1) to demultiplex the encoded stream into a video
`
`stream (S5 and S6) and audio stream (S5 and S7). Id. at Fig. 15; id. at 7:10-11
`
`(“packet filtering (or demultiplexing) process in accordance with the algorithm
`
`illustrated in FIG. 7”); see also id. at 10:11-13 (“The processes of S5 to S9 after
`
`the packet PID is fetched are the same as FIG. 7.”); Ex. 1003 ¶¶ 57-58. The
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`Program Packet Filter sends the data to the transfer buffer of the Interface Unit,
`
`which saves demultiplexed streams to the RAM. Id. ¶ 58; Ex. 1004 at 9:23-25,
`
`9:47-50, 9:59-65; see also id. at 6:10-13; id. at Fig. 14; id. at 11:42-44 (“The
`
`channel demultiplexer 202 shown in FIG. 17 corresponds to the circuit constituted
`
`by the program packet filter 15 and interface unit 14 shown in FIG. 11.”)
`
`d. Claim 1[c]: “a system controller coupled to the transport
`logic which controls operations within the MPEG decoder
`system;”
`
`Claim 10[c]: “a system controller controlling operations
`within the MPEG decoder system,”
`Claim 16[c]: “a system controller coupled to the transport
`logic which controls operations within the video decoder
`system;”
`Fujii discloses a system controller coupled to the transport logic which
`
`controls operations within the MPEG decoder system. Fujii’s “system controller”
`
`is microprocessor (box 12) shown in Figure 11 as coupled to the Program Packet
`
`Filter (box 15) and Interface Unit (box 14). Ex. 1004 at Fig. 11. The
`
`
`
`16
`
`

`
`
`
`microprocessor provides “system control.” Id. at 10:14; id. at 3:60-64 (“a RAM
`
`used by a CPU for the system control”). For instance, it schedules data moves (id.
`
`at 6:10-13, 9:47-50) and handles interrupts. Id. at 6:43-45, 9:42-46; Ex. 1003 ¶ 60.
`
`e. Claim 1[d]: “an MPEG decoder coupled to receive one or
`more multimedia data streams output from the transport
`logic, wherein the MPEG decoder operates to perform
`MPEG decoding on the multimedia data streams; and”
`
`Claim 10[d]: “performing MPEG decoding on
`multimedia data streams,”
`Claim 16[d]: “a video decoder coupled to receive one or
`more multimedia data streams output from the transport
`logic, wherein the video decoder operates to perform video
`decoding on the multimedia data streams; and”
`Fujii discloses an MPEG decoder coupled to receive one or more multimedia
`
`the
`
`data streams output from the transport logic, wherein the MPEG decoder operates
`
`to perform MPEG decoding on the multimedia data streams. Fujii’s Video
`
`Decoder (box 8) and Audio Decoder (box 10) of Figure 11 are an MPEG decoder.
`
`Ex. 1003 ¶¶ 61-63. Each is coupled to a data bus to receive multimedia data
`
`streams outputted from the transport logic (Program Packet Filter and Interface
`
`Unit). Ex. 1004 at Fig. 11. The transport logic outputs the demultiplexed
`
`multimedia data streams and saves them to RAM (id. 9:59-61) so that the
`
`“decoders” only receive filtered (i.e., demultiplexed) streams. Id. at 10:8-11; see
`
`also id. at 4:12-14. The “video data” and “audio data” are supplied to the decoders
`
`
`
`17
`
`

`
`
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`from RAM “via the bus.” Id. at 4:55-57; Ex. 1003 ¶ 61. The decoder “expands
`
`and decodes the encoded video data” and audio data. Ex. 1004 at 4:60-65.
`
`f. Claim 1[e]: “a memory coupled to the MPEG decoder,”
`Claim 16[e]: “a memory coupled to the video decoder,”
`Fujii discloses a memory coupled to the MPEG decoder. Figure 11 depicts
`
`the Video decoder (box 8) and Audio decoder (box 10) coupled to the “RAM”
`
`(box 7) through the “DATA BUS.” Ex. 1004 at Fig. 11; Ex. 1003 ¶ 64. Fujii
`
`explains that the “encoded stream” is “stored via the bus access means and the bus
`
`into the random access memory” and “via the bus the video data is supplied to the
`
`video data decoding means” and the “audio data decoding means.” Ex. 1004 at
`
`4:51-57.
`
` Fujii further explains that this “RAM” is used by both the
`
`“microprocessor for system control” and as the source of “data [that] can be
`
`supplied to the decoders.” Id. at 10:14-16.
`
`g. Claim 1[f]: “wherein the memory is used by the MPEG
`decoder during MPEG decoding operations,”
`
`Claim 1[g]: “wherein the MPEG decoder is operable to
`access the memory during MPEG decoding operations;”
`Claim 10[f]5: “wherein said . . . performing MPEG decoding
`. . . use said first unified memory”
`Claim 10[g]: “wherein said performing MPEG decoding
`
`
`5 Method claim 10 lacks an element analogous to 1[e] and 16[e]. Petitioner
`
`therefore skips reference to a 10[e] so that the following elements remain align.
`
`
`
`18
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`

`
`
`
`operates using said first unified memory”
`Claim 16[f]: “wherein the memory is used by the video
`decoder during video decoding operations,”
`Claim 16[g]: “wherein the video decoder is operable to
`access the memory during video decoding operations;”
`Fujii discloses wherein the memory is used by the MPEG decoder during
`
`MPEG decoding operations, and the decoder is operable to access the memory
`
`during MPEG decoding operations. Ex. 1003 ¶¶ 65-68. Fujii discloses the use of
`
`packet transport buffers to “convert the bit rates” of the multimedia stream so that
`
`the decoder’s buffers do not overflow. Ex. 1004 at 2:54-60. These packet
`
`transport buffers, also referred to as “packet landing buffers,” are in RAM. Id. at
`
`3:60-64; see also id. at Fig. 11 (box 71). Data from the packet landing buffers is
`
`provided to the MPEG decoder so that it can be decoded. Id. at 10:13-16; see also
`
`id. at 8:20-27; Ex. 1003 ¶ 65.
`
`Further, the MPEG decoder uses RAM during the decoding process because
`
`the RAM is used to synchronize the display of the decoded data. Fujii explains
`
`that there is a video delay time, “Tvid,” and an audio delay time, “Taud,” between
`
`the decoding of data and the presentation of that decoded data. Ex. 1004 at 8:1-14.
`
`“In order to synchronize video and audio, the microprocessor 12 is required to
`
`adjust a difference Tadj between Tvid and Taud.” Id. at 8:12-14. The
`
`microprocessor uses “delay buffer 74” in RAM 7 “to realize synchronized
`
`outputs.” Id. 8:14-16. More specifically, “the timing when the data is supplied to
`
`
`
`19
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`

`
`
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`the video or audio decoder is delayed by Tadj.” Id. at 8:18-20. Therefore, one
`
`portion of the MPEG decoder (e.g. Video Decoder 86) will receive data from RAM
`
`and begin the decoding process, during which another portion of the MPEG
`
`decoder (e.g. Audio Decoder 10) will receive data from RAM to decode. Ex. 1003
`
`¶ 66; see also Ex. 1004 at 10:17-21 (“The secondary advantage is that
`
`synchronization control can be performed by software because RAM has the delay
`
`buffer 74 as shown in FIG. 1 for the compensation for asynchronization between
`
`video and audio to be caused by delays inherent to the decoders and system.”).
`
`h. Claim 1[h]: “wherein the memory stores code and data
`useable by the system controller which enables the system
`controller to perform control functions within the MPEG
`decoder system,”
`
`Claim 1[i]: “wherein the system controller is operable to
`access the memory to retrieve code and data during system
`control functions.”
`Claim 10[h]: “said controlling operations each use said first
`unified memory.”
`Claim 10[i]: “wherein said controlling operations accesses
`code and data from said first unified memory;”
`
`6 While claim 16 refers to a “video decoder,” the ’087 specification states that is
`
`preferably “an MPEG decoder.” Ex. 1001 at 6:42-52. The specification further
`
`states that this “MPEG decoder” can “include[] an MPEG audio visual decoder
`
`224.” Id. at 8:48-50. A POSA would thus understand claim 16’s video decoder to
`
`encompass an audio-video decoder. Ex. 1003 ¶ 68.
`
`
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`20
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`

`
`
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`Claim 16[h]: “wherein the memory stores code and data
`useable by the system controller which enables the system
`controller to perform control functions within the video
`decoder system,”
`Claim 16[i]: “wherein the system controller is operable to
`access the memory to retrieve code and data during system
`control functions.”
`Fujii discloses wherein the memory stores code and data useable by the
`
`system controller which enables the system controller to perform control functions
`
`within the MPEG decoder system, and wherein the system controller is operable