Paper 1
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`———————
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`———————
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`HTC CORPORATION and HTC AMERICA, INC.,
`Petitioners,
`
`v.
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`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner
`
`———————
`
`Case IPR2017-00513
`U.S. Patent No. 5,960,464
`
`———————
`
`
`
`PETITION FOR INTER PARTES REVIEW
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`———————
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`———————
`
`HTC CORPORATION and HTC AMERICA, INC.,
`Petitioners,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner
`
`———————
`
`Case IPR2017-00513
`U.S. Patent No. 5,960,464
`
`———————
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`
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`
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`
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`TABLE OF CONTENTS
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`I.
`
`INTRODUCTION ............................................................................................. 1
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`II. MANDATORY NOTICES ............................................................................... 1
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`A. Real Party-in-Interest ................................................................................ 1
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`B. Related Matters ......................................................................................... 1
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`C. Lead and Back-up Counsel and Service Information .............................. 2
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`III. GROUNDS FOR STANDING .......................................................................... 2
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`IV. THE CHALLENGED CLAIMS ARE UNPATENTABLE .............................. 3
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`A. The ’464 Patent ......................................................................................... 3
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`1. Overview .......................................................................................... 3
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`2.
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`Prosecution History .......................................................................... 8
`
`B.
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`Identification of Challenges ..................................................................... 9
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`1. Challenged Claims ........................................................................... 9
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`2.
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`Statutory Ground for Challenges ..................................................... 9
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`3. Redundancy ...................................................................................... 9
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`C. Claim Construction ................................................................................. 11
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`i.
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`ii.
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`“a processor controlled by an operating system” ................... 13
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`“translate”/ “translating” ......................................................... 13
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`iii. “algorithmically translate the noncontiguous addresses to the
`contiguous addresses” ............................................................. 13
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`1.
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`Identification of How the Claims Are Unpatentable ..................... 14
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`
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
`
`i.
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`Challenge #1: Claims 1, 3-4, 7-8, 10, 12-13, 16-17, and 19-23
`are obvious under 35 U.S.C. § 103 over Gulick and Nale ..... 14
`
`(a) Summary of Gulick ......................................................................... 14
`(b) Summary of Nale ............................................................................ 16
`(c) Reasons to Combine Gulick and Nale ............................................ 19
`(d) Detailed Analysis ............................................................................ 21
`V. CONCLUSION ................................................................................................ 56
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`Certificate Of Service................................................................................................. 3
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`I.
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`INTRODUCTION
`HTC Corporation and HTC America, Inc. (“HTC”) respectfully request inter
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`partes review of claims 1, 3-4, 7-8, 10, 12-13, 16-17, and 19-23 of U.S. Patent No.
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`5,960,464 (“the ’464 patent”) (Ex1001). Apple Inc. previously filed a petition for
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`inter partes review of the 464 patent, which was instituted on December 5, 2016.
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`See IPR2016-01121 (“the Apple 464 IPR”). This petition presents patentability
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`challenges that are substantively identical to those in the Apple 464 IPR, and relies
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`on the same evidence and the same expert testimony. Accordingly, Petitioners
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`request a determination that this petition warrants institution on the same grounds
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`as the instituted grounds in the Apple 464 IPR, and concurrently moves under 35
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`U.S.C. § 315(c) to join this proceeding to the instituted Apple 464 IPR. See Paper
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`2 (Petitioners’ Motion for Joinder).
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`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`The real parties-in-interest are HTC Corporation and HTC America, Inc.
`
`B. Related Matters
`The ’464 Patent has been asserted in the following district court
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`proceedings: PUMA LLC v. LG Electronics MobileComm, USA, No. 2:15-cv-
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`01950 (E.D. Tex.); PUMA LLC v. Huawei Techs. Co., Ltd. et al., No. 2:14-cv-
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`00687-JRG-RSP (E.D. Tex.); PUMA LLC v. Motorola Mobility, Inc., No. 2:14-cv-
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`00689-JRG-RSP (E.D. Tex.); PUMA LLC v. HTC Corp. et al., No. 2:14-cv-00690-
`
`
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`1
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`
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`RSP (E.D. Tex.); PUMA LLC v. LG Elecs., Inc. et al., No. 2:14-cv-00691-JRG-
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`RSP (E.D. Tex.); PUMA LLC v. Samsung Elecs. Co., Ltd. et al., No. 2:14-cv-
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`00902-JRG-RSP (E.D. Tex.); PUMA LLC v. Qualcomm Inc. et al., No. 2:14-cv-
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`00930-JRG-RSP (E.D. Tex.); PUMA LLC v. ZTE Corp. et al., No. 2:15-cv-00225-
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`JRG-RSP (E.D. Tex.); and PUMA LLC v. Apple, Inc., No. 2:15-cv-00621-JRG-
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`RSP (E.D. Tex.).
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`Additionally, the ’464 Patent has been challenged in the following inter
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`partes
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`review proceedings:
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`IPR2015-01946
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`(terminated);
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`IPR2016-00665
`
`(terminated);
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`IPR2016-00848
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`(instituted);
`
`IPR2016-00924
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`(instituted), and
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`IPR2016-01121 (instituted).
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`C. Lead and Back-up Counsel and Service Information
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`Lead counsel is Joseph A. Micallef (Reg. No. 39,772). Backup counsel is
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`Samuel A. Dillon (Reg. No. 65,197). Service information: Sidley Austin LLP,
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`1501 K Street, N.W., Washington, D.C. 20005. Telephone: 202-736-8492, Fax:
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`202-736-8711, E-mail: iprnotices@sidley.com. Petitioners consent to electronic
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`service.
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`III. GROUNDS FOR STANDING
`Petitioners certify that the ’464 patent is available for inter partes review
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`and that they are not barred or estopped from requesting an inter partes review
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`challenging the patent claims on the grounds identified in the petition. Neither
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`
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`2
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`Petitioners, nor any party in privity with Petitioners, have filed a civil action
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`challenging the validity of any claim of the ’464 patent. See 35 U.S.C. § 315(a)(1).
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`While Petitioners were served with a complaint alleging infringement of the ’464
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`patent more than one year before the date this petition is filed, the time limitation
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`of 35 U.S.C. § 315(b) “shall not apply to a request for joinder under” 35 U.S.C. §
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`315(c). Because this petition is accompanied by a Motion for Joinder (Paper 2), it
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`complies with 35 U.S.C. § 315(b). See, e.g., Dell Inc. v. Network-1 Security
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`Solutions, Inc., IPR2013-00385, Paper 17 at 4-5.
`
`IV. THE CHALLENGED CLAIMS ARE UNPATENTABLE
`As explained below and in the declaration of Dr. Robert Colwell, Ph.D., the
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`concepts described and claimed in the ’464 Patent were not novel. See Ex. 1003.
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`This petition explains where each element of claims 1, 3-4, 7-8, 10, 12-13, 16-17,
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`and 19-23 is found in the prior art and why the claims would have been obvious to
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`a person of ordinary skill in the art before the earliest claimed priority date of the
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`’464 Patent. As explained below, the Board should institute trial and cancel the
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`challenged claims as unpatentable.
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`A. The ’464 Patent
`1. Overview
`The ’464 Patent was filed on August 23, 1996. The ’464 Patent has 40
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`claims in total, including independent claims 1, 10, 19, 25, and 32.
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`3
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`The ’464 Patent generally describes computer systems that employ memory
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`
`
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`management techniques that interact with the operating system of the computer
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`system to share use of the main memory in possibly noncontiguous blocks. Ex.
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`1001, Abstract, 3:11-16. The memory management techniques represent the
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`noncontiguous blocks as contiguous blocks to a decoder. Id. at Abstract, 3:28-33.
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`The ’464 Patent acknowledges that MPEG 1, MPEG 2, H.261, and H.263 were
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`already known techniques at the time of filing of the ’464 Patent. Id. at 1:46-50;
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`Ex. 1003, ¶ 23.
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`
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`“MPEG 2 decoding requires 2 megabytes of contiguous memory,” but
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`“Windows 95 allocates small blocks of memory (typically “pages” of 4 kilobytes
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`each) that are scattered throughout the main memory.” Ex. 1001, 2:59-63. The
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`’464 Patent allegedly addresses these problems by a memory management system
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`with a microcontroller that requests pages from the operating system. Id. at 3:11-
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`14. The microcontroller “employs [a] lookup table to translate one of the 2-
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`megabyte contiguous addresses to its appropriate page in the main memory,” that
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`may not be contiguous. Id. at 3:31-33. The ’464 Patent explains that its proposed
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`solution results in “the video decoder circuit” being able to “perform operations on
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`what appears to be a 2-megabyte continuous block of main memory” even where
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`that is not the case. Id. at 3:28-31; Ex. 1003, ¶¶ 24-26.
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`
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`4
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`FIG. 1 of the ’464 Patent illustrates a computer system containing a decoder
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`
`
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`114. The MPEG2 decoder 114 “decodes the compressed video images from the
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`DVD CD-ROM player 112 to reconstruct the original, uncompressed video images
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`so that they can be displayed on the CRT 110.” Ex. 1001, 4:31-35.
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`Id. at FIG. 1; Ex. 1003, ¶ 27.
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`FIG. 2 of the ’464 Patent focuses on the MPEG2 decoder 114:
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`5
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`Ex. 1001, FIG. 2.
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`
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`FIG. 2 shows the “video decoding circuit 126” and the “audio decoding
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`circuit 128,” which are described as being “of conventional construction.” Id. at
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`5:3-5 (emphasis added). The memory 129 stores a lookup table or memory map,
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`and a memory sharing routine is performed by the microcontroller 120 in
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`cooperation with a Windows 95 operating system. Id. at 5:8-9; 6:63-65. The
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`routine includes “request[ing] from the Windows 95 operating system 152, 2
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`megabytes of the main memory 106.” Id. at 7:5-7. The blocks of memory are
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`returned from the Windows 95 operating system in sizes ranging from the full 2
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`
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`6
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`megabyte block, smaller 1 megabyte blocks, or smaller 500 kilobyte blocks. Id. at
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`7:16-28; Ex. 1003, ¶¶ 28, 29.
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`
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`The ’464 Patent states that, as part of the routine, the microcontroller 120
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`programs a lookup table (in the memory 129) “based on the page descriptors of the
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`blocks of the 500 pages of memory.” Ex. 1001, 7:40-43. As an alternative to the
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`lookup table, the ’464 Patent relies upon the MMU 122 to “algorithmically map[] a
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`contiguous address to a noncontiguous address in the main memory 106.” Id. at
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`8:15-23. When the microcontroller 120 determines that the MPEG 2 decoding
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`application is interrupted or terminated, the microcontroller 120 informs the
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`Windows 95 operating system that the application has terminated and, “[a]s a
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`result, the 2 megabytes of memory from the main memory 106 are released to the
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`Windows 95 operating system 152.” Id. at 8:45-57; Ex. 1003, ¶¶ 30, 31.
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`In claim 1 of the ’464 Patent, which is exemplary, a “decoding circuit” is
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`coupled to receive/decode encoded data from a storage device. The ’464 Patent
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`states that “data” is routed from a DVD CD-ROM disk, mentions “playback of
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`video from the DVD CD-ROM disk,” and states that decoding is of “different
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`packets of video [and audio].” Ex. 1001, 5:28-31, 5:49-53, 6:1-9, 6:17-20. Further,
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`a “control circuit” is coupled to the decoding circuit, a processor, and a main
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`memory. According to the ’464 Patent, the “microcontroller 120” performs a
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`7
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`“memory sharing routine” that includes the aspects described in claim 1. Id. at
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`6:63-66; Ex. 1003, ¶¶ 32-34.
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`
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`As discussed below in more detail, the system presented in the ’464 Patent—
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`sharing a memory between multiple devices and translating between contiguous
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`and non-contiguous addresses—was well known to persons of ordinary skill in the
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`art before the earliest alleged priority date of the ’464 Patent. Ex. 1003, ¶¶ 35-36.
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`2.
`Prosecution History
`The ’464 Patent issued on September 28, 1999 from Application No.
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`08/701,890 which was filed on Aug. 23, 1996.
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`The claims were rejected in a Non-Final Office Action that was mailed on
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`September 29, 1998, identifying claims 1-24 as allowed and claims 25-40 as
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`obvious over U.S. Pat. No. 5,301,287 to Herrell. Ex. 1002, pp. 43-48. In response
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`to the rejection, Applicant added “translating the noncontiguous addresses to
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`contiguous addresses of a block of memory” with the argument that it avoids
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`needing onboard memory chips for graphic microcontrollers and video cards. Id. at
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`pp. 56-61. The Examiner allowed the application in response to the amendment
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`and arguments filed for the remaining claims. Id. at pp. 62-65.
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`As illustrated herein, Nale teaches an address translator in a system that
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`shares a system memory between a graphics controller and a CPU that perform just
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`these functions in combination with Gulick which provides a chipset and MPEG
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`
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`8
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`decoding devices that can share a main memory with a CPU. Neither Gulick nor
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`Nale were not considered by the Examiner when examining the claims of the ’464
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`Patent.
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`B.
`
`Identification of Challenges
`1.
`Challenged Claims
`Claims 1, 3-4, 7-8, 10, 12-13, 16-17, and 19-23 of the ’464 Patent are
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`challenged in this petition.
`
`2.
`Statutory Ground for Challenges
`Challenge #1: Claims 1, 3-4, 7-8, 10, 12-13, 16-17, and 19-23 are obvious
`
`under 35 U.S.C. § 103 over U.S. Patent No. 5,797,028 to Gulick et al. (“Gulick”)
`
`in view of U.S. Patent No. 5,793,385 to Nale (“Nale”).
`
`Gulick was filed September 11, 1995, and issued August 18, 1998, and for
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`purposes of this Petition is prior art to the ’464 Patent at least under (pre-AIA) 35
`
`U.S.C. § 102(e). Nale was filed June 12, 1996 and issued August 11, 1998, and for
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`purposes of this Petition is prior art to the ’464 Patent at least under (pre-AIA) 35
`
`U.S.C. § 102(e).
`
`3.
`Redundancy
`The ’464 Patent is currently the subject of inter partes review proceedings
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`IPR2016-00848, IPR2016-00924, and IPR2016-01121 (to which joinder is sought).
`
`The challenges presented in the instant petition rely on different prior art
`
`combinations, different arguments regarding the asserted prior art, and different
`
`
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`9
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`
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
`
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`expert declaration testimony than those relied upon in IPR2016-00848 and
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`IPR2016-00924. See, e.g., Nestle USA, Inc., v. Steuben Foods, Inc., IPR2014-
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`01235, Paper 12 at 7 (PTAB 2014) (declining to deny petition under § 325(d)
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`where petition relied on “combination of references previously not considered and
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`[was] supported by a declaration previously not considered”); see also Tandus
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`Flooring, Inc. v. Interface, Inc., IPR2013-00333, Paper 16 at 6 (PTAB 2013)
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`(declining to deny petition under § 325(d) where Petitioner presented new
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`declaration evidence).
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`The arguments presented in the present petition could not have been
`
`presented in IPR2016-00848 because that filing sought joinder with already-
`
`instituted IPR2015-01946. When filing a petition with a motion to join, the
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`conditions for joinder can be satisfied by filing substantively identical grounds. See
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`Sony Corp. v. Memory Integrity, LLC, IPR2015-01353, Paper 11 at 4-6
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`(determining that the conditions for joinder were satisfied because the grounds
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`asserted were substantively identical to those instituted with the same prior art,
`
`arguments, and evidence). Accordingly, Petitioners filed IPR2016-00848 on April
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`6, 2016 as a “copycat” Petition. Because Petitioners sought a motion to join,
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`Petitioners limited the grounds therein so that such petition maintained identical
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`grounds to the petition filed in IPR2015-01946 by Samsung.
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`Moreover, the art and arguments in the present petition are not substantially
`
`
`
`10
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`
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
`
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`the same as the IPR2016-00848. The IPR2016-00848 copycat petition relies upon
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`Notarianni, which describes a “compact disc player with fragment memory
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`management.” However, the present petition is based on Gulick, which more
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`particularly describes a substantively different technology, namely a “computer
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`system having an improved digital and analog configuration.” Gulick more closely
`
`aligns with the technology space alleged by Patent Owner to be infringed in district
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`court. The prior art, combinations, arguments, and expert declaration testimony in
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`the present petition are therefore different from that relied upon in IPR2016-00848
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`filed previously by Petitioners. See, e.g., Valeo N. Am., Inc. v. Magna Elecs., Inc.,
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`IPR2014-01206, Paper 13 at 11 (declining under § 325(d) to find the art and
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`arguments in the petition to be the same or substantially the same where the same
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`petitioner had filed a prior petition against the same patent that was instituted and
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`the present petition presented different combinations of prior art and arguments).
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`Accordingly, because the instant petition presents new prior art and
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`arguments, it falls outside of the scope of § 325(d).
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`C. Claim Construction
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`In
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`inter partes review,
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`the Board applies
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`the broadest reasonable
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`construction in light of the specification to claims of an unexpired patent. See 37
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`C.F.R. § 42.100(b). Under the broadest reasonable construction, claim terms are
`
`given their ordinary and accustomed meaning as would be understood by one of
`
`
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`11
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
`
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`ordinary skill in the art in the context of the entire disclosure. In re Translogic
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`Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). However, patent claims, if
`
`expiring prior to a final decision by the Board, are typically construed by the
`
`standard applied in the district courts by applying the principles set forth in Phillips
`
`v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005). See, e.g., 37 C.F.R. § 42.108(c).
`
`Under this standard, the claim terms are given their ordinary and accustomed
`
`meanings as understood by one having ordinary skill in the art at the time of the
`
`invention in the context of the entire patent, considering intrinsic evidence (the
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`claims, the specification, and the prosecution history), and extrinsic evidence
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`(technical dictionaries, treatises, etc.) to a lesser extent.
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`Petitioners understand that the ’464 Patent has expired, and is therefore
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`interpreted under the Phillips standard.1
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`
`1
`For the purposes of this proceeding so as to streamline possible joinder with
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`the Apple 464 IPR, Petitioners propose that the same claim constructions already
`
`adopted by the Board in its institution decision in the Apple 46 IPR be maintained
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`in order to reduce the issues between the parties and because their precise
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`construction does not appear relevant to the merits of this proceeding. Nothing in
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`this filing is intended to conflict in any way with Petitioners’ positions in related
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`district court proceedings with respect to any issue, including claim construction.
`
`
`
`12
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`“a processor controlled by an operating system”
`
`
`
`i.
`
`This claim term is found in claims 1, 10, and 19 as well as in the detailed
`
`description. In IPR2016-01121, Apple Inc.’s petition (at 15-17) proposed that “a
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`processor controlled by an operating system” be construed, but the Board’s
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`institution decision (at 9) found that no construction was necessary. Petitioners
`
`note that the precise construction of this term appears irrelevant to the grounds of
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`patentability
`
`instituted
`
`in IPR2016-01121, and
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`therefore propose
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`that no
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`construction is needed for the purposes of this proceeding. See supra n.1.
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`ii.
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`“translate”/ “translating”
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`This claim term is found in claims 1, 7, 10, 16, 19, and 22 as well as in the
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`detailed description. In IPR2016-01121, Apple Inc.’s petition (at 16) proposed that
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`“translate” be construed as “convert,” and the Board’s institution decision (at 9)
`
`construed it as such. Petitioners note that this construction appears irrelevant to the
`
`grounds of patentability instituted in IPR2016-01121, and therefore propose
`
`maintaining the Board’s construction for the purposes of this proceeding. See
`
`supra n.1.
`
`iii.
`
`“algorithmically translate the noncontiguous addresses to the contiguous
`addresses”
`
`
`Petitioners maintain their right to proceed in the underlying district court litigation
`
`pursuant to the claim construction positions asserted in that action.
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`
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`13
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`
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`This claim term is found in claims 7 and 22, but the detailed description does
`
`not explicitly use this whole term. In IPR2016-01121, Apple Inc.’s petition (at 17)
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`proposed that “algorithmically translate the noncontiguous addresses to the
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`contiguous addresses” be construed as “convert using at least one mathematical
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`operation,” but the Board’s institution decision (at 8-9) construed it as “convert the
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`noncontiguous addresses
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`to
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`the contiguous addresses using at
`
`least one
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`mathematical operation.” Petitioners note that this construction appears irrelevant
`
`to the grounds of patentability instituted in IPR2016-01121, and therefore propose
`
`maintaining the Board’s construction for the purposes of this proceeding. See
`
`supra n.1.
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`1.
`
`Identification of How the Claims Are Unpatentable
`i. Challenge #1: Claims 1, 3-4, 7-8, 10, 12-13, 16-17, and 19-23
`are obvious under 35 U.S.C. § 103 over Gulick and Nale
`(a)
`Summary of Gulick
`
`
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`Gulick describes a computer system that includes a “digital system chip
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`which performs various digital functions, including multimedia functions and
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`chipset functions.” Ex. 1005, Abstract. Gulick is designed with multimedia
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`functions in mind. Embodiments of the computer architecture of Gulick are
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`disclosed in FIG. 1:
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`14
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`Id. at FIG. 1; Ex. 1003, ¶ 56.
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`
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`The computer architecture in Gulick discloses multiple storage devices,
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`including hard disk 122, floppy drive 141, and CD ROM 144. See id. Gulick also
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`teaches that the digital system chip includes MPEG processing capability: “[t]he
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`digital system chip 112 may also include a dedicated MPEG (Motion Pictures
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`Electronics Group) decoder (not shown).” Ex. 1005, 6:11-13. “The digital system
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`chip 112 also preferably includes a general purpose DSP engine 206 which is
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`programmable to perform various functions, such as MPEG decoding …” Id. at
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`6:20-22; Ex. 1003, ¶¶ 57-58.
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`
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`15
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`Gulick further discloses in embodiments a shared main memory: “[i]n one
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`embodiment, the digital system chip 112 does not include multimedia memory, but
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`rather video data and audio data are stored in the system memory 110 according to
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`a unified memory architecture.” Ex. 1005, 6:48-51. This is similar to the computer
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`architecture in Nale discussed below; the CPU 102 in Gulick shares the main
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`memory 110 with the digital system chip, which includes a DSP (see id. at FIG. 2,
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`element 206, or an MPEG decoder, id. at 6:11-13) that can perform MPEG
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`decoding. Ex. 1003, ¶¶ 59-60.
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`Gulick teaches that the components of the computer architecture, including
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`the DSP engine performing MPEG decoding, are controlled by an operating
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`system executing on the CPU 102. Ex. 1005, 7:56-60. Gulick does not explicitly
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`discuss the specific addressing scheme used between the DSP engine/MPEG
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`decoder of the digital system chip and shared main memory. An addressing
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`scheme, with corresponding translator, however, was well known prior to the
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`earliest alleged priority date of the ’464 Patent. For instance, Nale explains an
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`address translator that converts contiguous addresses to non-contiguous addresses
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`utilized by computer systems before the earliest alleged priority date of the ’464
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`Patent, as described below. See Ex. 1003, ¶ 61.
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`(b)
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`Summary of Nale
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`Nale describes an address translator in a shared memory system that
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`performs address translation between contiguous and non-contiguous addresses for
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`memory access. Memory in Nale is described as being allocated in 4K byte
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`increments by the operating system. Ex. 1006, 3:32-34. As shown in Nale’s FIG. 2,
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`the translator 12 of the present invention is illustrated converting
`graphics addresses generated by a graphics controller into addresses in
`the system memory, according to the presently preferred embodiment
`of the invention. A graphics memory address map 20 illustrates the
`contiguous graphics addresses generated by the graphics controller.
`Similarly, a system memory map 22 illustrates the non-contiguous
`addresses corresponding to available memory blocks in the system
`memory.
`Id. at 3:46-54; see also FIG. 2, reproduced and annotated below.
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`Non-contiguous
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`Contiguous
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`Translator 12
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`Ex. 1006, FIG. 2; Ex. 1003, ¶ 62.
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`The address translator 12 is coupled between a graphics controller 6 and
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`system memory 10 (shared with the CPU 2), and “is positioned to intercept
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`addresses generated by the graphics controller 6 and translate same into addresses
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`in the system memory 10.” Ex. 1006, 3:6-9. “The address translator translates, or
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`converts, contiguous graphics addresses generated by a graphics controller into
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`non-contiguous addresses in the system memory.” Id. at 2:6-9 (emphasis added);
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`Ex. 1003, ¶¶ 62-63.
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`The translation occurs after allocation of system memory based on a need
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`for the system memory. Ex. 1006, 5:42-47. Based on the need, “the additional
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`needed memory from the operating system” is requested. Id. at 6:13-15. In
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`response, the operating system allocates the memory for use, which may not be
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`contiguous, by the graphics controller of Nale. Id. at 2:1-13. As part of this, the
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`starting addresses are provided to the address translator, which puts them into a
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`look-up table (effectively translating the possibly noncontiguous addresses into
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`available contiguous addresses for the graphics controller). Id.at 6:13-29. As part
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`of the request to the operating system, an instruction would have been included to
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`treat the allocated blocks as nonswappable until released. Ex. 1003, ¶¶ 64-65.
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`Nale’s structure and teachings provide, therefore, for an address translator in
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`a computer system that translates addresses between a requesting device (graphics
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`Petition for Inter Partes Review of U.S. Patent No. 5,960,464
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`controller in Nale) and a shared system memory “in real-time” as addresses are
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`received. Ex. 1006, 2:9-11; Ex. 1003, ¶ 66.
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`(c) Reasons to Combine Gulick and Nale
`First, Gulick teaches an MPEG decoder (whether a dedicated MPEG
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`decoder or a general purpose DSP engine programmable for MPEG decoding). Ex.
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`1005, 6:11-13, 20-24. Gulick also teaches that the MPEG decoder/DSP engine
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`accesses the main system memory, and shares the main system memory with the
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`CPU. Id. at 6:48-55; 10:31-36. Gulick further teaches that a chipset may interface
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`the DSP engine/MPEG decoder to the main memory, and that the chipset may be
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`similar to a type (e.g., the “Triton chipset”) that includes memory interfacing
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`functions. Id. at 4:47-49; Ex. 1003, ¶¶ 67-68.
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`Nale teaches an approach to performing an exemplary memory interfacing
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`function of address translation for a device. Specifically, Nale teaches an improved
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`method of accessing main memory in a system where the graphics system shares
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`the main memory with the CPU: “a need exists in the prior art for a method for
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`dynamically allocating additional memory to the graphics controller from the
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`system memory.” Ex. 1006, 1:36-38. As Nale teaches, “[a]lthough most graphics
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`controllers are designed to address contiguous memory, those portions of a system
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`memory that might be usable by a graphics controller generally are not
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`contiguous.” Id. at 2:3-6. Nale teaches that, by using its memory interfacing
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`approach, “additional system memory may be dynamically allocated to the
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`graphics controller.” Id. at 2:2-13; Ex. 1003, ¶ 69.
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`Second, like Gulick, Nale contemplates a unified memory architecture: “The
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`present invention enables a system memory to be shared by a graphics controller
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`without requiring a user to reboot the system to accommodate more demanding
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`graphics modes.” Id. at 1:41-44. Nale teaches solving a problem that would enable
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`Gulick’s computer system to dynamically allocate memory but still provide
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`contiguous memory to the decoder/DSP engine. The combination would have been
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`obvious because it would provide the digital system chip (namely the decoder in
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`the digital system chip) of Gulick a contiguous address space in which to work in
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`Gulick’s main memory for graphics control and MPEG decoding operations,
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`though the physical locations in main memory may not be contiguous, by way of
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`the chipset performing memory interfacing functions such as taught by Nale with
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`respect to address translation. Ex. 1003, ¶ 70.
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`Further, it would have been within the skill of one having ordinary skill in
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`the art to combine the memory interfacing teachings of Nale into the unified
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`memory architecture of Gulick, and specifically to the chipset, so as to obtain the
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`Nale’s benefit of dynamic allocation of memory to graphics and decoding without
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`having to reboot in a manner that provides the appearance of a contiguous address
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`space to the MPEG decoder/DSP engine of Gulick’s digital system chip. It would
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`have been nothing more than the combination of prior art elements according to
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`known methods to yield the predictable result of a contiguous address space that
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`can be dynamically allocated in a unified memory architecture that supports MPEG
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`decoding. Ex. 1003, ¶ 71.
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`Nale specifically solves the problem of providing large blocks of memory to
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`a graphics device, including the ability to use noncontiguous addresses for a device
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`that operates with contiguous addresses, and an ability to dynamically allocate
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`system memory for graphics without requiring a reboot. Ex. 1003, ¶ 72.
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`Accordingly, persons of ordinary skill in the art before the earliest alleged
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`priority date of the ’464 Patent would have been motivated to combine Nale’s
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`memory interfacing teachings regarding address translation between contiguous
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`and noncontiguous addresses in a shared memory system with Gulick’s teaching of
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`a computer system with a shared main memory, multiple storage devices, a DSP
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`engine that performs MPEG decoding, and a chipset that includes memory
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`interfacing functions. The predictable and desirable combination would yield a
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`system with the ability to dynamically allocate memory even when it is in
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`noncontiguous blocks. Ex. 1003, ¶ 73.
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`(d) Detailed Analysis
`The following analysis describes how Gulick as informed by Nale renders
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`obvious each and every element of at least claims 1, 3-4, 7-8, 10, 12-13, 16-17, and
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`19-23 of the ’464 Patent. A corresponding claim chart is contained in Dr. Colwell’s
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`expert declaration. See Ex. 1003, pp. 32-65.
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`Claim 1 recites:
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`[1.0]
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`In a computer system having a main memory, a storage device having
`encoded data stored therein and a processor controlled by an operating
`system, an electronic device comprising:
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`Gulick teaches a computer system having a main memory, a hard disk
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`(storage device), and a central processing unit (processor).
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`Processor
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`Memory
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`Computer
`System
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`Storage device
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`Ex. 1005, FIG. 1 (annotated); Ex. 1
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