PRELIMINARY
`82430FX PClset DATASHEET 82437FX
`SYSTEM CONTROLLER (TSC) AND
`82438FX DATA PATH UNIT (TOP)
`
`•
`
`• Supports the Pentium® Processor at
`iCOMf>® Index 1110\133 MHz, iCOMP
`Index 1000\120 MHz, iCOMP Index
`815\100 MHz, iCOMP Index 735\90 MHz
`and the iCOMP Index 610\75 MHz
`Integrated Second Level Cache
`Controller
`Direct Mapped Organization
`Write-Back Cache Policy
`Cacheless, 256-Kbyte, and
`512-Kbyte
`Standard Burst and Pipelined Burst
`SRA Ms
`Cache Hit Read/Write Cycle Timings
`at 3-1-1-1 with Burst or Pipelined
`Burst SRAMs
`Back-to-Back Read Cycles at
`3-1-1-1-1-1-1-1 with Burst or
`Pipelined Burst SRAMs
`Integrated TagNalid Status Bits for
`Cost Savings and Performance
`Supports 5V SRAMs for Tag
`Address
`Integrated DRAM Controller
`64-Bit Data Path to Memory
`4 Mbytes to 128 Mbytes Main
`Memory
`EDO/Hyper Page Mode DRAM
`(x-2-2-2 Reads) or Standard Page
`Mode DRAMS
`5 RAS Lines
`
`•
`
`4 Qword Deep Buffer for 3-1-1-1
`Posted Write Cycles
`Symmetrical and Asymmetrical
`ORA Ms
`3V or 5V DRAMs
`• EDO DRAM Support
`Highest Performance with Burst or
`Pipelined Burst SRAMs
`Superior Cacheless Designs
`• Fully Synchronous 25/30/33 MHz PCI
`Bus Interface
`100 MB/s Instant Access Enables
`Native Signal Processing (NSP) on
`Pentium Processors
`Synchronized CPU-to-PCI Interface
`for High Performance Graphics
`PCI Bus Arbiter: PllX and Four PCI
`Bus Masters Supported
`CPU-to-PCI Memory Write Posting
`with 4 Dword Deep Buffers
`Converts Back-to-Back Sequential
`CPU to PCI Memory Writes to PCI
`Burst Writes
`PCl-to-DRAM Posting of 12 Dwords
`PCl-to-DRAM up to 120 Mbytes/Sec
`Bandwidth Utilizing Snoop Ahead
`Feature
`• NANO Tree for Board-Level ATE
`Testing
`• 208 Pin QFP for the 82437FX System
`Controller (TSC); 100 Pin QFP for Each
`82438FX Data Path (TOP)
`
`The 82430FX PClset consists of the 82437FX System Controller (TSC), two 82438FX Data Paths (TOP), and
`the 82371 FB PCI ISA IDE Xcelerator (PllX). The PClset forms a Host-to-PCI bridge and provides the second
`level cache control and a full function 64-bit data path to main memory. The TSC integrates the cache and
`main memory DRAM control functions and provides bus control for transfers between the CPU, cache, main
`memory, and the PCI Bus. The second level (L2) cache controller supports a write-back cache policy for
`cache sizes of 256 Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache memory can
`be implemented with either standard, burst, or pipelined burst SRAMs. An external Tag RAM is used for the
`address tag and an internal Tag RAM for the cache line status bits. For the TSC's DRAM controller, five rows
`are supported for up to 128 Mbytes of main memory. The TSC's optimized PCI interface allows the CPU to
`sustain the highest possible bandwidth to the graphics frame buffer at all frequencies. Using the snoop ahead
`feature, the TSC allows PCI masters to achieve full PCI bandwidth. The TDPs provide the data paths
`between the CPU/cache, main memory, and PCI. For increased system performance, the TDPs contain read
`prefetch and posted write buffers.
`
`Information in this documen1 is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement
`of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products.
`Information contained herein supersedes previously published specifications on these devices from Intel.
`©INTEL CORPORATION 1995
`June 1995
`
`Order Number: 290518-001
`
`I
`
`...C'
`():>
`ru
`er
`~
`-..J
`ln
`
`D
`~
`ln
`():>
`w
`():>
`w
`
`ln
`--D
`w
`I
`
`Apple Inc. v. Parthenon
`Ex. 1009 / Page 1 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 1
`
`

`
`.
`
`;..
`
`;
`.
`.
`
`.
`
`AD[31:0]
`C/BE[3:0]#
`FRAME#
`TRDY#
`IRDY#
`STOP#
`LOCK#
`DEVSEL#
`PAR
`REQ[3:0]#
`GNT[3:0]#
`PHLD#
`PHLDA#
`RST#
`
`;
`
`.
`.
`.
`
`RAS[4:0]#
`CAS[7:0]#
`MA[11:2]
`MAA[1:0]
`MAB[1:0]
`
`;..
`
`PLINK[15:0]
`MSTB#
`MADV#
`; .
`PCMD[1:0]
`HOE#
`MOE#
`POE#
`
`;
`
`82437FX TSC AND 82438FX TOP
`
`PCI
`I+-~ Interface
`
`Host
`Interface
`
`~
`
`'
`
`.
`
`~
`
`-
`
`;..
`-;.
`
`-- ~
`
`
`
`~ -
`
`A[31:3]
`BE[7:0]#
`ADS#
`DIG#
`M/10#
`W/R#
`BRDY#
`EADS#
`HITM#
`BOFF#
`AHOLD
`NA#
`KEN#/INV
`CACHE#
`HLOCK#
`SMIACT#
`
`CCS#/CAB4#
`CAB3#
`TWE#
`COE#
`CWE[7:0]#
`CADS#/CAA3#
`CADV#/CAA4
`TI0[7:0]
`
`~
`
`~
`
`-
`
`HCLKIN
`PCLKIN
`
`DRAM
`~ Interface
`
`Cache -
`
`Interface
`
`i----.
`
`TOP
`Interface
`
`r
`
`Clocks ~
`
`82437FX TSC Simplified Block Diagram
`
`2
`
`PRELI MINAR]
`
`• 4826175 0158384 42T •
`
`Ex. 1009 / Page 2 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 2
`
`

`
`82437FX TSC AND 82438FX TOP
`
`0[31:0]
`
`Host
`- Interface
`
`+----
`
`-
`
`-
`
`TSC
`Interface
`
`'------+
`
`MD[31:0]
`
`DRAM
`Interface
`
`~
`
`-
`
`PLINK[7:0]
`MSTB#
`MADVil
`PCMD[1:0]
`HOE#
`MOE#
`POE#
`
`L--+
`
`Clocks
`
`HCLK
`
`82438FX TOP Simplified Block Diagram
`
`I PRELIMINARY
`
`• 4826175 0158385 366 •
`
`051802
`
`3
`
`Ex. 1009 / Page 3 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 3
`
`

`
`82437FX TSC AND 82438FX TOP
`
`CONTENTS
`
`PAGE
`
`1.0. ARCHITECTURE OVERVIEW OF TSCITDP ••••••.••.••••••••••••••••...••••••••••••••••••••...•••••••••.•.•••.•.••••.••••••••••••...• 6
`
`2.0. SIGNAL DESCRIPTION ...•.....••.•••••••••••••••••••••••.••••..•••.•••••••••••.•••••••.•.•••••••••••.•••••••••••••••.•••••.•••••••.••••••.••.••• 8
`2.1. TSC Signals .......................................................................................................................................... 9
`2.1.1. HOST INTERFACE (TSC) ............................................................................................................. 9
`2.1.2. DRAM INTERFACE (TSC) ........................................................................................................... 10
`2.1.3. SECONDARY CACHE INTERFACE (TSC) .................................................................................. 11
`2.1.4. PCI INTERFACE (TSC) ............................................................................................................... 12
`2.1.5. TOP INTERFACE (TSC) .............................................................................................................. 13
`2.1.6. CLOCKS (TSC) ............................................................................................................................ 13
`2.2. TOP Signals ........................................................................................................................................ 14
`2.2.1. DATA INTERFACE SIGNALS (TDP) ............................................................................................ 14
`2.2.2. TSC INTERFACE SIGNALS (TDP) .............................................................................................. 14
`2.2.3. CLOCK SIGNAL (TOP) ................................................................................................................ 14
`2.3. Signal State During Reset.. ................................................................................................................. 15
`
`3.0. REGISTER DESCRIPTION .••..•••••••••••••••••••.•••••.••.•••.••.•••••••••••••••••.•.•.••••••..•...•.•••••••••••.•••••••••••••••.••••••••••• 16
`3.1 . Control Registers ................................................................................................................................ 16
`3.1.1. CONFADD-CONFIGURATION ADDRESS REGISTER ............................................................. 17
`3.1.2. CONFDATA-CONFIGURATION DATA REGISTER ................................................................... 18
`3.2. PCI Configuration Registers ................................................................................................................ 18
`3.2.1. YID-VENDOR IDENTIFICATION REGISTER ............................................................................ 20
`3.2.2. DID-DEVICE IDENTIFICATION REGISTER .............................................................................. 20
`3.2.3. PCICMD-PCI COMMAND REGISTER. ...................................................................................... 20
`3.2.4. PCISTS--PCI STATUS REGISTER ............................................................................................ 21
`3.2.5. RID-REVISION IDENTIFICATION REGISTER .......................................................................... 21
`3.2.6. SUBC-SUB-CLASS CODE REGISTER ..................................................................................... 22
`3.2.7. BCC-BASE CLASS CODE REGISTER .................................................................................... 22
`3.2.8. MLT-MASTER LATENCY TIMER REGISTER ........................................................................... 22
`3.2.9. BIST-BIST REGISTER .............................................................................................................. 23
`3.2.10. PCON--PCI CONTROL REGISTER .......................................................................................... 23
`3.2.11. CC-CACHE CONTROL REGISTER ......................................................................................... 24
`3.2.12. DRAMC--DRAM CONTROL REGISTER ................................................................................... 25
`3.2.13. DRAMT-DRAM TIMING REGISTER ........................................................................................ 26
`3.2.14. PAM-PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0]) ..................................... 28
`3.2.15. ORB-DRAM ROW BOUNDARY REGISTERS ......................................................................... 31
`3.2.16. ORT-DRAM ROW TYPE REGISTER ....................................................................................... 33
`3.2.17. SMRAM-SYSTEM MANAGEMENT RAM CONTROL REGISTER ........................................... 33
`
`4
`
`• 4826175 0158386 2T2 •
`
`PRELIMINARY I
`
`Ex. 1009 / Page 4 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 4
`
`

`
`82437FX TSC AND 82438FX TOP
`
`4.0. FUNCTIONAL DESCRIPTION .............................................................................................................. 34
`4.1. Host Interface ..................................................................................................................................... 34
`4.2. PCI lnterface ....................................................................................................................................... 35
`4.3. Secondary Cache lnterface ................................................................................................................. 35
`4.3.1. CLOCK LATENCIES .................................................................................................................... 36
`4.3.2. SNOOP CYCLES ......................................................................................................................... 36
`4.3.3. CACHE ORGANIZATION ............................................................................................................ 37
`4.4. DRAM Interface ................................................................................................................................. .42
`4.4.1. DRAM ORGANIZATION ............................................................................................................. .42
`4.4.2. MAIN MEMORY ADDRESS MAP ............................................................................................... .43
`4.4.3. DRAM ADDRESS TRANSLATION .............................................................................................. .43
`4.4.4. DRAM PAGE MODE ................................................................................................................... .45
`4.4.5. EDO MODE ................................................................................................................................ .45
`4.4.6. DRAM PERFORMANCE ............................................................................................................. .46
`4.4.7. DRAM REFRESH ....................................................................................................................... .46
`4.4.8. SYSTEM MANAGEMENT RAM ................................................................................................... 46
`4.5. 82438FX Data Path (TOP) .................................................................................................................. 47
`4.6. PCI Bus Arbitration ............................................................................................................................ .48
`4.6.1. PRIORITY SCHEME AND BUS GRANT ..................................................................................... .48
`4.6.2. CPU POLICIES ............................................................................................................................ 48
`4.7. Clock Generation and Distribution ...................................................................................................... .49
`4.7.1. RESET SEQUENCING ................................................................................................................ 49
`
`5.0. PINOUT AND PACKAGE INFORMATION ............................................................................................. 50
`5.1 . 82437FX Pinout .................................................................................................................................. 50
`5.2. 82438FX Pinout .................................................................................................................................. 54
`5.3. 82437FX Package Dimensions ........................................................................................................... 56
`5.4. 82438FX Package Dimensions ........................................................................................................... 58
`
`6.0. 82437FX TSC TESTABILITY ................................................................................................................. 59
`6.1. Test Mode Description ........................................................................................................................ 59
`6.2. NANO Tree Mode ............................................................................................................................... 59
`
`7.0. 82438FX TOP TESTABILITY ................................................................................................................. 65
`7.1. Test Mode Description ........................................................................................................................ 65
`7.2. NANO Tree Mode ............................................................................................................................... 65
`
`I PRELIMINARY
`
`• 4826175
`
`0158387 139 •
`
`5
`
`Ex. 1009 / Page 5 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 5
`
`

`
`82437FX TSC AND 82438FX TOP
`
`1.0. ARCHITECTURE OVERVIEW OF TSCITDP
`
`The 82430FX PClset (Figure 1) consists of the 82437FX System Controller (TSC), two 82438FX Data Path
`(TOP) units, and the 82371 FB PCI IDE ISA Xcelerator (PllX). The TSC and two TDPs form a Host-to-PC!
`bridge. The PllX is a multi-function PCI device providing a PCl-to-ISA bridge and a fast IDE interface. The
`PllX also provides power management and has a plug and play port.
`
`The two TDPs provide a 64-bit data path to the host and to main memory and provide a 16-bit data path
`(PLINK) between the TSC and TOP. PLINK provides the data path for CPU to PCI accesses and for PCI to
`main memory accesses. The TSC and TOP bus interfaces are designed for 3V and 5V busses. The
`TSC!TDP connect directly to the Pentium® processor 3V host bus; The TSC!TDP connect directly to 5V or
`3V main memory DRAMs; and the TSC connects directly to the 5V PCI Bus.
`
`DRAM Interface
`
`The DRAM interface is a 64-bit data path that supports both standard page mode and Extended Data Out
`(EDO) (also known as Hyper Page Mode) memory. The DRAM interface supports 4 Mbytes to 128 Mbytes
`with five RAS lines available and also supports symmetrical and asymmetrical addressing for 512K, 1 M, 2M,
`and 4M deep DRAMs.
`
`Second Level Cache
`
`The TSC supports a write-back cache policy providing all necessary snoop functions and inquire cycles. The
`second level cache is direct mapped and supports both a 256-Kbyte or 512-Kbyte SAAM configuration using
`either burst, pipelined burst, or standard SRAMs. The burst 256-Kbyte configuration performance is 3-1-1-1
`for read/write cycles; pipelined back-to-back reads can maintain a 3-1-1-1-1-1-1-1 transfer rate.
`
`TOP
`
`Two TDPs create a 64-bit CPU and main memory data path. The TDP's also interface to the TSC's 16-bit
`PLINK inter-chip bus for PCI transactions. The combination of the 64-bit memory path and the 16-bit PLINK
`bus make the TDP's a cost effective solution, providing optimal CPU-to-main memory performance while
`maintaining a small package footprint (100 pins each).
`
`PCI Interface
`
`The PCI interface is 2.0 compliant and supports up to 4 PCI bus masters in addition to the PllX bus master
`requests. While the TSC and TDP's together provide the interface between PCI and main memory, only the
`TSC connects to the PCI Bus.
`
`6
`
`• 4826175 0158388 075 •
`
`PRELIMINARY I
`
`Ex. 1009 / Page 6 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 6
`
`

`
`82437FX TSC AND 82438FX TOP
`
`Pentium® Processor
`
`l Control
`
`Address
`
`Data
`
`'
`
`Addr
`
`Cntl
`
`.
`"
`.
`
`Main
`Memory
`(DRAM)
`
`Data
`
`-
`
`~
`
`TOP Cntl
`
`-
`
`PLINK (Data)
`
`TOP
`
`"
`
`-
`
`Control
`
`Address/Data
`
`·~
`
`'
`
`'
`
`TSC
`
`·~
`
`,.
`
`'
`
`1
`
`·~
`
`,.
`......... ------ ----------,
`'
`:
`'
`:
`
`,.
`l--~-~'._:~~=~~-----1
`
`r--------------------·••1
`'
`'
`:
`;
`! ISA Device(s)
`!
`
`~------------ __________ J
`·~
`
`,,
`
`"
`
`"
`
`"
`
`"
`
`~
`
`051803
`
`7
`
`,::
`
`-
`-
`
`Host Bus
`(\
`: ~
`'
`'
`'
`
`'
`I
`
`'
`'
`' '
`' ' ,,
`Second Level
`"
`... ----.... ---------.. ---..... '
`Cache
`
`.
`
`"
`
`"
`
`Cache
`(SRAM)
`
`Cntl
`
`-
`GJ - Tag Cntl
`-
`- TI0[7:0]
`-
`
`'
`·----------------------
`'
`
`PCI Bus
`/\
`'
`! '
`'
`~ :
`\./
`
`-
`-
`
`CD ROM
`
`Hard
`Disk
`
`Fast IDE
`
`Audio
`
`Plug-n-Play Port
`
`ISA Bus
`
`"
`
`PllX
`
`·~
`
`,,
`
`Figure 1. 82430FX PClset System
`
`I PRELIMINARY
`
`• 4826175 0158389 TD1
`
`•
`
`Ex. 1009 / Page 7 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 7
`
`

`
`82437FX TSC AND 82438FX TOP
`
`Buffers
`
`The TSC and TDP's together contain buffers for optimizing data flow. A four Qword deep buffer is provided
`for CPU-to-main memory writes, second level cache write back cycles, and PCl-to-main memory transfers.
`This buffer is used to achieve 3-1-1-1 posted writes to main memory. A four Dword buffer is used for CPU-to(cid:173)
`PCI writes. In addition, a four Dword PCI Write Buffer is provided which is combined with the DRAM Write
`Buffer to supply a 12 Dword deep buffering for PCI to main memory writes.
`
`System Clocking
`
`The processor, second level cache, main memory subsystem, and PLINK bus all run synchronous to the host
`clock. The PCI clock runs synchronously at half the host clock frequency. The TSC and TDP's have a host
`clock input and the TSC has a PCI clock input. These clocks are derived from an external source and have a
`maximum clock skew requirement with respect to each other.
`
`2.0. SIGNAL DESCRIPTION
`
`This section provides a detailed description of each signal. The signals are arranged in functional groups
`according to their associated interface.
`
`The"#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal
`is at a low voltage level. When "#" is not present after the signal name, the signal is asserted when at the high
`voltage level.
`
`The terms assertion and negation are used extensively. This is done to avoid confusion when working with a
`mixture of "active-low" and "active-high" signals. The term assert, or assertion indicates that a signal is
`active, independent of whether that level is represented by a high or low voltage. The term negate, or
`negation indicates that a signal is inactive.
`
`The following notations are used to describe the signal type.
`
`Input is a standard input-only signal.
`I
`Totem pole output is a standard active driver.
`0
`Open drain.
`o/d
`Tri-State is a bi-directional, tri-state input/output pin.
`tis
`s/t/s Sustained tri-state is an active low tri-state signal owned and driven by one and only one agent at a
`time. The agent that drives a s/t/s pin low must drive it high for at least one clock before letting it float.
`A new agent can not start driving a s/t/s signal any sooner than one clock after the previous owner tri(cid:173)
`states it. An external pull-up is required to sustain the inactive state until another agent drives it and
`must be provided by the central resource.
`
`8
`
`• 4826175 0158390 723 •
`
`PRELIMINAR~ I
`
`Ex. 1009 / Page 8 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 8
`
`

`
`82437FX TSC AND 82438FX TOP
`
`2.1.
`
`TSC Signals
`
`2.1.1.
`
`HOST INTERFACE (TSC)
`
`Signal
`Name
`
`Type
`
`Description
`
`A[31:3]
`
`1/03V ADDRESS BUS: A[31 :3] connect to the address bus of the CPU. During CPU
`cycles A[31 :3] are inputs. These signals are driven by the TSC during cache
`snoop operations. Note that A[31 :28] provide poweron/reset strapping options for
`the second level cache.
`
`BE[7:0]#
`
`13V
`
`BYTE ENABLES: The CPU byte enables indicate which byte lane the current
`CPU cycle is accessing. All eight byte lanes are provided to the CPU if the cycle
`is a cacheable read regardless of the state of BE[7:0]#.
`
`ADS#
`
`I 3V
`
`ADDRESS STATUS: The CPU asserts ADS# to indicate that a new bus cycle is
`being driven.
`
`BROY#
`
`03V
`
`BUS READY: The TSC asserts BROY# to indicate to the CPU that data is
`available on reads or has been received on writes.
`
`NA#
`
`03V
`
`AHOLD
`
`03V
`
`NEXT ADDRESS: When burst SRAMs are used in the second level cache or the
`second level cache is disabled, the TSC asserts NA# in T2 during CPU write
`cycles and with the first assertion of BROY# during CPU linefills. NA# is never
`asserted if the second level cache is enabled with asynchronous SRAMs. NA# on
`the TSC must be connected to the CPU NA# pin for all configurations.
`
`ADDRESS HOLD: The TSC asserts AHOLD when a PCI master is accessing
`main memory. AHOLD is held for the duration of the PCI burst transfer. The TSC
`negates AHOLD when the PCI to main memory read/write cycles complete and
`during PCI peer transfers.
`
`EADS#
`
`03V
`
`EXTERNAL ADDRESS STROBE: Asserted by the TSC to inquire the first level
`cache when servicing PCI master accesses to main memory.
`
`BOFF#
`
`03V
`
`BACK OFF: Asserted by the TSC when required to terminate a CPU cycle that
`was in progress.
`
`HITM#
`
`13V
`
`M/10#, DIC#, 13V
`W/R#
`
`HLOCK#
`
`13V
`
`CACHE#
`
`13V
`
`HIT MODIFIED: Asserted by the CPU to indicate that the address presented with
`the last assertion of EADS# is modified in the first level cache and needs to be
`written back.
`
`MEMORYnO; DATA/CONTROL; WRITE/READ: Asserted by the CPU with ADS#
`to indicate the type of cycle on the host bus.
`
`HOST LOCK: All CPU cycles sampled with the assertion of HLOCK# and ADS#,
`until the negation of HLOCK# must be atomic (i.e., no PCI activity to main
`memory is allowed).
`
`CACHEABLE: Asserted by the CPU during a read cycle to indicate the CPU can
`perform a burst line fill. Asserted by the CPU during a write cycle to indicate that
`the CPU will perform a burst write-back cycle. If CACHE# is asserted to indicate
`cacheability, the TSC asserts KEN# either with the first BROY#, or with NA#, if
`NA# is asserted before the first BROY#.
`
`I PRELIMINARY
`
`• 4826175
`
`0158391 bbT •
`
`9
`
`Ex. 1009 / Page 9 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 9
`
`

`
`82437FX TSC AND 82438FX TOP
`
`Signal
`Name
`
`Type
`
`KEN#/INV
`
`03V
`
`SMIACT#
`
`13V
`
`Description
`
`CACHE ENABLE/INVALIDATE: KEN#/INV functions as both the KEN# signal
`during CPU read cycles and the INV signal during first level cache snoop cycles.
`During CPU cycles, KEN#/INV is normally low. The TSC drives KEN# high during
`the first BADY# or NA# assertion of a non-cacheable (in first level cache) CPU
`read cycle.
`
`The TSC drives INV high during the EADS# assertion of a PCI master DRAM
`write snoop cycle and low during the EADS# assertion of a PCI master DRAM
`read snoop cycle.
`
`SYSTEM MANAGEMENT INTERRUPT ACTIVE: The CPU asserts SMIACT#
`when it is in system management mode as a result of an SMI. After SMM space
`(located at AOOOOh) is loaded and locked by BIOS, this signal must be sampled
`active with ADS# for the processor to access the SMM space of DRAM.
`
`2.1.2.
`
`DRAM INTERFACE (TSC)
`
`Signal
`Name
`
`Type
`
`Description
`
`RAS[4:0]#
`
`03V
`
`ROW ADDRESS STROBE: These pins select the DRAM row.
`
`CAS[7:0)#
`
`03V
`
`COLUMN ADDRESS STROBE: These pins always select which bytes are
`affected by a DRAM cycle.
`
`MA[11 :2]
`
`MAA[1:0]
`
`03V
`
`03V
`
`MEMORY ADDRESS: This is the row and column address for DRAM.
`
`MEMORY ADDRESS COPY A: One copy of the MAs that change during a burst
`read or write of DRAM.
`
`MAB[1:0]
`
`03V
`
`MEMORY ADDRESS COPY B: A second copy of the MAs that change during a
`burst read or write of DRAM.
`
`10
`
`• 4826175 0158392 5Tb •
`
`PRELIMINARY I
`
`Ex. 1009 / Page 10 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 10
`
`

`
`82437FX TSC AND 82438FX TOP
`
`2.1.3.
`
`SECONDARY CACHE INTERFACE (TSC)
`
`Signal
`Name
`CADV#/
`CAA4
`
`Type
`
`03V
`
`CADS#/
`CAA3
`
`03V
`
`CAB3
`
`03V
`
`CCS#/
`CAB4
`
`03V
`
`Description
`
`CACHE ADVANCE/CACHE ADDRESS 4 (COPY A): This pin has two modes of
`operation depending on the type of SRAMs selected via hardware strapping options
`or programming the CC Register. The CAA4 mode is used when the L2 cache
`consists of asynchronous SRAMs. CAA4 is used to sequence through the Qwords
`in a cache line during a burst operation.
`
`CADV# mode is used when the L2 cache consists of burst SRAMs. In this mode,
`assertion causes the burst SRAM in the L2 cache to advance to the next Qword in
`the cache line.
`
`CACHE ADDRESS STROBE/CACHE ADDRESS 3 (COPY A): This pin has two
`modes of operation depending on the type of SRAMs selected via hardware
`strapping options or programming the CC Register. The CAA3 mode is used when
`the L2 cache consists of asynchronous SRAMs. CAA3 is used to sequence through
`the Qwords in a cache line during a burst operation.
`
`CADS# mode is used when the L2 cache consists of burst SRAMs. In this mode
`assertion causes the burst SRAM in the L2 cache to load the BSRAM address
`register from the BSRAM address pins.
`
`CACHE ADDRESS 3 (COPY B): CAB3 is used when the L2 cache consists of
`asynchronous SRAMs. CAB3 is used to sequence through the Qwords in a cache
`line during a burst operation
`
`CACHE CHIP SELECT/CACHE ADDRESS (COPY B): This pin has two modes of
`operation depending on the type of SRAMs selected via hardware strapping options
`or programming the CC Register. The CAB4 mode is used when the L2 cache
`consists of asynchronous SRAMs. CAB4 is used to sequence through the Qwords
`in a cache line during a burst operation.
`
`A L2 cache consisting of burst SRAMs will power up, if necessary, and perform an
`access if CCS# is asserted when CADS# is asserted. A L2 cache consisting of
`burst SRAMs will power down if CCS# is negated when CADS# is asserted. When
`CCS# is negated, a L2 cache consisting of burst SRAMs ignores ADS#. If CCS# is
`asserted when ADS# is asserted, a L2 cache consisting of burst SRAMs will power
`up, if necessary, and perform an access.
`
`COE#
`
`03V
`
`CACHE OUTPUT ENABLE: The secondary cache data RAMs drive the CPU's data
`bus when COE# is asserted.
`
`CWE[7:0]# 03V
`
`CACHE WRITE ENABLE: Each CWE# corresponds to one byte lane. Assertion
`causes the byte lane to be written into the secondary cache data RAMs if they are
`powered up.
`
`TI0[7:0]
`
`l/05V TAG ADDRESS: These are inputs during CPU accesses and outputs during L2
`cache line fills and L2 cache line invalidates due to inquire cycles. TI0[7:0] contain
`the L2 tag address for 256-Kbyte L2 caches. TI0[6:0] contains the L2 tag address
`and TI07 contains the L2 cache valid bit for 512-Kbyte caches.
`
`TWE#
`
`05V
`
`TAG WRITE ENABLE: When asserted, new state and tag addresses are written
`into the external tag.
`
`I PRELIMINARY
`
`• 4826175
`
`0158393 432 •
`
`11
`
`Ex. 1009 / Page 11 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 11
`
`

`
`82437FX TSC AND 82438FX TOP
`
`2.1.4.
`
`PCI INTERFACE (TSC)
`
`Signal
`Name
`
`AD[31:0]
`
`C/BE[3:0]#
`
`Type
`
`Description
`
`110 sv ADDRESS DATA BUS: The standard PCI address and data lines. The address is
`driven with FRAME# assertion and data is driven or received in following clocks.
`
`l/05V COMMAND, BYTE ENABLE: The command is driven with FRAME# assertion.
`Byte enables corresponding to supplied or requested data are driven on following
`clocks.
`
`FRAME#
`
`l/OSV
`
`FRAME: Assertion indicates the address phase of a PCI transfer. Negation
`indicates that one more data transfer is desired by the cycle initiator.
`
`DEVSEL#
`
`1/05V DEVICE SELECT: The TSC drvies DEVSEL# when a PCI initiator attempts to
`access main memory. DEVSEL# is asserted at medium decode time.
`
`IRDY#
`
`l/OSV
`
`INITIATOR READY: Asserted when the initiator is ready for a data transfer.
`
`TRDY#
`
`l/OSV
`
`TARGET READY: Asserted when the target is ready for a data transfer.
`
`STOP#
`
`LOCK#
`
`l/OSV STOP: Asserted by the target to request the master to stop the current transaction.
`
`1/05V
`
`LOCK: Used to establish, maintain, and release resource locks on PCI.
`
`REQ[3:0]#
`ISV
`GNT[3:0]# osv
`PHLD#
`15V
`
`REQUEST: PCI master requests for PCI.
`
`GRANT: Permission is given to the master to use PCI.
`
`PCI HOLD: This signal comes from the PllX. PHLD# is the PllX request for the PCI
`Bus. The TSC flushes the DRAM Write Buffers and acquires the host bus before
`granting PllX via PHLDA#. This ensures that the guaranteed access time is met for
`ISA masters.
`
`PHLDA#
`
`05V
`
`PCI HOLD ACKNOWLEDGE: This signal is driven by the TSC to grant PCI to the
`PllX.
`
`PAR
`
`RST#
`
`l/OSV PARITY: A single parity bit is provided over AD[31 :O] and C/BE[3:0].
`
`ISV
`
`RESET: When asserted, RST# resets the TSC and sets all register bits to the
`default value.
`
`12
`
`• 4826175 0158394 379 •
`
`PRELIMINARY I
`
`Ex. 1009 / Page 12 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 12
`
`

`
`82437FX TSC AND 82438FX TOP
`
`2.1.5.
`
`TOP INTERFACE (TSC)
`
`Signal
`Name
`
`Type
`
`Description
`
`PLINK[15:0]
`
`1/0 3V PCI LINK: These signals are connected to the PLINK data bus on the TOP. This
`is the data path between the TSC and TOP. Each TOP connects to one byte of
`the 16-bit bus.
`
`MSTB#
`
`03V
`
`MEMORY STROBE: Assertion causes data to be posted in the DRAM Write
`Buffer.
`
`MADV#
`
`03V
`
`MEMORY ADVANCE: For memory write cycles, assertion causes a Qword to be
`drained from the DRAM Write Buffer and the next data to be made available to
`the MD pins of the TDPs. For memory read cycles, assertion causes a Qword to
`be latched in the DRAM Input Register.
`
`PCMD[1:0]
`
`03V
`
`PLINK COMMAND: This field controls how data is loaded into the PLINK input
`and output registers.
`
`HOE#
`
`03V
`
`HOST OUTPUT ENABLE: This signal is used as the output enable for the Host
`Data Bus.
`
`MOE#
`
`03V
`
`MEMORY OUTPUT ENABLE: This signal is used as the output enable for the
`memory data bus. A buffered copy of MOE# also serves as a WE# select for the
`DRAM array.
`
`POE#
`
`03V
`
`PLINK OUTPUT ENABLE: This signal is used as the output enable for the PLINK
`Data Bus.
`
`2.1.6.
`
`CLOCKS (TSC)
`
`Signal
`Name
`
`Type
`
`HCLKIN
`
`15V
`
`Description
`
`HOST CLOCK IN: This pin receives a buffered host clock. This clock is used by all of
`the TSC logic that is in the Host clock domain. This should be the same clock net that is
`delivered to the CPU. The net should tee and have equal lengths from the tee to the
`CPU and the TSC.
`
`PCLKIN
`
`ISV
`
`PCI CLOCK IN: This pin receives a buffered divide-by-2 host clock. This clock is used
`by all of the TSC logic that is in the PCI clock domain.
`
`I PRELIMINARY
`
`• 4826175
`
`0158395 205 •
`
`13
`
`Ex. 1009 / Page 13 of 68
`
`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1009, p. 13
`
`

`
`82437FX TSC AND 82438FX TOP
`
`2.2.
`
`TOP Signals
`
`2.2.1.
`
`DATA INTERFACE SIGNALS (TOP)
`
`Signal
`Name
`
`HD[31:0]
`
`MD[31:0]
`
`Type
`
`Description
`
`1/03V HOST DATA: These signals are connected to the CPU data bus. The CPU data
`bus is interleaved between the two TDPs for every byte, effectively creating an even
`and an odd TOP.
`
`1/0
`3V/5V
`
`MEMORY DATA: These signals are connected to the DRAM data bus. The DRAM
`data bus is interleaved between the two TDPs for every by