IPR2017-00512
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`HTC Corporation and HTC America, Inc.,
`PETITIONERS
`
`v.
`
`Parthenon Unified Memory Architecture LLC,
`PATENT OWNER
`___________
`
`Case IPR2017-00512
`U.S. Patent No. 5,812,789
`Title: VIDEO AND/OR AUDIO DECOMPRESSION AND/OR COMPRESSION DEVICE THAT
`SHARES A MEMORY INTERFACE
`____________
`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. §42.107
`
`
`
`
`
`
`
`
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`HTC Corporation and HTC America, Inc.,
`PETITIONERS
`
`v.
`
`Parthenon Unified Memory Architecture LLC,
`PATENT OWNER
`___________
`
`Case IPR2017-00512
`U.S. Patent No. 5,812,789
`Title: VIDEO AND/OR AUDIO DECOMPRESSION AND/OR COMPRESSION DEVICE THAT
`SHARES A MEMORY INTERFACE
`____________
`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. §42.107
`
`
`
`
`
`
`
`
`
`IPR2017-00512
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`
`TABLE OF CONTENTS
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`I. INTRODUCTION .................................................................................................... 1
`II. STATE OF THE PRIOR ART & THE `789 PATENT ............................................. 2
`III. CLAIM CONSTRUCTION .................................................................................... 5
`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE LIKELIHOOD THAT
`ANY CHALLENGED CLAIM IS INVALID ..................................................................... 6
`A. Bowes, TMS, and Thomas [claims 1–5 and 12–14] ..................................... 6
`1. TMS does not disclose or render obvious “the bus having a sufficient
`bandwidth to enable the decoder to access the memory and operate in real
`time when the first device simultaneously accesses the bus.” ........................... 7
`2. Bowes does not disclose “the bus having a sufficient bandwidth to enable
`the decoder to access the memory and operate in real time when the first
`device simultaneously accesses the bus.” ............................................................ 7
`3. Bowes in combination with Thomas does not render obvious “the bus
`having a sufficient bandwidth to enable the decoder to access the memory
`and operate in real time when the first device simultaneously accesses the
`bus.” ........................................................................................................................ 8
`B. Bowes, TMS, Thomas, and Gove [claims 6 and 8] .................................... 12
`C. Bowes, TMS, Thomas, and Ran [claim 7] .................................................. 13
`D. Bowes, TMS, Thomas, and Celi [claim 11] ................................................ 13
`V. CONCLUSION ..................................................................................................... 14
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`IPR2017-00512
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`
`TABLE OF AUTHORITIES
`
`
`Cases
`In re Fine,
` 837 F.2d 1076 (Fed. Cir. 1988) ............................................................... 12, 13, 14
`
`In re Rambus Inc.,
` 694 F.3d 42 (Fed. Cir. 2012) .................................................................................. 5
`
`In re Wilson,
` 424 F.2d 1382 (CCPA 1970) .................................................................................. 7
`
`Phillips v. AWH Corp.,
` 415 F.3d 1303 (Fed. Cir. 2005) .............................................................................. 6
`
`Toyota Motor Corp. v. Cellport Sys., Inc.,
` Case IPR2015-00633 (PTAB Aug. 14, 2015) ........................................................ 5
`
`Rules
`
`35 U.S.C. § 103 .......................................................................................................... 1
`
`
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`iii
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`IPR2017-00512
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`
`TABLE OF EXHIBITS
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`Exhibit Description
`
`U.S. Patent No. 5,812,789 (“`789 Patent”)1
`U.S. Patent No. 5,546,547 (“Bowes”)
`U.S. Patent No. 5, 001,625 (“Thomas”)
`Declaration of Mitchell A. Thornton (Thornton Decl.”) from
`IPR2016-01135
`Deposition testimony of Robert Colwell, Ph.D. dated February 27,
`2017 (“Colwell Depo.”) from IPR2016-01135
`
`
`
`Exhibit
`No.
`
`1001
`1005
`1007
`2003
`
`2004
`
`
`1 Ex. 1001, 1005, and 1007 are already of record and not attached to this
`Preliminary Response.
`
`iv
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`
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`I.
`
`INTRODUCTION
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`IPR2017-00512
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`The patent owner Parthenon Unified Memory Architecture LLC (“Patent
`
`Owner”) respectfully requests that the Board deny the Petition for Inter Partes
`
`review (“Petition”) filed by HTC Corporation and HTC America, Inc.
`
`(“Petitioner”) regarding certain claims of U.S. Patent No. 5,812,789 (“`789
`
`Patent”) because the Petition fails to demonstrate a reasonable likelihood that the
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`Petitioner would prevail as to at least one of the challenged claims, as required
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`under 34 U.S.C. § 314(a).
`
`The Petition proposes four grounds challenging claims 1–8 and 11–14
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`(“challenged claims”). Specifically, the Petitioner contends that certain challenged
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`claims are invalid as obvious in view of Bowes, TMS, and Thomas (Ground A).
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`The Petitioner also contends that certain dependent challenged claims are obvious
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`in view of Bowes, TMS, Thomas, and Gove (Ground B) or Ran (Ground C) or Celi
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`(Ground D).
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`For the reasons discussed below, Bowes, TMS, and Thomas do not render
`
`claim 1 obvious. Because they depend on claim 1, claims 2–8 and 11–14 are
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`allowable for at least the same reasons. Therefore, there is no reasonable
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`likelihood that the Petitioner would prevail with respect to any of the claims
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`challenged in Grounds A–D, and the Petition should be denied.
`
`1
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`
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`II. STATE OF THE PRIOR ART & THE `789 PATENT
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`IPR2017-00512
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`The computer memory storage requirements of a digital representation of an
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`uncompressed image is dependent on its resolution, color depth, and size in pixels.
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`Video files are comprised of sequences of images that are further enhanced with a
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`corresponding audio track to accompany them. [Ex. 2003, Thornton Decl. at ¶ 29].
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`As a result, a video file quickly becomes large in size. The transmission of
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`uncompressed video files is prohibitively expensive. Id.
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`Accordingly, video files are typically compressed at a transmitting device.
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`[Ex. 2003, Thornton Decl. at ¶ 30]. The compressed file is then transmitted to a
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`receiving device where it is decompressed. Id. To that end, an encoder at the
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`transmitter compresses the video file and a decoder decompresses the file received
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`at the receiver in order to retrieve a facsimile of the original video and audio data.
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`Id. In order to ensure compatibility between devices, a number of standards for
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`encoding and decoding video files were developed. Id. One of those standards was
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`developed by the Motion Picture Experts Group (“MPEG”) and has been adopted
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`as a standard for the communication of video. Id.
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`If a decoder does not operate in real time, the decoded video being displayed
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`would stop periodically between images until the decoder can access the memory
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`and process the subsequent image frame. [Ex. 2003, Thornton Decl. at ¶ 31].
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`2
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`IPR2017-00512
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`Moreover, when using a temporal (intercompression) technique such as the MPEG
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`Standard, some of the images are decoded based on previous images and some
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`based on previous and subsequent images. Id. Accordingly, dropping an image on
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`which the decoding of other images depends is unacceptable as it can result in poor
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`or unrecognizable decoded images. Id. Therefore, it is typically the case that a
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`decoder requires its own dedicated memory. Id. For instance, traditional MPEG
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`decoders require a 2 Mbyte dedicated memory that is utilized during the decoding
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`process. Id. This dedicated memory is necessary to allow the decoder to decode
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`images in real-time without dropping frames that would result in a deterioration of
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`the video quality at the receiver. Id.
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`It is generally desirable to reduce the die area of an integrated circuit device
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`for a given functionality. [Ex. 2003, Thornton Decl. at ¶ 32]. Such a reduction
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`allows for an increase in the number of the die that can be manufactured on a
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`silicon wafer having a given size. Id. For example, a video decoder die would be
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`reduced in size if it did not include a dedicated memory circuit. Id. Moreover, such
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`a dedicated memory of a decoder may remain unused when an image is not being
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`decoded which is inefficient. Id. Accordingly, it is desirable to permit the decoder
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`to share the main memory of the system with other system components. Id.
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`3
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`IPR2017-00512
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`To that end, the `789 Patent is generally directed to sharing both a memory
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`interface and a memory between a video and/or audio decoder and another device
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`contained in an electronic system. [`789 Pat. [Ex. 1001], Abstract; 4:12-22; 4:30-
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`34; 4:40-48; independent claim 1]. Accordingly, the electronic system includes a
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`first device that requires access to the memory and a decoder that requires access
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`to the memory sufficient to maintain real time operation. Id. at claim 1. A memory
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`interface is coupled to the memory, the first device and the decoder. Id. The
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`memory interface includes an arbiter for selectively providing access for the first
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`device and the decoder to the memory. Id. A shared bus is coupled to the memory,
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`the first device and the decoder. Id. The shared bus has sufficient bandwidth to
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`enable the decoder to access the memory and operate in real time when the first
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`device simultaneously accesses the shared bus. Id.
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`A video decoder only requires access to memory during its operation. [Ex.
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`2003, Thornton Decl. at ¶ 34]. In accordance with the implementation of the `789
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`Patent, other devices such as a first device may have exclusive access to a shared
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`memory when the decoder is not operating. Id. In such instances, the first device
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`can use the entire bandwidth of the fast bus to support memory accesses. Id.
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`The fast bus (70) of the `789 Patent has a bandwidth that is at least twice the
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`required bandwidth to support the memory accesses needed to support real time
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`4
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`IPR2017-00512
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`video decoding. [`789 Pat., 6:67-7:2]. Accordingly, the video decoder will
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`typically be using less than 40% of the bandwidth of the fast bus (70) during
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`decoding. [`789 Pat., 7:18-20]. This frees up the remaining bandwidth to be used
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`by other devices such as a first device during the decoder operation. [`789 Pat.,
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`7:20-22]. Because the decoder does not use the entire available bandwidth of the
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`fast bus (70) during real time decoding, the remaining bus bandwidth may be used
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`by other devices such as a first device simultaneously while real time decoding is
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`occurring. [`789 Pat., 7:5-15].
`
`III. CLAIM CONSTRUCTION
`Pursuant to 37 C.F.R. § 42.100(b), “[a] claim in an unexpired patent shall be
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`given its broadest reasonable construction in light of the specification of the patent
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`in which it appears.” The `789 Patent is likely to expire before the Board is likely
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`to issue a final written decision as to the patentability of the challenged claims.
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`Therefore, the claim terms are to be construed in accordance with the standard set
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`forth in Phillips.2 37 C.F.R. § 42.5(b); see Toyota Motor Corp. v. Cellport Sys.,
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`Inc., Case IPR2015-00633, slip op. at 8-10 (PTAB Aug. 14, 2015) (Paper 11); cf.
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`In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir. 2012) (“While claims are generally
`
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`2 The construction of the terms and the analysis of the claims set forth herein
`would have remained the same even if the broadest reasonable interpretation
`standard was applied.
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`5
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`given their broadest possible scope during prosecution, the Board’s review of the
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`claims of an expired patent is similar to that of a district court’s review.”) (internal
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`citation omitted). Under this standard, the claim terms are given their ordinary and
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`accustomed meaning as understood by one having ordinary skill in the art at the
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`time of the invention in the context of the entire patent, considering intrinsic
`
`evidence (the claims, the specification, and the prosecution history), and extrinsic
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`evidence (technical dictionaries, treatises, etc.) to a lesser extent. Phillips v. AWH
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`Corp., 415 F.3d 1303, 1313, 1316-17 (Fed. Cir. 2005).
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`Petitioner proposes maintaining the Board’s construction in IPR2016-01135
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`for the terms “decoder” and “encoder.” [Petition at 14–15.] Petitioner further
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`proposes adopting the Board’s conclusion in IPR2016-01135 that the terms “real
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`time” and “variable bandwidth” do not require a construction. [Id. at 15.] Patent
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`Owner agrees that the Board’s conclusions regarding claim construction in
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`IPR2016-01135 should apply to this proceeding.
`
`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE LIKELIHOOD THAT
`ANY CHALLENGED CLAIM IS INVALID
`
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`A. Bowes, TMS, and Thomas [claims 1–5 and 12–14]
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`Independent claim 1 is not invalid as obvious in view of Bowes, TMS, and
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`Thomas because Bowes, TMS, and Thomas, alone or in combination, fail to
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`disclose “the bus having a sufficient bandwidth to enable the decoder to access the
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`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`memory and operate in real time when the first device simultaneously accesses the
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`bus.” See, e.g., In re Wilson, 424 F.2d 1382 1385 (CCPA 1970) (“All words in a
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`claim must be considered in judging the patentability of that claim against the prior
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`art”).
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`1. TMS does not disclose or render obvious “the bus having a
`sufficient bandwidth to enable the decoder to access the
`memory and operate in real time when the first device
`simultaneously accesses the bus.”
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`Petitioner does not rely on TMS to disclose or render obvious the “when the
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`first device simultaneously accesses the bus” portion of this limitation. [See
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`Petition at 39–41.] Indeed, Dr. Thornton confirms that TMS does not disclose or
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`render obvious this portion of the limitation. [Ex. 2003, Thornton Decl. at ¶ 39.]
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`Accordingly, TMS does not disclose or render obvious this portion of the
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`limitation.
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`2. Bowes does not disclose “the bus having a sufficient bandwidth
`to enable the decoder to access the memory and operate in real
`time when the first device simultaneously accesses the bus.”
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`It is unclear whether Petitioner argues that Bowes discloses the “when the
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`first device simultaneously accesses the bus” portion of this limitation. [See
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`Petition at 40.] In any event, Bowes does not disclose this portion of the
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`limitation. [Ex. 2003, Thornton Decl. at ¶ 40.] Bowes never discloses the CPU
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`using the bus at the same time that the DSP is performing real-time decoding.
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`U.S. Patent No. 5,812,789
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`Indeed, Petitioner has not provided any analysis to support a conclusion that
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`Bowes discloses this portion of the limitation. [See Petition at 40.]
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`3. Bowes in combination with Thomas does not render obvious
`“the bus having a sufficient bandwidth to enable the decoder to
`access the memory and operate in real time when the first
`device simultaneously accesses the bus.”
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`Petitioner argues that Bowes in combination with Thomas renders the “when
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`the first device simultaneously accesses the bus” portion of this limitation obvious.
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`[See Petition at 40–41.] This is incorrect. A POSA would not be motivated to
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`combine Bowes with Thomas for the reasons described below. [Ex. 2003,
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`Thornton Decl. at ¶ 41].
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`The DSP of Bowes requires an extraordinarily large amount of bus
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`bandwidth. [See Ex. 2003, Thornton Decl. at ¶ 42; Ex. 1005 at 1:51–53 (“[A] DSP
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`requires a large amount of bandwidth to memory for processing the sheer volume
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`of data required to effectuate real-time computing.”); 2:25–26 (“the high
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`bandwidth required for real-time processing by a DSP”); 3:21–23 (“The arbitration
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`scheme is tuned to maximize accessibility of the memory bus to the DSP which
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`has by far the greatest bandwidth requirements.”); 6:35–38 (“Many of these
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`functions are real-time operation and require a tremendous amount of the memory
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`bus bandwidth between the DSP and the DRAM of the main memory subsystem
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`14.”); 7:31–32 (“In addition to the DSP’s huge requirement for bandwidth on the
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`IPR2017-00512
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`U.S. Patent No. 5,812,789
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`memory bus . . . .”)] As a result, the Bowes system is “optimized” to support the
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`DSP and make sure that it has the bus bandwidth it needs to perform real-time
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`operations. [See Ex. 2003, Thornton Decl. at ¶ 42; Ex. 1005 at 8:40–42 (“Because
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`the DSP has the largest bus bandwidth requirement, the system is optimized to
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`meet its need and support its real-time operations.”)]
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`Combining Bowes with Thomas to meet this limitation would not support
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`the DSP’s real-time operations because the combined system would effectively
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`halve the bus bandwidth available to the DSP. [Ex. 2003, Thornton Decl. at ¶ 43].
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`To meet this limitation, the DSP in a combined Bowes/Thomas system must be
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`able to use the bus to operate in real-time while the CPU is using the bus at the
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`same time. [Id.] Given the teachings of Thomas, this means that the DSP and
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`CPU will each be using, at most, only half of the available bus bandwidth. [Id.]
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`For example, Thomas teaches bus units that request “system bus access to perform
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`a full bus transfer or a half bus transfer.” [Ex. 1007 at 15:43–44.] The
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`“simultaneous data return” described by Thomas occurs only when the cache
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`memory requests a half bus transfer (as opposed to a full bus transfer), which
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`allows the main memory to use the other half of the bus. [See Ex. 2003, Thornton
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`Decl. at ¶ 43; Ex. 1007 at 15:50–16:2.] Therefore, the DSP in a combined
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`IPR2017-00512
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`U.S. Patent No. 5,812,789
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`Bowes/Thomas system will be limited to half the bandwidth that it would
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`otherwise have in the original Bowes system. [Ex. 2003, Thornton Decl. at ¶ 43].
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`Petitioner’s expert agrees with this analysis of Thomas. For example, Dr.
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`Colwell agrees that Thomas’ bus can support simultaneous bus transactions only
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`when both of the transactions are half bus transfers:
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`[Ex. 2004, Colwell Depo. at 17:2–6.] Dr. Colwell further agrees that the bus units
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`in Thomas can use, at most, only half of the peak bus bandwidth when engaged in
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`a simultaneous bus transaction:
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`[Ex. 2004, Colwell Depo. at 15:3–21.]
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`A POSA would not be motivated to reduce the Bowes DSP’s available bus
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`bandwidth by 50% (or more) when the DSP requires a “tremendous” amount of
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`bandwidth, especially when the entire system should be optimized to guarantee
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`that the DSP has sufficient bandwidth. [Ex. 2003, Thornton Decl. at ¶ 45].
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`Combining Bowes with Thomas would not support the DSP’s real-time operations;
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`it would achieve the exact opposite result. [Id.] Accordingly, a POSA would not
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`be motivated to combine Bowes with Thomas. [Id.]
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`At least for these reasons, independent claim 1 is not invalid as obvious in
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`view of Bowes, TMS, and Thomas. Claims 2–5 and 12–14 depend on independent
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`claim 1 and are therefore allowable for at least the same reasons. In re Fine, 837
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`F.2d 1071, 1076 (Fed. Cir. 1988) (“Dependent claims are nonobvious under § 103
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`if the independent claims from which they depend are nonobvious”).
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`B. Bowes, TMS, Thomas, and Gove [claims 6 and 8]
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`The Petition alleges that claims 6 and 8 are obvious in view of Bowes, TMS.
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`Thomas, and Gove. Claims 6 and 8 depend on independent claim 1. As discussed
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`in Section IV.A., supra, claim 1 is not invalid as obvious in view of Bowes, TMS,
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`and Thomas. The Petition relies on Gove only for its alleged disclosure of certain
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`limitations in claims 6 and 8. [Petition at 54–56.] Therefore, independent claim 1
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`is also not obvious in view of the proposed combination of Bowes, TMS, Thomas,
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`and Gove. Dependent claims 6 and 8 are allowable at least for the same reasons.
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`In re Fine, 837 F.2d 1071, 1076 (Fed. Cir. 1988) (“Dependent claims are
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`nonobvious under § 103 if the independent claims from which they depend are
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`nonobvious”).
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`C. Bowes, TMS, Thomas, and Ran [claim 7]
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`The Petition alleges that claim 7 is obvious in view of Bowes, TMS,
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`Thomas, and Ran. Claim 7 depends on independent claim 1. As discussed in
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`Section IV.A., supra, claim 1 is not invalid as obvious in view of Bowes, TMS,
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`and Thomas. The Petition relies on Ran only for its alleged disclosure of certain
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`limitations in claim 7. [Petition at 56–59.] Therefore, independent claim 1 is also
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`not obvious in view of the proposed combination of Bowes, TMS, Thomas, and
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`Ran. Dependent claim 7 is allowable at least for the same reasons. In re Fine, 837
`
`F.2d 1071, 1076 (Fed. Cir. 1988) (“Dependent claims are nonobvious under § 103
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`if the independent claims from which they depend are nonobvious”).
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`D. Bowes, TMS, Thomas, and Celi [claim 11]
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`The Petition alleges that claim 11 is obvious in view of Bowes, TMS,
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`Thomas, and Celi. Claim 11 depends on independent claim 1. As discussed in
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`Section IV.A., supra, claim 1 is not invalid as obvious in view of Bowes, TMS,
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`and Thomas. The Petition relies on Celi only for its alleged disclosure of certain
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`limitations in claim 11. [Petition at 59–66.] Therefore, independent claim 1 is also
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`not obvious in view of the proposed combination of Bowes, TMS, Thomas, and
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`Celi. Dependent claim 11 is allowable at least for the same reasons. In re Fine,
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`837 F.2d 1071, 1076 (Fed. Cir. 1988) (“Dependent claims are nonobvious under §
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`103 if the independent claims from which they depend are nonobvious”).
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`V. CONCLUSION
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`For the foregoing reasons, the Patent Owner respectfully submits that the
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`Petitioner has not made the threshold showing that there is a reasonable likelihood
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`that it will prevail in demonstrating the invalidity of at least one challenged claim.
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`Therefore, the Patent Owner requests that the Petition be denied.
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`By: /s/ Masood Anjom
`Masood Anjom, Lead Counsel
`Reg. No. 62,167
`Attorney for Patent Owner
`Parthenon Unified Memory
`Architecture, LLC
`
`AHMAD, ZAVITSANOS, ANAIPAKOS,
`ALAVI &MENSING, P.C.
`1221 McKinney Street, Suite 2500
`Houston, TX 77010
`Telephone: 713-655-1101
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`Dated: April 21, 2017
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`IPR2017-00512
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`U.S. Patent No. 5,812,789
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`CERTIFICATE OF SERVICE
`I hereby certify that the Patent Owner’s Preliminary Response under 37
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`C.F.R. §42.107 was served on this Friday, April 21, 2017 by electronic mail to the
`following:
`Lead Counsel for HTC Corp. and HTC
`America, Inc.
`Joseph A. Micallef, Reg. No. 39,772
`SIDLEY AUSTIN LLP
`1501 K Street NW
`Washington, DC 20005
`Email: jmicallef@sidley.com
`
`Back-up Counsel for HTC Corp. and HTC
`America, Inc.
`Stephen M. Everett
`Registration No. 30,050
`SIDLEY AUSTIN LLP
`555 California Street
`Suite 200
`San Francisco, CA 94104
`stephen.everett@sidley.com
`
`Samuel A. Dillon
`Registration No. 65,197
`SIDLEY AUSTIN LLP
`1501 K Street NW
`Washington, DC 2005
`samuel.dillon@sidley.com
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`Dated: April 21, 2017
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`By: /s/ Masood Anjom
`
`Masood Anjom, Lead Counsel
`
`Reg. No. 62,167
`
`Attorney for Patent Owner
`Parthenon Unified Memory
`Architecture, LLC
`
`AHMAD, ZAVITSANOS, ANAIPAKOS,
`ALAVI &MENSING, P.C.
`1221 McKinney Street, Suite 2500
`Houston, TX 77010
`Telephone: 713-655-1101
`
`
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