Paper 1
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`———————
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`———————
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`HTC CORPORATION and HTC AMERICA, INC.,
`Petitioners,
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`v.
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`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner
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`———————
`
`Case IPR2017-00512
`U.S. Patent No. 5,812,789
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`———————
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`
`
`PETITION FOR INTER PARTES REVIEW
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`TABLE OF CONTENTS
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`I.
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`INTRODUCTION ............................................................................................. 1
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`II. MANDATORY NOTICES ............................................................................... 1
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`A. Real Party-in-Interest ................................................................................ 1
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`B. Related Matters ......................................................................................... 1
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`C. Lead and Back-up Counsel and Service Information .............................. 2
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`III. GROUNDS FOR STANDING .......................................................................... 2
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`IV. THE CHALLENGED CLAIMS ARE UNPATENTABLE .............................. 3
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`A. The ’789 Patent ......................................................................................... 3
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`1. Overview .......................................................................................... 3
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`2.
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`Prosecution History .......................................................................... 8
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`B.
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`Identification of Challenges ..................................................................... 9
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`1. Challenged Claims ........................................................................... 9
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`2.
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`Statutory Ground for Challenges ..................................................... 9
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`3. Redundancy .................................................................................... 11
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`C. Claim Construction ................................................................................. 13
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`i.
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`ii.
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`“decoder” ................................................................................ 14
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`“encoder” ................................................................................ 14
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`iii. “real time” ............................................................................... 15
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`iv. “variable bandwidth” .............................................................. 15
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`1.
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`Identification of How the Claims Are Unpatentable ..................... 15
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`

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`
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`i.
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`Challenge #1: Claims 1-5 and 12-14 are obvious under 35
`U.S.C. § 103 over Bowes in view of TMS and Thomas ........ 15
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`(a) Summary of Bowes ......................................................................... 16
`(b) Summary of TMS320C8x System-Level Synopsis ........................ 19
`(c) Reasons to Combine Bowes and TMS ............................................ 20
`(d) Summary of Thomas ....................................................................... 23
`(e) Reasons to Combine Bowes, TMS, and Thomas ............................ 25
`(f) Detailed Analysis ............................................................................ 29
`ii. Challenge #2: Claims 6 and 8 are obvious under 35 U.S.C. §
`103 over Bowes in view of TMS and Thomas, further in view
`of Gove .................................................................................... 51
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`(a) Summary of Gove ........................................................................... 51
`(b) Reasons to Combine Bowes, TMS, Thomas, and Gove ................. 52
`(c) Detailed Analysis ............................................................................ 53
`iii. Challenge #3: Claim 7 is obvious under 35 U.S.C. § 103 over
`Bowes in view of TMS and Thomas, further in view of Ran . 56
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`(a) Summary of Ran ............................................................................. 56
`(b) Reasons to Combine Bowes, TMS, Thomas, and Ran ................... 57
`(c) Detailed Analysis ............................................................................ 58
`iv. Challenge #4: Claim 11 is obvious under 35 U.S.C. § 103 over
`Bowes in view of TMS and Thomas, further in view of Celi 59
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`(d) Summary of Celi ............................................................................. 59
`(e) Reasons to Combine Bowes, TMS, Thomas, and Celi ................... 60
`(f) Detailed Analysis ............................................................................ 61
`V. CONCLUSION ................................................................................................ 66
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`Certificate Of Service................................................................................................. 4
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`I.
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`INTRODUCTION
`HTC Corporation and HTC America, Inc. (“HTC”) respectfully request inter
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`partes review of claims 1-8 and 11-14 of U.S. Patent No. 5,812,789 (“the ’789
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`patent”) (Ex1001). Apple Inc. previously filed a petition for inter partes review of
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`the 789 patent, which was instituted on December 6, 2016. See IPR2016-01135
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`(“the Apple 789 IPR”). This petition presents patentability challenges that are
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`substantively identical to those in the Apple 789 IPR, and relies on the same
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`evidence and the same expert testimony. Accordingly, Petitioners request a
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`determination that this petition warrants institution on the same grounds as the
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`instituted grounds in the Apple 789 IPR, and concurrently moves under 35 U.S.C.
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`§ 315(c) to join this proceeding to the instituted Apple 789 IPR. See Paper 2
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`(Petitioners’ Motion for Joinder).
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`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`The real parties-in-interest are HTC Corporation and HTC America, Inc.
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`B. Related Matters
`The ’789 Patent has been asserted in the following district court
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`proceedings: STMicroelectronics v. Motorola
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`Inc., 4:03-CV-00276
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`(E.D.
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`Tex.); PUMA LLC v. Apple Inc., 2-15-CV-00621 (E.D. Tex.); PUMA LLC v.
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`Huawei Tech. Co., Ltd. et al., 2:14-CV-00687 (E.D. Tex.); PUMA LLC v.
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`Motorola Mobility, Inc., 2:14-CV-00689 (E.D. Tex.); PUMA LLC v. HTC Corp. et
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`1
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`al., 2:14-CV-00690 (E.D. Tex.); PUMA LLC v. LG Elec., Inc. et al., 2:14-CV-
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`00691 (E.D. Tex.); PUMA LLC v. Samsung Elecs. Co. Ltd. et al., No. 2:14-CV-
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`00902 (E.D. Tex.); PUMA LLC v. Qualcomm Inc. et al., No. 2:14-CV-00930
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`(E.D. Tex.); PUMA LLC v. ZTE Corp. et al., No. 2:15-CV-00225 (E.D. Tex.);
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`and PUMA LLC v. LG Electronics MobileComm, USA, 2-15-CV-01950 (E.D.
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`Tex.);
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`Additionally, the ’789 Patent has been challenged in the following inter
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`partes
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`review proceedings:
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`IPR2015-01944
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`(terminated),
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`IPR2016-00664
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`(terminated),
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`IPR2016-00847
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`(instituted),
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`IPR2016-00923
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`(instituted), and
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`IPR2016-01135 (instituted).
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`C. Lead and Back-up Counsel and Service Information
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`Lead counsel is Joseph A. Micallef (Reg. No. 39,772). Backup counsel is
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`Samuel A. Dillon (Reg. No. 65,197). Service information: Sidley Austin LLP,
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`1501 K Street, N.W., Washington, D.C. 20005. Telephone: 202-736-8492, Fax:
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`202-736-8711, E-mail: iprnotices@sidley.com. Petitioners consent to electronic
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`service.
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`III. GROUNDS FOR STANDING
`Petitioners certify that the ’789 patent is available for inter partes review
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`and that they are not barred or estopped from requesting an inter partes review
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`challenging the patent claims on the grounds identified in the petition. Neither
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`2
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`Petitioners, nor any party in privity with Petitioners, have filed a civil action
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`challenging the validity of any claim of the ’789 patent. See 35 U.S.C. § 315(a)(1).
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`While Petitioners were served with a complaint alleging infringement of the ’789
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`patent more than one year before the date this petition is filed, the time limitation
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`of 35 U.S.C. § 315(b) “shall not apply to a request for joinder under” 35 U.S.C. §
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`315(c). Because this petition is accompanied by a Motion for Joinder (Paper 2), it
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`complies with 35 U.S.C. § 315(b). See, e.g., Dell Inc. v. Network-1 Security
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`Solutions, Inc., IPR2013-00385, Paper 17 at 4-5.
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`IV. THE CHALLENGED CLAIMS ARE UNPATENTABLE
`As explained below and in the declaration of Dr. Robert Colwell, Ph.D.
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`(Ex1003), the concepts described and claimed in the ’789 Patent were not novel.
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`This petition explains where each element of claims 1-8 and 11-14 is found in the
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`prior art and why the claims would have been obvious to a person of ordinary skill
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`in the art before the earliest claimed priority date of the ’789 Patent. As explained
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`below, the Board should institute trial and cancel the challenged claims as
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`unpatentable.
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`A. The ’789 Patent
`1. Overview
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`3
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`The ’789 Patent was filed on August 26, 1996. The ’789 Patent has 33
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`claims in total, including independent claims 1, 15, and 29, of which independent
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`claim 1 is challenged by the present petition.
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`The ’789 Patent describes an electronic system with a first device and a
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`“video and/or audio decompression and/or compression device” that share a
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`memory interface in a manner that permits the device to operate in real time.
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`Ex1001, Abstract. In order to fit digital media, such as movies, onto “conventional
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`recording medium, such as a CD,” it was already known to “compress video and
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`audio sequences before they are transmitted or stored.” Id. at 1:25-34. For
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`compression/decompression, “[t]he MPEG standards are currently well accepted
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`standards for one way communication. H.261, and H.263 are currently well
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`accepted standards for video telephony.” Id. at 1:56-59; Ex1003, ¶ 23.
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`The ’789 Patent further states that electronic systems added decoders to
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`these systems in order to “allow them to display compressed sequences” and
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`encoders “to allow the system to compress video and/or audio sequences to be
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`transmitted or stored.” Ex1001, 1:64-2:2. The ’789 Patent continued that a decoder
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`for MPEG sequences “typically … requires a 2 Mbyte memory,” and that such
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`memory was “dedicated to the MPEG decoder 10 and increases the price of adding
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`a decoder 10 to the electronic system.” Id. at 2:28-31; Ex1003, ¶ 24.
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`4
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`The ’789 Patent allegedly addresses these problems by having the “video
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`and/or audio decompression and/or compression device share[] a memory interface
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`and the memory with the first device.” Ex1001, 3:67-4:2. An arbiter is used “to
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`arbitrate between the two devices when one of them is requesting access to the
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`memory.” Id. at 4:4-8. The ’789 Patent explains that its proposed solution results in
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`cost reduction “due to the fact that the video and/or audio decompression and/or
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`compression device does not need its own dedicated memory but can share a
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`memory with another device and still operate in real time.” Id. at 4:30-34. Figure 2
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`illustrates an electronic system containing a device having a memory interface and
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`an encoder and decoder:
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`5
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`Ex1001, Fig. 2
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`Ex1003, ¶¶ 25, 26.
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`
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`The ’789 Patent further explains that its real time operation is made possible
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`through an arbiter, where requests obtain access to the memory through the arbiter
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`based on the priority scheme, which “can be any priority scheme that ensures that
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`the decoder/encoder 45 gets access to the memory 50 often enough and for enough
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`of a burst length to operate properly, yet not starve the other devices sharing the
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`memory.” Ex1001, 10:9-24; Ex1003, ¶ 27.
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`6
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`In claim 1 of the ’789 Patent, a “first device” and a “decoder” both require
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`access to a memory. As explained by the ’789 Patent, the “first device” “can be a
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`processor, a core logic chipset, a graphics accelerator, or any other device that
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`requires access to the memory 50, and either contains or is coupled to a memory
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`interface.” Ex1001, 5:19-22. Further, the ’789 Patent refers to “a video and/or
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`audio decompression device” as a “decoder.” Id. at 1:48-51; Ex1003, ¶ 30.
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` The “first device” and the “decoder” are coupled to a memory and an
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`arbiter, all of which are coupled to a “shared bus.” The “shared bus” is claimed as
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`having a “sufficient bandwidth” to enable the “decoder” to operate in real time
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`“when the first device simultaneously accesses the bus.” According to the ’789
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`Patent, “[a] goal is to have the decoder/encoder 45 operate in real time without
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`dropping so many frames that it becomes noticeable to the human viewer of the
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`movie. To operate in real time the decoder/encoder 45 should decoder and/or
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`encode images fast enough so that any delay in decoding and/or encoding cannot
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`be detected by a human viewer.” Ex1001, 6:41-46. The ’789 Patent continues that
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`“[t]o operate in real time the required bandwidth should be lower than the
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`bandwidth of the bus.” Id. at 6:52-53; Ex1003, ¶¶ 31-32.
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`As discussed below in more detail, the system presented in the ’789 Patent—
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`sharing a memory between multiple devices and arbitrating access thereto between
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`7
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`the devices—was well known to persons of ordinary skill in the art before the
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`earliest alleged priority date of the ’789 Patent. Ex1003, ¶¶ 28-29, 33-34.
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`2.
`Prosecution History
`The ’789 Patent issued on September 22, 1998 from Application No.
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`08/702,911 filed on Aug. 26, 1996.
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`The claims of Application No. 08/702,911, which issued as the ’789 Patent,
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`were rejected just once during prosecution. In response, the Applicants deleted a
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`recitation of “a fast bus coupled to the first device and the decoder” in independent
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`claim 1 and added the limitation “and a shared bus coupled to the memory, the first
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`device, and the decoder, the bus having a sufficient bandwidth to enable the
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`decoder to access the memory and operate in real time when the first device
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`simultaneously accesses the bus.” Ex1002, p. 106.
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`In arguing against the rejection, the Applicants asserted that the references
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`either did not disclose arbitration “for accomplishing real time operation of the
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`decoder” or were “not concerned with real time operation.” Id. at pp. 108-109. The
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`Examiner allowed the application in response to the amendment and arguments
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`filed. Ex1002, pp. 112-115.
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`As illustrated herein, the prior art teaches a memory bus and an arbiter
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`circuit that perform these functions in support of real time operation of a DSP
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`while other devices are simultaneously accessing the memory bus.
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`8
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`B.
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`Identification of Challenges
`1.
`Challenged Claims
`Claims 1-8 and 11-14 of the ’789 Patent are challenged in this petition.
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`2.
`Statutory Ground for Challenges
`Challenge #1: Claims 1-5 and 12-14 are obvious under 35 U.S.C. § 103
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`over U.S. Patent No. 5,546,547 to Bowes et al. (“Bowes”) in view of TMS320C8x
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`System-Level Synopsis (“TMS”).
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`Bowes was filed January 28, 1994 and issued August 13, 1996, and for
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`purposes of this Petition is prior art to the ’789 Patent at least under (pre-AIA) 35
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`U.S.C. §§ 102(a) and (e).
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`TMS is an official Texas Instruments (TI) publication that was obtained
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`from TI’s website. Ex1020, ¶ 3. TMS has a copyright date of 1995 and is identified
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`as being printed in September 1995. See Ex1006, cover page. Further, a
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`contemporaneous TI manual (Ex1019, “Software Guide”) indicates that TMS and
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`other TI documents describing the TMS320C8x could have been obtained in
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`November 1995 by calling the Texas Instruments Literature Response Center.
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`Ex1019, p. iv (“[t]o obtain a copy of any of these TI documents [including TMS,
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`Ex1006], call the Texas Instruments Literature Response Center at (800) 477–
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`8924.”). The Software Guide is also an official TI publication obtained from TI’s
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`website with a copyright date of 1995 and is identified as being printed in
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`November 1995. Ex1020, ¶ 4.
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`9
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`Accordingly, TMS was a printed, ancient document that could be ordered by
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`the public at least as of November 1995 and thus was publicly available at least by
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`November 1995. TMS is thus, for purposes of this Petition, prior art to the ’789
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`Patent at least under (pre-AIA) 35 U.S.C. § 102(a).
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`Challenge #2: Claims 6 and 8 are invalid under 35 U.S.C. § 103 over
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`Bowes in view of TMS, further in view of “The MVP: A Highly-Integrated Video
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`Compression Chip,” R.J. Gove, Proceedings of the IEEE Data Compression
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`Conference (DCC ’94), pp. 215-224 (“Gove”).
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`Gove was included in the proceedings of the Data Compression Conference
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`held March 29-31, 1994. Moreover, the copyright registration filed with the
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`Copyright Office indicates Gove was published March 29, 1994. See Ex1008;
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`Ex1020; see also Ex1003, ¶ 96. Gove is thus, for purposes of this Petition, prior art
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`to the ’789 Patent at least under (pre-AIA) 35 U.S.C. § 102(b).
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`Challenge #3: Claim 7 is invalid under 35 U.S.C. § 103 over Bowes in view
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`of TMS, further in view of U.S. Patent No. 5,768,533 to Ran (“Ran”). Ran was
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`filed on September 1, 1995 and issued June 16, 1998, and for purposes of this
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`Petition is prior art to the ’789 Patent at least under (pre-AIA) 35 U.S.C. § 102(e).
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`Challenge #4: Claim 11 is invalid under 35 U.S.C. § 103 over Bowes in
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`view of TMS, further in view of U.S. Patent No. 5,742,797 to Celi et al. (“Celi”).
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`Celi was filed on August 11, 1995 and issued April 21, 1998, and for purposes of
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`10
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`this Petition is prior art to the ’789 Patent at least under (pre-AIA) 35 U.S.C. §
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`102(e).
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`3.
`Redundancy
`The ’789 Patent is currently the subject of inter partes review proceedings
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`IPR2016-00847, IPR2016-00923, and IPR2016-01135 (to which joinder is sought).
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`The challenges presented in the instant petition rely on different prior art
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`combinations, different arguments regarding the asserted prior art, and different
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`expert declaration testimony than those relied upon in IPR2016-00847 and
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`IPR2016-00923. See, e.g., Nestle USA, Inc., v. Steuben Foods, Inc., IPR2014-
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`01235, Paper 12 at 7 (PTAB 2014) (declining to deny petition under § 325(d)
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`where petition relied on “combination of references previously not considered and
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`[was] supported by a declaration previously not considered”); see also Tandus
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`Flooring, Inc. v. Interface, Inc., IPR2013-00333, Paper 16 at 6 (PTAB 2013)
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`(declining to deny petition under § 325(d) where petitioner presented new
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`declaration evidence).
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`The arguments presented in the present petition could not have been
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`presented in IPR2016-00847 because that filing sought joinder with already-
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`instituted IPR2015-01944. When filing a petition with a motion to join, the
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`conditions for joinder can be satisfied by filing substantively identical grounds. See
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`Sony Corp. v. Memory Integrity, LLC, IPR2015-01353, Paper 11 at 4-6
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`11
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`(determining that conditions for joinder were satisfied because grounds asserted
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`were substantively identical to those instituted with same prior art, arguments, and
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`evidence). Accordingly, Petitioners filed IPR2016-00847 on April 6, 2016 as a
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`“copycat” petition. Because Petitioners sought a motion to join, Petitioners limited
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`the grounds therein so that such petition maintained substantively identical grounds
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`to the petition filed in IPR2015-01944 by Samsung.
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`Moreover, the art and arguments in the present petition are not substantially
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`the same as the IPR2016-00847. The IPR2016-00847 copycat petition relies upon
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`Lambrecht, while the present petition is based on Bowes. Bowes aligns with the
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`technology space alleged by Patent Owner to be infringed in district court
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`litigation. The prior art, combinations, arguments, and expert declaration
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`testimony in the present petition are therefore different from that relied upon in
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`IPR2016-00847 filed previously by Petitioners. See, e.g., Valeo N. Am., Inc. v.
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`Magna Elecs., Inc., IPR2014-01206, Paper 13 at 11 (declining under § 325(d) to
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`find the petitioners’ art and arguments to be the same or substantially the same
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`where the same petitioner had filed a prior petition against the same patent that was
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`instituted and the present petition presented different combinations of prior art and
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`arguments).
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`Accordingly, because the instant petition presents new prior art and
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`arguments, it falls outside of the scope of § 325(d).
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`12
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`C. Claim Construction
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`In
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`inter partes review,
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`the Board applies
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`the broadest reasonable
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`construction (BRI) in light of the specification to claims of an unexpired patent.
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`See 37 C.F.R. § 42.100(b). Under BRI, claim terms are given their ordinary and
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`accustomed meaning as would be understood by one of ordinary skill in the art in
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`the context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
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`1257 (Fed. Cir. 2007). However, patent claims, if expiring prior to a final decision
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`by the Board, are typically construed by the standard applied in the district courts
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`by applying the principles set forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed.
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`Cir. 2005). See, e.g., 37 C.F.R. § 42.108(c). Under this standard, the claim terms
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`are given their ordinary and accustomed meanings as understood by one having
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`ordinary skill in the art at the time of the invention in the context of the entire
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`patent, considering intrinsic evidence, and extrinsic evidence to a lesser extent.
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`Petitioners understand that the ’789 Patent has expired, and is therefore
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`interpreted under the Phillips standard. 1
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`1
`For the purposes of this proceeding so as to streamline possible joinder with
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`the Apple 789 IPR, Petitioners propose that the same claim constructions already
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`adopted by the Board in its institution decision in the Apple 789 IPR be maintained
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`in order to reduce the issues between the parties and because their precise
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`construction does not appear relevant to the merits of this proceeding. Nothing in
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`13
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`

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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`
`
`i.
`
`“decoder”
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`This claim term is found in claims 1-4, 6, 8, and 12-14, as well as in the
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`detailed description. In IPR2016-01135, Apple Inc.’s petition (at 15) proposed that
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`“decoder” be construed as “a video and/or audio decompression device,” but the
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`Board’s institution decision (at 11) construed the term as “hardware and/or
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`software that translates data streams into video or audio information.” Petitioners
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`note that this distinction appears irrelevant to the grounds of patentability instituted
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`in IPR2016-01135, and therefore propose maintaining the Board’s construction for
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`the purposes of this proceeding. See supra n.1.
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`ii.
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`“encoder”
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`This claim term is found in claims 5-7, as well as in the detailed description.
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`In IPR2016-01135, Apple Inc.’s petition (at 16) proposed that “encoder” be
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`construed as “a video and/or audio compression device,” but the Board’s
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`institution decision (at 13) construed the term as “hardware and/or software that
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`translates video and audio information into data streams.” Petitioners note that this
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`distinction appears irrelevant to the grounds of patentability instituted in IPR2016-
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`this filing is intended to conflict in any way with Petitioners’ positions in related
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`district court proceedings with respect to any issue, including claim construction.
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`Petitioners maintain their right to proceed in the underlying district court litigation
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`pursuant to the claim construction positions asserted in that action.
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`14
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`01135, and therefore propose maintaining the Board’s construction for the
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`purposes of this proceeding. See supra n.1.
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`iii.
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`“real time”
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`This claim term is found in claims 1 and 13 and is also used in the detailed
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`description. In IPR2016-01135, Apple Inc.’s petition (at 15-18) proposed that
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`“real time” be construed, but the Board’s institution decision (at 9) found that no
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`construction was necessary. Petitioners agree the precise construction of “real
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`time” appears irrelevant to the grounds of patentability instituted in IPR2016-
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`01135, and therefore propose that no construction is needed for the purposes of this
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`proceeding. See supra n.1.
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`iv.
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` “variable bandwidth”
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`This claim term is found in claim 2, but the detailed description does not
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`explicitly use this term. In IPR2016-01135, Apple Inc.’s petition (at 15-18)
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`proposed that “variable bandwidth” be construed, but the Board’s institution
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`decision (at 9) found that no construction was necessary. Petitioners agree the
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`precise construction of “variable bandwidth” appears irrelevant to the grounds of
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`patentability
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`instituted
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`in IPR2016-01135, and
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`therefore propose
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`that no
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`construction is needed for the purposes of this proceeding. See supra n.1.
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`1.
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`Identification of How the Claims Are Unpatentable
`i. Challenge #1: Claims 1-5 and 12-14 are obvious under 35
`U.S.C. § 103 over Bowes in view of TMS and Thomas
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`15
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`(a)
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`Summary of Bowes
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`Bowes describes the components and operation of an arbitration scheme “for
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`a computer system in which a digital signal processor resides on the computer
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`system’s memory bus without requiring a block of dedicated static random access
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`memory,” thereby reducing “system costs by eliminating the need for an expensive
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`block of SRAM.” Ex1005, Abstract; 6:22-25. Bowes teaches that the computer
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`system includes multiple “bus masters” coupled to a common memory bus. Id. at
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`2:52-3:2, 4:15-17.
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`
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`The examples given in Bowes of “bus masters” include “the CPU, the DSP,
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`the I/O interface and the NuBus controller.” Id. at 7:66-67. These devices are
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`illustrated in the computer system architecture of FIG. 2:
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`16
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`

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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`Ex1005, Fig. 2
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`
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`“[T]he present invention provides for the DSP 20 to reside on the system’s
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`memory bus and operate from the computer system’s main memory subsystem
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`14.” Id. at 6:22-25 (emphasis added).
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`
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`Each bus master may, at some point, access the main memory subsystem 14
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`illustrated in FIG. 2. A person having ordinary skill in the art (POSITA) would
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`recognize that any of the bus masters would have access to the shared main
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`memory subsystem 14 because of their respective access and control of the
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`common memory bus 110. Ex1003, ¶ 62.
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`17
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`A memory controller and arbiter (MCA) 200 arbitrates access for the bus
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`
`
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`masters according to a priority scheme. Ex1005, 7:64-8:10. According to Bowes,
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`“[t]he memory bus 110 provides the signal paths for the exchanging of data
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`between the various elements on the memory bus. Further provided by the memory
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`bus are control lines for such things as bus requests and bus granting signals and
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`other system level control signals” such as that are handled by the memory
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`controller and arbiter (MCA). Id. at 5:13-18.
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`Bowes teaches that the arbitration is an adaptive scheme “that varies access
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`to the memory bus as a function of time and depends upon what operations the
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`various bus masters are requesting.” Id. at 3:15-18. The scheme provides the DSP
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`“with sufficient bandwidth to perform real-time digital signal processing using the
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`system’s dynamic random access memory (DRAM).” Id. at 4:55-58. Bowes
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`teaches that to support the DSP’s real-time operations, the DSP may be “assigned 5
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`time slots among a total of 10 in the arbitration loop.” Id. at 8:44-45.
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`Bowes teaches that the DSP used for real-time operations (e.g., including
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`image processing) can be a general-purpose DSP. Id. at 2:22-30. An example of a
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`general-purpose DSP is the TMS320C80 MVP that was produced by Texas
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`Instruments, Inc., as described below. See Ex1003, ¶¶ 59-66.
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`18
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`Summary of TMS320C8x System-Level Synopsis
`(b)
`TMS describes general-purpose DSP devices that perform video and audio
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`encoding/decoding, namely the “TMS320C8x,” which is a “generation of single-
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`chip multiprocessor digital signal processor (DSP) devices.” Ex1006, p. iii. This
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`generation of single-chip multiprocessor DSPs includes the multimedia video
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`processor, or “MVP.” See id. at pp. iv-v. TMS teaches that the DSP device has a
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`“high degree of on-chip integration” so that multiple devices (e.g., ASICs, RISC
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`processors, DSPs, etc.) may be replaced by the ‘C8x device. Id. at p. SL:1-1.
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`TMS teaches that the single-chip multiprocessor DSP may be used to
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`accelerate applications “such as video compression and decompression, image
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`processing, and graphics manipulation.” Id. at p. A-6.2 Specifically, TMS teaches
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`that the single-chip multiprocessor DSP may be used for moving picture experts
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`group (“MPEG”) video compression/decompression. Id. at p. A-5.
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`The single-chip multiprocessor DSP includes a small 50 KB on-board data
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`cache, divided into multiple dedicated caches. Id. at pp. SL:1-4, SL:2-4, SL:3-7-
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`SL:3-9. The single-chip multiprocessor DSP also has an interface (a “transfer
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`2The ’789 Patent equates video compression to video encoding, and video
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`decompression to video decoding. Video decompression includes video decoding
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`and, therefore, the ‘C8x device taught in TMS would have been known to perform
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`decoding operations. Ex1003, ¶ 68.
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`19
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`controller”) to external memory such as DRAM. Id. at SL:2-3, SL:2-9-SL:2-10.
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`The size of on-chip memory in TMS is far below the amount the ’789 Patent
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`identifies as used for video decoding (around 2 MB), and TMS teaches the benefit
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`of accessing external memory for processing tasks, including both accessing data
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`from external memory and storing the data back in the external memory. Id. at p.
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`SL:2-11; Ex1003, ¶¶ 67-70.
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`(c) Reasons to Combine Bowes and TMS
`Bowes contemplates using its system for real-time processing tasks
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`including “image processing and the like.” Ex1005, 6:32-34. Bowes also
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`contemplates video and video conferencing applications. Id. at 1:34-41. Bowes
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`intends its design to be flexible enough so as to accommodate “new technology
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`and faster DSPs” as they are developed. Id. at 6:41-44. Bowes’ system
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`accomplishes this by not being limited to one particular DSP. Instead, Bowes states
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`that its system is compatible with “off-the-shelf” DSPs. See id. at 2:22-23; 6:30.
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`There are several ways that a POSITA may accommodate new technology and
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`faster DSPs, including selecting dedicated hardware or selecting an off-the-shelf
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`DSP to program, as suggested by Bowes. Ex1003, ¶¶ 71-72.
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`TMS’ single-chip DSP system is an example of such an “off-the-shelf” DSP
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`envisioned by Bowes. Id. at ¶ 73. The TMS single chip DSP system “accelerates
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`applications such as video compression and decompression, image processing
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`
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`20
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`

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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
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`….” Ex1006, p. A-6 (emphasis added). Using the TMS single chip DSP system as
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`the DSP in Bowes provides the advantage of more powerful image processing,
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`including video decompression and compression, with Bowes’ real-time operation
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`support in a shared memory context. A POSITA would have been motivated to
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`implement the “off-the-shelf” DSP taught in Bowes using the teachings of TMS
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`regarding its single chip DSP system as an example DSP that could be
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`implemented in Bowes. Ex1003, ¶ 73.
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`The combination of Bowes’ and TMS’ single chip DSP system teachings
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`would have been predictable because the TMS single chip DSP system is