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` UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE, INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01135
`Patent 5,812,789
`____________
`
`Declaration of Mitchell A. Thornton, Ph. D., P.E.
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`I.
`
`Introduction
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`1.
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`I am over the age of eighteen (18) and otherwise competent to make
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`this declaration.
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`2. My name is Mitchell Aaron Thornton. I am offering this declaration
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`in the matter listed above on behalf of Parthenon Unified Memory Architecture
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`LLC and at the behest of their attorneys Ahmad, Zavitsanos, Anaipakos, Alavi &
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`Mensing P.C. I am being compensated at my usual rate and my compensation is
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`not dependent on any opinions that I may take in this matter, any testimony, or any
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`intermediate or final resolution in the matter.
`
`3.
`
`I understand that the Board has issued an institution Decision in the
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`above-captioned IPR concluding that the Petitioner has established a reasonable
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`likelihood of success with respect to the following grounds (collectively “Instituted
`
`Grounds”):
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`a. Obviousness of claims 1–5 and 12–14 over Bowes, TMS, and
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`Thomas;
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`b. Obviousness of claims 6 and 8 over Bowes, TMS, Thomas, and Gove;
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`c. Obviousness of claim 7 over Bowes, TMS, Thomas, and Ran; and
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`d. Obviousness of claim 11 over Bowes, TMS, Thomas, and Celi.
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`4.
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`This declaration is directed to an analysis of these Instituted Grounds.
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`II. My Background and Qualifications
`
`1
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`5.
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`I earned a Bachelor of Science degree in Electrical Engineering from
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`Oklahoma State University in 1985. In 1990, I earned a Masters of Science degree
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`in Electrical Engineering from the University of Texas at Arlington. In 1993, I
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`earned a Masters of Science degree in Computer Science from Southern Methodist
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`University. I earned a Ph.D. in Computer Engineering from Southern Methodist
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`University in 1995. I am a Licensed Professional Engineer in the states of Texas,
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`Mississippi, and Arkansas. I also hold a Commercial General Radiotelephone
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`Operator License (GROL) with Ship Radar endorsement issued by the Federal
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`Communications Commission (FCC).
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`6.
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`I am currently the Acting Chair of the Department of Computer
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`Science and Engineering at Southern Methodist University. My academic rank is
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`Cecil H. Green Chair of Engineering and Professor in the Department of Computer
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`Science and Engineering and in the Department of Electrical Engineering at
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`Southern Methodist University. Prior to 2002, I served as a faculty member at
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`Mississippi State University in the Department of Electrical and Computer
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`Engineering from 1999 through 2002. I served as a faculty member at the
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`University of Arkansas from 1995 through 1999 in the Department of Computer
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`Systems Engineering. In my university positions, my responsibilities are research,
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`teaching, and providing service in my profession. My teaching and research area of
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`2
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`expertise is generally in the area of computer engineering where I specialize in
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`hardware design for information processing systems.
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`7.
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`In addition to my academic rank of professor, I am also the Research
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`Director of the Darwin Deason Institute for Cyber Security at Southern Methodist
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`University. The Institute mission is to advance the science, policy, application and
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`education of cyber security through basic and problem-driven, interdisciplinary
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`research. As Research Director, I am responsible for the coordination and oversight
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`of all research projects within the auspices of this multi-million dollar endowed
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`research Institute that is comprised of several principal investigators and their
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`associated research teams. In this role, I am routinely involved with several
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`different state-of-the-art projects regarding the technical aspects of information
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`processing system processes, methods, software, and hardware.
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`8.
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`Prior to my academic career, I was employed in the commercial sector
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`as an engineer. I was employed full-time at E-Systems, Inc. (now L3
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`Communications) in Greenville, Texas from 1986 through 1991 and resigned from
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`my position as Senior Electronic Systems Engineer in 1991 to pursue full-time
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`graduate studies in Computer Science and Computer Engineering. My duties at E-
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`Systems involved the design, analysis, implementation, and test of a variety of
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`different electronic systems including various information processing systems
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`centered around signal processing, data transmission and processing, and
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`3
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`communications systems. The communications systems I was involved with
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`processed a variety of different types of signals including data, audio, and video
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`systems. These systems were comprised of components such as receivers,
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`transmitters, computers, and special purpose circuitry.
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`9.
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`During the time I was in graduate school pursuing the Ph.D. degree, I
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`also worked part-time and full-time during the summer of 1992 at a commercial
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`integrated circuit (IC) design company named the Cyrix Corporation. At Cyrix, I
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`was a member of a design team that ultimately produced a microprocessor that is
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`compatible with the Intel Pentium. My duties included the design of the bus
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`controller and memory interface circuitry for this IC.
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`10. My practice and research covers a range of topics centered around
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`hardware design and analysis including secure circuit and embedded system
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`design, electronic design automation (EDA) methods, and algorithms for quantum,
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`classical digital systems, and large systems design. I have also maintained an
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`independent professional engineering practice since 1993 as a sole proprietor that
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`is a registered engineering firm in the state of Texas.
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`11.
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`I am a named inventor on four (4) issued patents and two (2) patent
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`applications under consideration at the USPTO. I have authored or coauthored over
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`200 scholarly publications in the fields of electrical engineering and computer
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`science.
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`4
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`12. My curriculum vitae and testimony list are included in Appendix A to
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`this declaration, which more fully sets forth my qualifications.
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`III. Documents Considered
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`13.
`
`In addition to my knowledge and experience, I have reviewed and
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`relied upon the following materials in performing my analysis:
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`• The `789 Patent (and the publications incorporated by reference therein)
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`and its file history;
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`• Petition for Inter Partes Review of U.S. Patent No. 5,812,789 including
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`all the exhibits [IPR2016-01135];
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`• Patent Owner’s Preliminary Response in IPR2016-01135
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`• Decision on Institution in IPR2016-01135;
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`• Declaration of Robert Colwell, Ph.D [Ex. 1003] (“Colwell Decl.”);
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`• U.S. Patent No. 5,546,547 to Bowes [Ex. 1005] (“Bowes”);
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`• U.S. Patent No. 5,001,625 to Thomas et al. [Ex. 1007] (“Thomas”)
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`• Deposition testimony of Robert Colwell, Ph.D dated February 27, 2017
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`(“Colwell Depo.”).
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`IV. Summary of Opinions
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`14. As detailed below, it is my opinion that the challenged independent
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`claim is not obvious in view of Bowes, TMS, and Thomas and that the challenged
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`dependent claims are also not obvious for at least the same reasons.
`5
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`V. Legal Standards
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`15.
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`I am not an attorney or patent agent, and thus, I have relied upon
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`certain legal factors that have been explained to me. Some of these, which form the
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`legal framework for the opinions I am providing, are summarized below.
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`16.
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`I understand that claims are to be interpreted from the perspective of
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`one of ordinary skill in the art. I understand that in determining the level of
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`ordinary skill in the art, the following factors may be considered: (1) the
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`educational level of the inventor; (2) type of problems encountered in the art; (3)
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`prior art solutions to those problems; (4) rapidity with which innovations are made;
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`(5) sophistication of the technology; and (6) educational level of active workers in
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`the field.
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`17.
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`I understand from reading the Board’s decision that in this inter partes
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`review, claim terms are to be given their broadest reasonable construction in light
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`of the patent specification. I also understand that claim terms are presumed to be
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`given their ordinary and customary meaning as would be understood by one of
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`ordinary skill in the art. Furthermore, I understand that an inventor may provide a
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`contrary definition of a term in the specification, if it is done with reasonable
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`clarity, deliberateness, and precision. I also understand that care must be taken not
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`to read a particular embodiment appearing in the specification into the claim if the
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`claim language is broader than the embodiment.
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`6
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`18.
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`I understand that a claim may be invalid as anticipated or as being
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`obvious.
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`19.
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`I understand that a claim is not patentable and is anticipated if a single
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`prior art reference discloses each and every element recited in the claim, expressly
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`or inherently, such that a person of ordinary skill in the art could practice the
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`disclosed embodiment without undue experimentation. I also understand that the
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`claim elements must be arranged in the reference in the same way as in the claim.
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`20.
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`I understand that an element is inherent in a reference if one of
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`ordinary skill in the art would understand that the reference makes clear that the
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`element, while not expressly disclosed, is necessarily present in the reference.
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`Inherency, however, may not be established by probabilities or possibilities.
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`21.
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`I understand that the obviousness standard is defined in the patent
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`statute (35 U.S.C. § 103(a)). I also understand that a claim is not patentable and is
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`obvious if the differences between a claim and the prior art are such that the
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`claimed subject matter as a whole would have been obvious to a person having
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`ordinary skill in the art at the time the invention was made. I understand that this
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`inquiry involves examination of number of factors including: (1) determining the
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`scope and content of the prior art; (2) ascertaining the differences between the
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`claim and the prior art; (3) resolving the level of ordinary skill in the prior art; and
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`(4) considering any secondary or objective evidence of non-obviousness. I
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`7
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`understand that secondary or objective evidence of non-obviousness include
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`factors such as commercial success, long felt need for the invention, and failure of
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`others.
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`22.
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`I understand that an obviousness analysis involves comparing a claim
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`to the prior art to determine whether the claimed invention would have been
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`obvious to a Person of Ordinary Skill in the Art (“POSA”) in view of the prior art,
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`and in light of the general knowledge in the art. I also understand when a POSA
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`would have reached the claimed invention through routine experimentation, the
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`invention may be deemed obvious.
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`23.
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`I also understand that obviousness can be established by combining or
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`modifying the teachings of the prior art to achieve the claimed invention. It is also
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`my understanding that where there is a reason to modify or combine the prior art to
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`achieve the claimed invention, there must also be a reasonable expectation of
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`success in so doing. I understand that the reason to combine prior art references
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`can come from a variety of sources, not just the prior art itself or the specific
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`problem the patentee was trying to solve. And I understand that the references
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`themselves need not provide a specific hint or suggestion of the alteration needed
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`to arrive at the claimed invention; the analysis may include recourse to logic,
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`judgment, and common sense available to a person of ordinary skill that does not
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`necessarily require explication in any reference. Finally, it is my understanding that
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`8
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`obviousness can be established by choosing from a finite number of identified,
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`predictable solutions, with a reasonable expectation of success.
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`24.
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`I further understand that a patent composed of several elements is not
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`proved obvious merely by demonstrating that each of its elements was,
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`independently, known in the prior art. I further understand that a showing of a
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`suggestion, teaching, or motivation to combine the prior art references is an
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`essential evidentiary component of an obviousness conclusion. I further understand
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`that a claim is not obvious if the references relied upon in a proposed combination
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`teach away from the claimed combination in a way that would deter any
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`investigation into such a combination. For instance, it is my understanding that a
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`reference teaches way from a combination when using it in that combination would
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`produce an inoperative result.
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`VI. Level of Ordinary Skill in the Art
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`25.
`
`In formulating my opinions, I have also considered the viewpoint of a
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`person of ordinary skill in the art (“POSA”) at the time of the filing of the `789
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`Patent.
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`26.
`
`I understand that Dr. Colwell has opined that a person of ordinary
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`skill in the art as of the effective filing date of the `789 Patent would have held a
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`Bachelor of Science degree (or higher degree) in an academic area emphasizing
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`9
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`electrical or computer engineering and had three years of relevant industry
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`experience. [Ex 1003, at ¶ 20.]
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`27. Based upon my knowledge of this field, I conclude that a person of
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`ordinary skill in this art at the time of the filing of the `789 Patent, and for that
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`matter, at all subsequent times through the present, would have held at least a
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`Bachelor’s degree in electrical engineering, computer engineering, or an equivalent
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`degree in a related discipline from an accredited institution of higher learning and
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`at least two to three years’ experience in signal and/or image processing and
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`computer architecture at both the systems and micro-architecture level. In lieu of
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`two to three years of experience, a person of ordinary skill in the art may hold, in
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`addition to a Bachelor’s degree as described above, a Master’s or other graduate
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`degree in electrical or computer engineering with a focus in computer architecture
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`and signal and/or image processing with one year of relevant experience.
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`28. My analysis was performed from the perspective of such a person. If
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`I were to apply the level of ordinary skill as proffered by Dr. Colwell in his
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`declaration, my analysis and conclusions would remain unchanged.
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`VII. State of the Prior Art and the `789 Patent
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`29. The computer memory storage requirements of a digital representation
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`of an uncompressed image is dependent on its resolution, color depth, and size in
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`pixels. Video files are comprised of sequences of images that are further enhanced
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`10
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`with a corresponding audio track to accompany them. As a result, a video file
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`quickly becomes large in size. The transmission of uncompressed video files is
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`prohibitively expensive.
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`30. Accordingly, video files are typically compressed at a transmitting
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`device. The compressed file is then transmitted to a receiving device where it is
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`decompressed. To that end, an encoder at the transmitter compresses the video file
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`and a decoder decompresses the file received at the receiver in order to retrieve a
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`facsimile of the original video and audio data. In order to ensure compatibility
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`between devices, a number of standards for encoding and decoding video files
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`were developed. One of those standards was developed by the Motion Picture
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`Experts Group (“MPEG”) and has been adopted as a standard for the
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`communication of video.
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`31.
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`If a decoder does not operate in real time, the decoded video being
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`displayed would stop periodically between images until the decoder can access the
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`memory and process the subsequent image frame. Moreover, when using a
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`temporal (intercompression) technique such as the MPEG Standard, some of the
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`images are decoded based on previous images and some based on previous and
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`subsequent images. Accordingly, dropping an image on which the decoding of
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`other images depends is unacceptable as it can result in poor or unrecognizable
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`decoded images. Therefore, it is typically the case that a decoder requires its own
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`11
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`dedicated memory. For instance, traditional MPEG decoders require a 2 Mbyte
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`dedicated memory that is utilized during the decoding process. This dedicated
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`memory is necessary to allow the decoder to decode images in real-time without
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`dropping frames that would result in a deterioration of the video quality at the
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`receiver.
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`32.
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`It is generally desirable to reduce the die area of an integrated circuit
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`device for a given functionality. Such a reduction allows for an increase in the
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`number of the die that can be manufactured on a silicon wafer having a given size.
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`For example, a video decoder die would be reduced in size if it did not include a
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`dedicated memory circuit. Moreover, such a dedicated memory of a decoder may
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`remain unused when an image is not being decoded which is inefficient.
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`Accordingly, it is desirable to permit the decoder to share the main memory of the
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`system with other system components.
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`33. To that end, the `789 Patent is generally directed to sharing both a
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`memory interface and a memory between a video and/or audio decoder and
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`another device contained in an electronic system. [`789 Pat. [Ex. 1001],
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`Abstract; 4:12-22; 4:30-34; 4:40-48; independent claim 1]. Accordingly, the
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`electronic system includes a first device that requires access to the memory and
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`a decoder that requires access to the memory sufficient to maintain real time
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`operation. Id. at claim 1. A memory interface is coupled to the memory, the first
`12
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`device and the decoder. Id. The memory interface includes an arbiter for
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`selectively providing access for the first device and the decoder to the memory.
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`Id. A shared bus is coupled to the memory, the first device and the decoder. Id.
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`The shared bus has sufficient bandwidth to enable the decoder to access the
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`memory and operate in real time when the first device simultaneously accesses
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`the shared bus. Id.
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`34. A video decoder only requires access to memory during its operation.
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`In accordance with the implementation of the `789 Patent, other devices such as a
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`first device may have exclusive access to a shared memory when the decoder is not
`
`operating. In such instances, the first device can use the entire bandwidth of the
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`fast bus to support memory accesses.
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`35. The fast bus (70) of the `789 Patent has a bandwidth that is at least
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`twice the required bandwidth to support the memory accesses needed to support
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`real time video decoding. [`789 Pat., 6:67-7:2]. Accordingly, the video decoder
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`will typically be using less than 40% of the bandwidth of the fast bus (70) during
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`decoding. [`789 Pat., 7:18-20]. This frees up the remaining bandwidth to be used
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`by other devices such as a first device during the decoder operation. [`789 Pat.,
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`7:20-22]. Because the decoder does not use the entire available bandwidth of the
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`fast bus (70) during real time decoding, the remaining bus bandwidth may be used
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`13
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`by other devices, such as a first device, simultaneously while real time decoding is
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`occurring. [`789 Pat., 7:5-15].
`
`VIII. Claim Construction
`36.
`I understand that the Board has construed the term “decoder” to mean
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`“hardware and/or software that translates data streams into video or audio
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`information.” (Institution Decision, Paper 7, at 11).
`
`37.
`
`I understand that the Board has construed the term “encoder” to mean
`
`“hardware and/or software that translates video and audio information into data
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`streams.” (Institution Decision, Paper 7, at 13).
`
`38.
`
`I have used the Board’s construction of the terms “decoder” and
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`“encoder” in performing my analysis. I have used the plain and ordinary meaning
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`of the remaining claim terms when performing my analysis.
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`IX. Analysis of Instituted Grounds
`
`A. Claim 1
`
`1) Bowes, TMS, and Thomas fail to disclose or render obvious “the bus
`having a sufficient bandwidth to enable the decoder to access the
`memory and operate
`in real
`time when
`the
`first device
`simultaneously accesses the bus”
`
`39. Dr. Colwell does not contend that TMS discloses or renders obvious
`
`this limitation. I agree that TMS does not disclose or render obvious this
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`limitation.
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`40.
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`It is unclear whether Dr. Colwell contends that Bowes discloses the
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`“when the first device simultaneously accesses the bus” portion of this limitation.
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`In any event, Bowes does not disclose this portion of the limitation. Bowes never
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`discloses the CPU using the bus at the same time that the DSP is performing real-
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`time decoding. Indeed, Dr. Colwell has not provided any analysis to support a
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`conclusion that Bowes discloses this portion of the limitation.
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`41. Dr. Colwell contends that the combination of Bowes with Thomas
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`renders the “when the first device simultaneously accesses the bus” portion of this
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`limitation obvious. [Ex. 1003 at 55–56.] I disagree. A POSA would not be
`
`motivated to combine Bowes with Thomas for the reasons described below.
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`42. The DSP of Bowes requires an extraordinarily large amount of bus
`
`bandwidth. [See Ex. 1005 at 1:51–53 (“[A] DSP requires a large amount of
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`bandwidth to memory for processing the sheer volume of data required to
`
`effectuate real-time computing.”); 2:25–26 (“the high bandwidth required for real-
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`time processing by a DSP”); 3:21–23 (“The arbitration scheme is tuned to
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`maximize accessibility of the memory bus to the DSP which has by far the greatest
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`bandwidth requirements.”); 6:35–38 (“Many of these functions are real-time
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`operation and require a tremendous amount of the memory bus bandwidth between
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`the DSP and the DRAM of the main memory subsystem 14.”); 7:31–32 (“In
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`addition to the DSP’s huge requirement for bandwidth on the memory bus . . . .”)]
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`As a result, the Bowes system is “optimized” to support the DSP and make sure
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`that it has the bus bandwidth it needs to perform real-time operations. [See Ex.
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`1005 at 8:40–42 (“Because the DSP has the largest bus bandwidth requirement, the
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`system is optimized to meet its need and support its real-time operations.”)]
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`43. Combining Bowes with Thomas to meet this limitation would not
`
`support the DSP’s real-time operations because the combined system would
`
`effectively halve the bus bandwidth available to the DSP. To meet this limitation,
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`the DSP in a combined Bowes/Thomas system must be able to use the bus to
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`operate in real-time while the CPU is using the bus at the same time. Given the
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`teachings of Thomas, this means that the DSP and CPU will each be using, at
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`most, only half of the available bus bandwidth. For example, Thomas teaches bus
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`units that request “system bus access to perform a full bus transfer or a half bus
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`transfer.” [Ex. 1007 at 15:43–44.] The “simultaneous data return” described by
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`Thomas occurs only when the cache memory requests a half bus transfer (as
`
`opposed to a full bus transfer), which allows the main memory to use the other half
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`of the bus. [See Ex. 1007 at 15:50–16:2.] Therefore, the DSP in a combined
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`Bowes/Thomas system will be limited to half the bandwidth that it would
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`otherwise have in the original Bowes system.
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`44.
`
`I note that Dr. Colwell agrees with my analysis of Thomas. For
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`example, Dr. Colwell agrees that Thomas’ bus can support simultaneous bus
`
`transactions only when both of the transactions are half bus transfers:
`
`[Colwell Depo. at 17:2–6.] Dr. Colwell further agrees that the bus units in Thomas
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`can use, at most, only half of the peak bus bandwidth when engaged in a
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`simultaneous bus transaction:
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`[Colwell Depo. at 15:3–21.]
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`45. A POSA would not be motivated to reduce the Bowes DSP’s
`
`available bus bandwidth by 50% (or more) when the DSP requires a “tremendous”
`
`amount of bandwidth, especially when the entire system should be optimized to
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`guarantee that the DSP has sufficient bandwidth. Combining Bowes with Thomas
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`would not support the DSP’s real-time operations; it would achieve the exact
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`opposite result. Accordingly, a POSA would not be motivated to combine Bowes
`
`with Thomas.
`
`B. Claims 2–5 and 12–14
`
`46.
`
` It my understanding that claims 2–5 and 12–14 depend on
`
`independent claim 1. As discussed above, Bowes, TMS, and Thomas do not
`
`render independent claim 1 obvious. Therefore, it is my opinion that claims 2–5
`
`and 12–14 are not obvious at least for the same reasons.
`
`C. Claims 6 and 8
`
`47.
`
` It my understanding that claims 6 and 8 depend on independent claim
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`1. As discussed above, Bowes, TMS, and Thomas do not render independent
`
`claim 1 obvious. Therefore, it is my opinion that claims 6 and 8 are not obvious at
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`least for the same reasons.
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`D. Claim 7
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`48.
`
`It my understanding that claim 7 depends on independent claim 1. As
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`discussed above, Bowes, TMS, and Thomas do not render independent claim 1
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`obvious. Therefore, it is my opinion that claim 7 is not obvious at least for the
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`same reasons.
`
`E. Claim 11
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`19
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`49.
`
`It my understanding that claim 11 depends on independent claim 1.
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`As discussed above, Bowes, TMS, and Thomas do not render independent claim 1
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`obvious. Therefore, it is my opinion that claim 11 is not obvious at least for the
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`same reasons.
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`X. Conclusion
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`50. For the reasons discussed above, it is my opinion that claims 1–5 and
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`12–14 are not obvious over Bowes, TMS, and Thomas; claims 6 and 8 are not
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`obvious over Bowes, TMS, Thomas, and Gove; claim 7 is not obvious over Bowes,
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`TMS, Thomas, and Ran; and claim 11 is not obvious over Bowes, TMS, Thomas,
`
`and Celi.
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`51.
`
`I reserve the right to amend or supplement this declaration based on,
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`among other things, new evidence presented and/or new positions set forth by the
`
`Petitioners or on their behalf, including but not limited to additional materials
`
`provided to me for analysis in regard to the Petition.
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`52.
`
`I, Mitchell A. Thornton, do hereby declare and state, that all
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`statements made herein of my own knowledge are true and that all statements
`
`made on information and belief are believed to be true; and further that these
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`statements were made with the knowledge that willful false statements and the like
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`so made are punishable by fine or imprisonment, under Section 1001 of Title 18 of
`
`the United States Code.
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`20
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`Executed on: __March 9, 2017__
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`
`
`__________________________
`
`Mitchell A. Thornton
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`21
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`APPENDIX A
`APPENDIX A
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`PUMA Exhibit 2003
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`HTC v. PUMA,IPR2017-00512
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`PUMA Exhibit 2003
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`
`
`
`Mitchell Aaron Thornton
`10118 Woodlake Drive
`Dallas, Texas 75243
`mitcht@ieee.org
`
`
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`
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`EDUCATION
`• Ph.D., computer engineering, Southern Methodist University, Dallas, Texas (1995)
`• M.S., computer science, Southern Methodist University, Dallas, Texas (1993)
`• M.S., electrical engineering, University of Texas at Arlington, Arlington, Texas (1990)
`• B.S., electrical engineering, Oklahoma State University, Stillwater, Oklahoma (1985)
`
`
`LICENSES AND CERTIFICATIONS
`• Licensed Professional Engineer: Texas (70202), Mississippi (14477), and Arkansas (9255)
`• Registered Engineering Firm in State of Texas: Mitchell A Thornton, PE; F-6940
`• FCC Licenses: Commercial General Radiotelephone Operator License (GROL) with ship radar
`endorsement, call sign PG00028247; Amateur Radio Operator, Extra Class License, call sign
`KE5CDJ; General Mobile Radio License, call sign WQBX350
`• Electronic Technician diploma, graduate of two-year technical electronics program in the Tulsa
`area Vocational Technical School (1981)
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`EMPLOYMENT
`•
`2017-present, Acting Chair, Dept. of Computer Science and Engineering, Southern Methodist
`University
`2002-present: Cecil H. Green Chair of Engineering, (since Feb. 2015), Professor (Sept. 2006 –
`Jan. 2015), Associate Professor (2002-2006), Department of Computer Science and Engineering,
`and by courtesy, Department of Electrical Engineering, Southern Methodist University.
`Appointed with tenure in August 2002.
`2017-present: Research Director, Darwin Deason Institute for Cyber Security, Southern Methodist
`University.
`2015-2016: Interim Associate Director, Darwin Deason Institute for Cyber Security, Southern
`Methodist University.
`2014-2016: Technical Director, Darwin Deason Institute for Cyber Security, Southern Methodist
`University.
`1999-2002: Associate Professor, Department of Electrical and Computer Engineering, Mississippi
`State University, awarded tenure in May 2001.
`1995 to 1999: Associate Professor (1999), Assistant Professor (1995-99), Department of
`Computer Systems Engineering, and by courtesy, the Department of Electrical Engineering and
`the Department of Computer Science, University of Arkansas, awarded tenure in May 1999.
`1991 to 1995: Teaching Assistant (1991-93), Research Assistant (U.S. Superconducting
`Supercollider laboratories & NSF) (1993-95), Department of Computer Science and Engineering,
`Southern Methodist University
`1992: Design Engineer, Cyrix Corporation (full-time in summer, part time in Fall’92/1993)
`1986-1991: Sr. Electronic Systems Engineer (1990-91), Electronics Systems Engineer (1987-90),
`Engineer Analyst (1985-87), E-Systems, Inc, (now L-3 Communications Systems)
`1982-1984: Research Technician, Amoco Research Center (full-time in summers)
`
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`RESEARCH INTERESTS
`
`EDA/CAD methods and algorithms for quantum, classical digital systems, and large systems
`design including synthesis, verification, asynchronous, security, and disaster and fault tolerant
`circuit techniques. Emphasis on modeling and method development for information technology
`hardware/software, security design/verification, and the mathematical basis of conventional,
`asynchronous, reversible, and quantum logic. Practice areas include computer architecture,
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`peripheral design, embedded systems, and ASIC/FPGA design and implementation. Hardware,
`software, and firmware design and analysis. Deep familiarity with standards, various high-level
`software languages, numerous assemblers, EDA/CAD tools, and hardware description languages
`(both Verilog and VHDL).
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`FUNDED RESEARCH
`•
`(PI) Design and Implementation of OBDD Variable Ordering/Reordering Methods, National
`Science Foundation, 10/01/96 – 09/30/00, NSF/CISE/CCR/DA-9633085, $105,518.
`(PI) Design and Simulation of a Processing Element Node for a Decoupled Multi-Threaded
`Computer, Arkansas Science and Technology Authority, 10/01/96 - 09/30/97, 97-B-12, $34,133.
`(PI) Infrastructure and Faculty Fellowship Request for Configurable Computing, Arkansas Space
`Grant Consortium/NASA, 10/01/97 – 03/31/99, $5,553.
`(Co-PI) High Speed Parallel Fiber Optic Data Bus Components for NMP, Space Photonics, Inc.,
`07/01/98 – 10/31/98, $58,000.
`(PI) Implementation of ASM using an FPGA Based Co-processor, Acxiom Corporation with
`100% match from the Arkansas Science and Technology Authority, 99-A-01, 09