Apple Inc. v. Parthenon
`Ex. 1017 / Page 1 of 5
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 1
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`Ex. 1017 / Page 2 of 5
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 2
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`THE PENTIUM® FAMILY-A TECHNICAL OVERVIEW
`
`This article begins by presenting an overview of the
`Pentium processor. It then details the key technological
`features that enable the Intel solution to meet the mar-
`ket’s evolving requirements for high performance, con-
`tinued software compatibility, and advanced function-
`ality.
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`Intel’s Pentium® processor family combines the per-
`formancetraditionally associated with minicomputers
`and workstations with the flexibility. and compatibility
`that characterize the personal computer platform. De-
`signed to meet the needs of today’s and tomorrow's
`sophisticated software applications, the Pentium proc-
`essor extends the range of Intel’s microprocessor archi-
`tecture to new heights, blurring previous distinctions
`between hardware platforms and creating an entirely
`new realm of possibilities for notebook computers,
`desktop PCs, and servers.
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` intel.
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`THE WORLD'S BEST PERFORMANCE
`FOR ALL PC SOFTWARE
`The Pentium processor family includes the highest per-
`forming members of Intel’s family of microprocessors.
`
`®
`L
`75/90/100/120/133CoreFrequency
`ExternalBusinterface
`iCOMP index
`Pentium® Processor
`;
`
`433 MHz
`66 MHz
`)
`4410
`
`r
`—r
`120 MHz
`60 MHz
`4000
`|
`
`L
`4
`4
`400 MHz
`66/50 MHz
`B15
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`90 MHz
`|
`60 MHz
`735
`75 MHz
`50 MHz
`610
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`the system bus frequencies range from 50 MHz to 66
`While incorporating new features and improvements
`MHz,allowing cost effective system designs.
`madepossible by advances in semiconductor technolo-
`gy, the Pentium processor is fully software compatible
`with previous members of the Intel microprocessor
`family-thereby preserving the value of users’ software
`investments. The Pentium processor meets the de-
`mands of computing in a number of areas: advanced
`operating systems. such as DOS*, Windows", 08/2",
`and UNIX"; computing-intensive graphics applica-
`tions, such as 3-D modcling, computer-aided design’
`engineering (CAD/CAE),large scale financial analysis,
`high-throughput client/server, handwriting, and voice
`recognition, network applications; virtual reality; elec-
`tronic mail that combines many of the above areas; and
`new applications yet to be developed.
`The Pentium processor family was designed using an
`advanced process technology and has features that are
`less than a micron (one-millionth of a meter} in size.
`The Pentium processor (510\60, 567\66) was devel-
`oped utilizing 5V, 0.8 micron technology, while the
`Pentium processor
`(61075,
`735\90,
` 815\100.
`1000\120, 1110\133) was designed using 3.3V, 0.6 mi-
`cron and 3.3¥V,0.35 micron technology.
`The increasingly improved Pentium processor family
`brings the users CPUs with higher frequencies, while
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`-
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`THE PENTIUM® PROCESSOR:
`TECHNICAL INNOVATIONS
`A numberof innovative product features contribute to
`the Pentium processor’s unique combination of high
`performance, compatibility, data integrity and upgrad-
`ability. These include:
`@ Superscalar Architecture
`e Separate 8K Code and Data Caches
`@ Writeback MESI Protocolin the Data Cache
`* Dynamic Branch Prediction
`e Pipelined Floating-point Unit
`e Improved Instruction Execution Time
`© 64-Bit Data Bus
`® Bus Cycle Pipelining
`« Address Parity
`Internal Parity Checking
`e Functional Redundancy Checking
`® Execution Tracing
`® Performance Monitoring
`
`Movember 1995
`Order Murnber: 242423-202
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`21
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1017, p. 3
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`Ex. 1017 / Page 3 of 5
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`Ex. 1017 / Page 3 of 5
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 3
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`THE PENTIUM® FAMILY-A TECHNICAL OVERVIEW
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`intel.
`This improves performance without affecting compati-
`bility. In the case of more complex instructions, the
`Pentium processor’s
`enhanced microcode
`further
`boosts performance by employing both dual
`integer
`pipelines to execute instructions.
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`e TEEE 1149.1 Boundary Scan
`® System Management Mode
`® Virtual Mode Extensions
`8 Upgradable With a Future, Pentium OverDrive®
`Processor
`@ Multiprocessor Support
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`In addition to the features listed above, the Pentium
`processor 75/90/100/120/133 offers the following en-
`hancements over the Pentium processor 60/66"
`® Dual Processing Support
`@ SL Power Management Features
`® Fractional Bus Operation
`@ On-chip Local APIC Device
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`Superscalar Architecture
`The Pentium. processor’s superscalar architecture en-
`ables the processor to achieve superior performance by
`executing more than one instruction per clock cycle.
`The term “superscalar” refers to a microprocessor ar-
`chitecture that contains more than one execution unit.
`These execution units, or piplines are where the CPU
`processes the data and instructions that are fed to it by
`the rest of. the system.
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`The Pentium processor’s superscalar implementation
`represents a natural progression from previous genera-
`tions of processors in the 32-bit Intel architecture. The
`Yntel486™™ processor for’ instance,
`is able to, execute
`many instructions in one clock cycle, while previous
`generations of Intel microprocessors require multiple
`clock cycles to execute a single instruction.
`The ability to execute multiple instructions per clock
`cycle is due to the fact that the Pentium processor has
`two pipelines that can execute twoinstructions simulta-
`neously. The Pentium processor’s* dual pipelines exe-
`cute integer instructions in five stages: prefetch, de-
`codel, decode2, execute and writeback. This permits
`several instructions to be in various stages of execution,
`thus increasing processing performance.
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`The Pentium processor also uses hardwired instruc-
`tions to replace many of the microcoded instructions
`used in previous microprocessor generations. Hard-
`wired instructions are simple and commonly used, and
`can be executed by the processor’s hardware without
`requiring microcode.
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`Separate 8K Code and Data Caches
`Pentium processors include separated code and data
`caches integrated on-chip to meet performance goals.
`On-chip caches increase performance by acting as tem-
`porary storage places for commonly-used instructions
`and data, replacing the need to go off-chip to the sys-
`tem’s main memory to fetch information. The separate
`caches reduce bus conflicts and are available more often
`when they are needed.
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`Thé Pentium processor’s code and data ‘caches each
`contain 8 Kbytes of information and both are organized
`as two-way: set associative caches-meaning that they
`save time by searching only pre-specified 32-byte seg-
`ments rather than the entire cache. Each cache has a
`dedicated Translation Lookaside Buffer (TLB) Lo trans-
`late linear addresses to physical addresses.
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`The Pentium processor’s data cacheis configurable to
`be “writeback”or “write through” on a line-by-line ba-
`sis and follows the MEST (Modified, Exclusive, Shared,
`Invalid) protocol. The “writeback” method transfers
`data to the cache without going out to main memory.
`Data is written to main memory only when it is re-
`moved from the cache. In contrast; the “write through”
`method transfer data to the external memory each time
`the processor writes data to the cache. The “writeback”
`technique increases performance by reducing busutili-
`zation and preventing unnecessary bottlenecks in the
`system.
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`To ensure that data in the cache and in main memory
`are consistent;
`the data cache implements the MESI
`protocol during reads and writes. This is especially im-
`portant in a multiprocessor environment.
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`Dynamic Branch Prediction
`Branch prediction is an advanced computing technique
`that boosts performance by keeping the execution pipe-
`lines full. It is accomplished by predetermining the
`mostlikely set of instructions to be executed.
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1017, p. 4
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`Ex. 1017 / Page 4 of 5
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`Ex. 1017 / Page 4 of 5
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 4
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`THE PENTIUM® FAMILY-A TECHNICAL OVERVIEW
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` intel.
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`To understand the concept better, consider a typical
`application program, After each pass through a soft-
`ware loop, the program performs a conditional test to
`determine whether to return to the beginning of the
`loop or to exit and continue on to the next execution
`step. These two paths are'called branches. Dynamic
`branch prediction forecasts which branch the software
`will require, based on the assumption that the previous
`taken branch will be used again. Pentium processors
`make prediction by using a Branch Target Buffer
`(BTB). Pentium processors also implement two pre-
`fetch buffers, one lo prefetch code in’a linear fashion
`and the otherto prefetch code according to the address-
`es in the BTB. As a result, the needed code is always
`prefetched before it is required for execution. In addi-
`lion, the Pentium processors support more sophisticat-
`ed algorithms by using two level branch prediction.
`
`Pipe-lined Floating-Peint Unit
`The 32-bit compute-intensive software applications re-
`quire a high degree of floating-point processing power
`to handle mathematical calculations. As the floating-
`point requirements of personal computer software have
`steadily increased, advances in microprocessor technol-
`ogy have been introduced to satisfy these needs. The
`Intel486 DX processor, for example, wasthefirst Intel
`microprocessor to integrate math coprocessing func-
`tions on-chip; previous-generation Intel processors used
`off-chip math coprocessors whenfloating-point calcula-
`tions were required.
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`The Pentium processor family takes math computation-
`al ability to the next performance level by using an
`enhanced on-chip floating-point unit that incorporates
`sophisticated eight-stage pipeline and hardwired func-
`tions. A three-stage floating-point instruction pipcline
`is appendedto the integer pipelines. Mostfloating-point
`instructions begin execution in one of the integer pipe-
`lines, then move on to the floating-point pipeline. In
`addition, common floating-point functions; such as,
`add, multiply and divide, are hardwired for faster exe-
`cution.
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`Data Bus
`Enhanced 64-Bit
`The data bus is the highway that carries information
`between the processor and the memory subsystem. Be-
`cause ofits external 64-bit data bus, the Pentium proc-
`essor can transfer data to and from memory at rates up
`to 528 Mbytes/second, a more than five-fold increase
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`over the peak transfer rate of the 66 MHz Intel DX2™
`microprocessor (105 Mbytes/second). This wider data
`busfacilitates high-speed processing by maintaining the
`flow of instructions and data to the processor’s supers-
`calar execution ‘unit.
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`Jn addition to having a wider data bus, the Pentium
`processor implements bus cycle pipelining to increase
`bus bandwidth. Bus cycle pipelining allows a second
`cycle to start before the first one is completed. This
`gives the memory subsystem more time to decode the
`address, which allows slower and less-expensive memo-
`ry components to be used, resulting in a lower overall
`system cost. Burst reads and writes, parity on address
`and data, and a simple cycle identification all contrib-
`ute to providing greater bandwidth and improved sys-
`tem reliability.
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`The Pentium processor also has two. write buffers, one
`corresponding to each pipeline,
`to enhance the per-
`formance of consccutive writes to memory. Write buff-
`ers improve performance byallowing the processor to
`proceed with the next pair of instructions, even though
`one of the current instructions needsto write to memo-
`ry while the bus is busy.
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`Data integrity and Error Detection
`Features
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`Protecting important data and ensuringits integrity has
`becomeincreasingly important as mission-critical appli-
`cations continue to proliferate. To ensure the Pentium
`processors’ reliability, Intel ran millions of simulations
`and tests. In addition, designers have added significant
`data integrity and error detection capability. Data pari-
`ty checking is supported on byte-by-byte basis. Address
`parity checking, and internal parity checking features
`have been added along with a new exception, the ma-
`chine check exception.
`
`Internal error detection places parity bits on the inter-
`nal code and data caches, translation look aside buffers,
`microcode, and branch target buffer. This feature helps
`to detect errors in a mannerthat remains transparent Lo
`both the user and the system.
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`Furthermore, the Pentium processors have implement-
`ed functional redundancy checking to provide maxi-
`mumerror detection of the processor and theinterface
`to the processor. When functional redundancy check-
`ing is used, two Pentium processors act as “master”
`and “checker” respectively. The “checker” is used to
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`Ex. 1017 / Page 5 of 5
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`Petitioners HTC Corp. & HTC America,Inc. - Ex. 1017, p. 5
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`Ex. 1017 / Page 5 of 5
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`Petitioners HTC Corp. & HTC America, Inc. - Ex. 1017, p. 5
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