SOUD STATE1MEMORY
`
`Flash memory goes mainstream
`
`! Matured over the kJsf/ive
`years from a norel~v
`product. this storage dez ice
`ojf ers system designers
`a ll'ealtb of applkations
`
`F lash memory 1,; the fi111t
`
`ments of designs i:n ·whi.:b full hit-alwrubility
`is not needed or can be architeccurally
`worked around.
`A fla>h m~.rr.ory cdl contains c1nly ouc
`t ransisroc This <iimplif1ed arch ii tcture
`results in signiftcant density ad,·antage.~
`over both .EEPROM and s talk random(cid:173)
`access memory CSR.."''\'O. Flash memory can
`even be as dense as ROM and dyn~mic
`RAM lDRAM) for eqairalent rnanuf.a<:turing
`proce$$ titliographies {Fi.g. l].
`signifK:antly new solid- 1
`st.ate memory te<:hnology I
`E\•ery top se:wlc-011ductor ma 1rufa~':turer
`to appear in ove! a d~- I
`of erasable and pr ogrammnble ROM!I
`ade. Its nonvolatilit)'. misy I
`(EJ'RO,,..ls) and DRA.);1~ is tod~y dtm~loping;
`updateahility, :md high i
`a flash memory iechJ1ologr. Two tn.md~
`density can l.'nhancc ex: i
`explain wily. First, s:ingle-uan~istor flash
`isting applications and '
`memorv will eventuallv \XiSt less to make
`than DRAM because of its ;Umpler cdl <II'
`make new ones ~wle. Although still a rel(cid:173)
`atively new approach, Oa~h memory i~
`chitecture ffiash nee;cis no uaich capacitor).
`al!eady in its second generation. These
`Second. there are oo fundallll"J\t11l 1t'Ch!1il;al
`de1.i.ces have been produced in volume for
`limi1.alio11$ that can keep fla.:1h fmm re·
`only the last fr.-e years, but are now moving
`placing ROM and RAM used fCK" t:Xl."CUtion·
`from n<l\-elty staOJS into !he mainstream.
`rode and data i;torage. Of coorsc, where tulJ
`bit-alterability is requir<>d. RAM tech(cid:173)
`Flash mernD!')' chips are ai;'3ilabk> in den(cid:173)
`nologies wi!I continue to be aS<.>d. As the
`sities up to IBM bits ii;'il.h random access
`time$ of 60 ns. Combined with complete!
`demand for flash memories inc·1eao;e>, <'Oh't$
`will come down. Now priced at lJS S-10-S6tl
`nonvolatility, this capacity make.<s tht: chi.PS a
`per 1111:gabyte, a chip could 5(>11 [CJr <Jill)'
`I $7.2~ per megabyte by th~ n 1icJ.l~l!)()i:~ <K·-
`1 cording to Oataquest tnc. ~an )c1St•, CA
`1 Ther<- are three distinct :flash i1.rchi·
`I Lectures-NOR. ET:::PROM-bast~d. and
`I NAND .EEPROM-based. All share tb.e
`I prima:y cbaracrerista"'S of nom"<JlaUhly and
`I updateability. but differ in ruch !lh."Ondary
`I char:tcteristics as block sire (the number of
`I cells that are erdSed al one tttnc>. access
`
`I pot€:n tia1 fit Jn applications t.1lac mi1t1l:1t ot.h(cid:173)
`erwise have used ROM. ek.'Clri<-'ally e1"a:;.:1bl\!
`i and programmable ROM mEPROMl. bat·
`tery-barkeod RAM, or magnetic mass
`storage [Table ll. Flash memory is also in·
`b)'l'tem Ul)Clateable: it can be era.~ a block
`at a time and is progranunable a bit at a
`time. Tbi.~ enables it to meet the require-
`Brian D1peit and Loo 11ehe't
`int.;! Corp
`
`E.PROM cell
`
`Intel Etox flash-memory cell
`
`41~r,
`
`Triple-poly EEPROM cell
`ORAM cell
`fl l 1'1ie cells ttsea i1t tli;r different prol{famma/Jle mew,ry ,irchitfcturt'J art' 1iariat1oii:; rm "
`tlrem~: t/11, JlPROiV and ETOX flash cells 1we 11ery tU.ike. but l:PROM's xalt o.mle~ ore
`thicker. EEPRWvfs usl! a third gal<" for ~rasiiig. Tlw DRAM uli, ffi1u.•rwr, is tilr 011/y v11latile
`cell shown.. II has no Jh:rting gate and stores d~1tii as tlu:rge cm 1111• trrnch 'aprtl'1J11r.
`
`time. and densil.) fTabk 2]. The NOR arch~·
`tectu.re is simplest, but i1. re-quirl'!l .1 duai
`pow<.'f supply mtd its larKt: blritk ~ize creates
`challen~'t'> for hard~rive 4:'mulat1on. Th<:
`EEPROM flash device has a smaU block size
`of 64 byies and a &.nitle txternal pow·;:r
`supply, features whooe oompleX!t)' makes
`for a more crpens.ive pnxluct. The NA..~D
`~EPROM flash archite<:ture hall an inter(cid:173)
`medfate block sire "' IK byl<'$< and includes
`eHw d<.>tection and corrertion <.Ef>AC> cir·
`.,·uitry {see "Filing in a flaslt." p. 531.
`HOW IT WORKS. When a nae,h m~·mory 1s
`read. address i1ipurn scle<:t <>PE:cific rnm(cid:173)
`sistors within the multikili)bi! (lr mlJl.ti ..
`megabii device arra~: In Intel Corp.'s ETOX
`teclmology, wtti.:h t~mploys th<~ !':OR arcbi·
`te-.'"ture, the decoded addre?ss .:enernks
`:rupplr-voitag4:' li-vel.s on Uw CMOS [i.J.d(cid:173)
`effeC't transistor sclC'<'L ~Le: ;ind dram. whi . .:
`ihe source~ grounded !Fig. 2, lt>Jtl.
`In an erased 0::ll. th<> ~le.:t-g.lte voltage
`is sufficient to overoomc the tnu1sbt.or nirn(cid:173)
`on threshold vol'..age (\'T), and the drain-to(cid:173)
`;;ourcc nirrem is d.."tecte<I b\' thl:! ~nse·arn·
`plliier citciliuy a~ m1rulntcd in:o " I. Ii; •
`l)mgriimrned ..:ell h<>V?l..'V(·t:, addcd d~trnns
`stnred cm the Elo:uini.: 1~1.e ra~.l: tJ~ tmn·
`sistt.1r's Yr s;:l ~h<1t appllr"<'I volt<1ge M tlw
`select gate i$ 1wt $Uffincmt t() turn ii. nn.
`The absen~ o.f c·ur~1t resull~ in ;1 () iil lh<(cid:173)
`corr~ding flasb memory outµut.
`To program a cell. UlE! Intel ETOX iJas.11
`memory tedl.Wg}: like EPROM. applies 12
`V bctwe<m ::<)'Jf'CI' i1nd select gate- {capaci(cid:173)
`rii'e!y coupkd t() too floating P,illd lU1d ~ir
`pr<Jl!imately 6 V betwe<:n Sllllrc.- and drain
`[Fi!!. 2, cemerl. The soun;c-drain ~oltagc·
`generate;; hot electrons that are S\<'ept
`across tbe cbannel from ~(lilrl:C to drain.
`Colliding with atcm1s "Ion~ tlw way, tliese
`hot elect ron~ r;tc<ll r 1!V•·: 11 nwre fr<Je
`eb.:mm,,;. Th4" hii.th Yo!I :i~i•: ;m the sd~(;t
`gat<~ ove.rcomes tl1t~ ox:idt~ rn<•1·izy barrier,
`and attracts the d~·trons al'J'Oss the thill
`h•''CI' oxide. \>tiler<: lh~ <ICt.:Unl\lL"ltt: 01'1 tl~
`floating gate. Wtli.>n enough han: 3t.:<,"llllm(cid:173)
`k1ted. the re1I switche>; from rt~ 1 <.erased) tv
`its Q {progrnmm<.>d) ~ta!<.>. This progr.1!11·
`ming i.&'11nique, calk-tl channel hoh:b.'lrN1
`inj~tioo, i> alsi.> tN?<1 tor EPROM cdl.s.
`Otlit!! flash mc-mory ;1pproath!.~ p.rOJi:l':l..'li
`brusing tum1eliog from the ~ubt-irate to I.lit:
`floating ga:te and higher i.ntmial \'ult;ig..':11 uf
`up to 25 V. The t.radc"Off for the fast~r cell
`pr(lgram spe.,><l th:1t rei;ults from th<> tligher
`V<•l!:agc i;i po;;;iihlc ~11 u.11reliiil>ility due· to
`@:ick brcakdO\,..'"fl,
`TIJ erasi: a ffash rnem1iry <'1~ll. ~kctr< •DS
`
`IPR2017-00430
`UNIFIED EX1024
`
`

`
`I
`
`GND
`I
`) Sooroe )
`
`+5 v
`Floating gate
`I
`c:: Drain
`\
`
`)
`
`~----- Approximately
`G-~N_D _ _::==F=loal~m=g=ga=t=e:::::__~·6_v
`Drain
`
`Substrate
`Substra1e
`Prog.ram, hot electron injection
`RHd
`/21 The ETOX cells are read, programmed, I erase of multiple flash memories and then
`and erased by applying appropriau voltages I <among other high-priority tasks) read from
`I or write to other devices as foreground Oi>"
`to the seuct gale, source and draitL
`l erations. Completion of this automated
`are removed from the noating gate, re- I erase, signified by a ready transition on the
`threshold behavior. Subsequent reads from I system processor via its interrupt input.
`turning the transistor to its normal VT Ready/Busy(RY/BYll)outpUt, interrupts the
`
`the ceU again output a l First-generation
`Preconditioning, or preprogramming, a
`block to Os before erasing puts an equal
`nash memories were erased in bulk like
`amount of electron charge on the floating
`EPROMs; an erase operation removed the
`gate of each cell in the block before aU are
`charge from aU transistors in the memory
`erased in parallel. This technique ensures
`array at the same time. Now nash mem-
`ories erase in smaller blocks, making them uniform and dependable erasure, resulting
`in equivalent threshold voltages for aU tran(cid:173)
`more suitable for both code- and file-storage
`appLications.
`sistors in the erased array or block, and is
`Intel's ETOX nash memory technology
`essential to reliable device operation as the
`erases by using Fowler-Nordheim tunneling. memory is cycled. Many second-generation
`Floating the drain, grounding the select NOR flash memories automatically precon(cid:173)
`gate, and applying 12 V to the source
`dition before erasure.
`creates an electric field across the thin
`Other flash memory approaches reverse(cid:173)
`oxide between the noating gate and the bias the same substrate/floating-gate
`source and pulls electrons off the floating
`junction used for programming, or use a
`gate (Fig. 2, right!. (Negative-gate-erase I separate float.ing-gate/erase-gate junction
`flash memories. such as those made by 1 and apply much higher voltages to speed
`Advanced Micro Devices Inc., Sunnyvale, j erase time (resulting in higher electric
`CA. create essentially the same electric field
`fields). The consequence of this tradeoff is
`by using voltages of ... 5 V and - 10.5 V on II potential oxide breakdown, especially if the
`the source and select gate, respectively.)
`cell is repeatedly cycled.
`The low 12-V differential results in rela- HAI. OR SINllE stffl.Y Wit.TUE. The physics
`of program and erasure for aU flash memory
`lively slow erase times. Intel based in Santa
`Clara, CA, provides hardware features such
`technologies requires the presence of elec(cid:173)
`as erase automation to hide the slow erase
`tric fields to move electrons on or off the
`time and minimize or eliminate the impact
`floating gate. This means that at the cell level.
`on the performance 'of systems with
`voltage potentials beyond those generated
`multiple arrays of nash memory. In such
`by the supply voltage alone are needed.
`designs, the system can initiate background
`Many of today's flash memories have two
`voltage inputs; V oc. the supply voltage, and a
`separate V PP• or program/erase voltage.
`which is externally generated. This dual(cid:173)
`voltage approach both simplifies the flash
`memory design and maximizes manufac(cid:173)
`turing yield. External V PP generation also
`minimizes die size, keeping silicon costs
`down (see "Beyond cell size." p. 521. This ap(cid:173)
`proach is especially attractive in multichip
`flash memory arrays because the additional
`cost of high-voltage generation is borne by
`the external voltage conversion circuitry
`alone, rather than by each flash memory
`chip. If an external V "' voltage does not
`already exist in the system for other
`purposes, up- and down-converters are
`readily available from several vendors in a
`variety of configurations .
`Single-supply nash memories that in(cid:173)
`tegrate high-voltage conversion circuitry di(cid:173)
`rectly on the silicon die are also beginning
`to appear. These products are especially at(cid:173)
`tractive in minimal-chip applications
`because eliminating the external V,,. voltage
`generation circuitry simplifies system
`
`1
`
`Defining lerms
`..- lllr. the number of cells that are erased at
`the same time.
`C-.: the process of programming and erasing
`a flash memory cell.
`rm.: to change a flash memory cell-value from a
`Oto a 1.
`Rllll 111 .,.._:a software utility that transforms
`standard file system read and write commands into
`functions compatible with llash memory features
`and capabilities.
`Flllll ....,: a nonvolatile, in-system-up(cid:173)
`dateable, high-density memory technology that is
`per-bit programmable and per-block or per-chip
`erasable.
`....- 3'1118'11'.3 memory whose contents
`can be easily modified by the system processor.
`
`*'' ' 1•: a memory whose stored data or rode
`
`is retained when power is removed from the
`memoiy cells.
`~ to change a flash rremory cell value from
`a1toa0.
`
`+~112~v _ _Jtit:~F=ioa='='n=g=ga=1=e;::::___~
`Drain
`
`Substrate
`Erase, Fowler-Nordheim tunneling
`design. Today such chips are available in
`volume in densities up to 12.BK bytes. The
`lower densities and the slower program/
`erase performance limit their widespread
`acceptance. The breadth of product offer(cid:173)
`ings is constrained by design complexity,
`larger die si.ze. and lower manufacturing
`yield. However. as these problems are
`solved, more and more single-voltage offer(cid:173)
`ings will emerge.
`FLAlll llUIORY CYCLINB. The number of
`possible program/erase cycles is probably
`the least understood specification related to
`flash memory. Depending on technology, cell
`architecture, process lithography. and pro(cid:173)
`gram/erase voltage, the impact on cells of
`extended cycling can be minimal (resulting
`in slower performance) or catastrophic (re(cid:173)
`sulting in permanent bit failure).
`As electrons repeatedly travel through
`the thin oxide during recurrent program(cid:173)
`ming and erasing, some of them becollle
`trapped in the oxide and do not reach their
`intended destinat ions. These trapped
`electrons affect electron mobility and
`impede further electron flow through the
`oxide, slowing program and erase times as
`cycling increases. This is considered to be a
`nondestructive impact since no actual cell
`damage results.
`In a relatively low program/erase voltage
`approach like Intel's ETOX. longer program
`and erase time is the main effect of cycling.
`A JOO 000-cycle specification. for example,
`means thar cell program and erase times
`through 100 000 cycles will be no longer
`than those specified in the data sheets.
`Beyond these cycling limits. the flash
`memory cells may take longer to program
`and erase but will still operate normally.
`Alternative EEPROM-based approaches
`achieve faster erase times by generating
`much higher voltages on the chip. However,
`the resulting electric fields can literally tear
`apart the thin oxide at silicon defect areas
`and induce a short circuit between Ooating
`gate and substrate. irrepa rably damaging
`the cell. Cell redundancy (two transistors
`per cell) and on-chip EDAC circuitry are
`two common approaches to overcoming this
`inherent limitation or EEPROM-based flash
`memories. The ver}' high electric fields and
`substantial current now stress not only the
`transistors in the memory array but also the
`peripheral circuitry on the chip.
`In evaluating different flash memories.
`the first step should be to realistically de(cid:173)
`termine how much cycling the specific aJ>"
`plication requires. and to identify what
`changes in software or hardware architet.~
`ture can be made to minimize this cycling.
`
`4!J
`
`

`
`Memory alternatives
`Insight into what flash memory is (and what ii is not) may be obtained most
`easily by considering its more established memory alternatives: read-only
`memory (ROM), random access memory (RAM). electrically erasable pro(cid:173)
`grammable read-only memory (EEPROM). and magnetic mass storage.
`Outlining flash memory characteristics in these terms allows its features, ca(cid:173)
`pabilities. and applications lo be more quickly grasped and assessed.
`lllM. This memory family is nonvolatile bul not in-system updateable. The
`family members ROM. PROM. and EPROM are distinguished by varying
`degrees of flexibility. ROM memories are used 10 store permanent code and
`data that are required to initialize and operate a system, and that must be ac(cid:173)
`cessible at relatively high speed (differentiating them from magnetic disk
`drives. for example). Most ROM technologies employ a single transistor or
`fusible link per cell and are therefore capable of high memory densities.
`1111. This family of in-system updateable and fully bit-alterable memories is
`easily rewritten by the system's central processing unit (CPU). However, RAM
`does not retain its stored values when power is removed. RAM is used to
`store temporary data and is also used to shadow the contents ol both ROM
`memory and magnetic mass storage during normal system operation. for
`high-speed access. Battery-backed static RAMs integrate a battery to retain
`stored data when system power is removed. These batteries are, of course.
`ultimately volatile and are also sensitive to le~ature variations.
`Each dynamic RAM cell consists of a transistor and a capacitor that must
`be refreshed or occasionally rewritten because of leakage, in order to retain
`stored contents. DRAM today is the technology that drives new manufacturing
`processes for many semiconductor companies.
`Static RAM (SAAM) requires no periodic refresh and has faster access
`
`lime, but at the price of density and cost SRAMs typically use between four
`and six transistors per cell. affecting attainable device density and signifi(cid:173)
`cantly increasing memory cost at a given density relative to DRAM.
`EEPl9. This device is in-system writeable on a byte-by-byte basis, like
`RAM, but it is also nonvolatile, like ROM. Write operations to an EEPROM
`cell store or remove electrons from areas of the cell transistor, resulting in a
`O or 1. respectively, when the cell is subsequently read.
`Since EEPROM is per-byte alterable. cell erase is part of rewrite. To speed
`this process, high internal voltage potentials (and subsequent high electric
`fields) are generated. This has the potentially unhappy consequence of com(cid:173)
`promising cell reliability over time by causing cell oxide to break down as the
`transistor is repeatedly rewritten. EEPROM vendors often strive to extend
`memory flfetime by means ol on-chip cell redundancy and error detection and
`correction logic. This added cell complexity, along with on-chip high-voltage
`generation and considerable peripheral logic, limits EEPROM density and in(cid:173)
`creases cost per megabyte ~red to other types of memory storage.
`lllmllC 11111 lllUll. The resident hard-disk drive and removable
`floppy-disk drive are extremely dense. inexpensive on a cost-per-megabyte
`basis {compared to semiconductor memory), nonvolatile and in-system up(cid:173)
`daleable. However. the relatively slow acaiss time, caused by platter seek and
`rotation delay, makes direct-read of code and data unrealistic. Instead, non(cid:173)
`volatile magnetic mass storage contents are copied to faster (but volatile)
`RAM for CPU access. The fact that hard-disk and floppy-<lisk drives contain
`moving parts (the motor and heads) also suggests that they are potentially
`less rugged and consume more powe< than solid-state storage alternatives.
`-8.0. and L.H.
`
`Fur example, with a file system optimized i voltage (Vo:;l tolerances. All this makes an 1 Algorithms tend to vary from vendor to
`installed EPROM difficult to program (driv- I vendor, although some standardization has
`for flash memory, 100 000 cycles can trans-
`late into almost 3900 years of operation for
`ing the successful PROM programming in-
`occurred. Second-generation algorithms are
`dustry); and it must still be removed for '1 more automated, simpler, and less system-
`a 10-Mbyte flash memory array, assuming a
`intensive than their first-generation coun-
`5K-byte frle written every 10 minutes.
`erasure with ultraviolet light.
`Flash memory's integrated circuitry sim- ! terparts. For example, first-generation flash
`A flash memory's published minimum
`and typical cycling specifications are only
`plifies the hardware and software interface, · memories required that preprogramrning
`part of the picture. Equally important is the making in-system update feasible. Internal
`be done by system software before erase.
`logic is controlled by command sequences Second-generation devices automatically
`expected flash memory failure rate and/or
`mean time between failures (found in reli· written to on·dlip registers at SRAM-like
`execute the preprogranuning step after an
`erase command sequence is received.
`· ability reports), and the usage model
`speeds. The flash memory translates these
`llOCllNI. One of the key innovations of
`. assumed in the failures-in-time calculation.
`commands and generates internal pro·
`1 IATA RELIABILITY. The length of time that
`flash memory architecture is blocking, or di-
`gram/erase pulses. All required internal
`stored information remains intact once a
`voltages are similarly generated from the
`viding the flash memory into individually
`erasable segments. This allows for the par(cid:173)
`flash memory cell is programmed or erased
`normal supply voltage and the program/
`erase voltage Gf it exists).
`(asswning all operating specifications are
`titioning of a flash memory chip or an array
`followed) is a function of the specific prod-
`uct, manufacturing process. operating volt- 1. Memory leatures
`age, program/erase voltage, temperature,
`and other variables. A sufficient and sus·
`tainable data reliability rating is an essential
`part of qualifying a new process, component,
`or subsystem for production. In-line testing
`of each flash memory screens out those
`with poor reliability before shipment.
`Margining, a technique whereby cell
`program/erase is verified at voltages higher
`than those undergone by the cell during
`later reads, serves to ensure data reliability.
`First used for EPROMs, it is an inherent
`part of the program and erase algorithms
`for many new nash memories.
`PRHRAMIERASE ALHlllTHMS. When an
`EPROM is programmed, addresses and data
`are supplied and held and an input pin
`(PGM#) is driven tow for tens or hundreds
`I of microseconds. Multiple external voltages
`I are applied to the memory at different steps
`
`H•ql
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`memory
`Static
`RAM
`Dynamic
`RAM
`EE PROM
`PROM/
`EPROM
`ROM
`Hard-
`disk
`drive
`Aoppy·
`disk
`drive
`in the algorithm, and these voltages cause
`outputs to drive above normal supply- EE PROM • •leetric•lly erasab~e and proorammal>le ROM; EPROM . e1ee1neal1Y programmable ROM; PROM • on .. 1im•;noorammac1e ROM.
`
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`50
`
`IEEE SPECTRUM OCTOBER 1993
`
`

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`No of
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`NANO
`
`16M (plus
`EDAC)
`1M
`
`38 bits
`
`38 bits
`
`151o15
`
`120ns
`
`300µsper
`byte
`150 µs per
`byte
`
`100000
`
`10000
`
`of flash memory chips for differen t uses. 2. flash memory technologies compared
`Intel's Boot Block flash memory product
`line, for example, employs asymmetrical
`blocking, in which one device is composed of
`large main blocks for the majority of code
`storage, very smaU blocks for parameter
`r
`storage and/or backup, and a small hard(cid:173)
`metlical}
`ware-lockable boot block for the system's
`4K (asym-
`kernel start-up code. This chip is becoming
`metrlcaQ
`i popular in PC built-in operating systems
`4K (sym-
`(BIOS) and in other dedicated applications
`metrical)
`where the system cannot afford to lose ini(cid:173)
`tialization capability.
`EEPROM-
`64 (sym-
`Symmetrical blocking is useful in mass
`based
`metrical)
`storage applications, where erase blocks of EDAC , error dalec!ion and corroclion: EEPROM . e1ec1rically erasable and programmab4e ROM
`equal size emulate the sector and cluster
`arrangement of a disk drive. This architec(cid:173)
`ture is used in Intel's FlashFile components
`and in offerings from other flash memory
`manufacturers.
`Larger flash memory chips (lM byte or
`more) aUow for storage and easy revision of
`ROM-based operating systems and appli(cid:173)
`cations. Systems manufacturers are moving
`from traditional ROM to flash memory to
`facilitate updating or enhancement of op-
`erating systems and to provide users with [3] Flash memory's nonvolatility and updateability displace the combination of dynamic RAM
`longer product life and added functionality. aiut hard disk drive used for cede storage, creating a new memory architecture.
`Possibly the most important frontier for
`products around the basic NOR architec- ' look-up tables, capture and recording of im-
`i flash memory is mass storage. Flash mem-
`ture. A joint project between Intel and Con- 1, portant data, such updateable firmware as
`1 ory technology in 0.8-m m lithography has
`nor Peripherals Inc., San Jose, CA, has re- I BIOS, and the more sophisticated disk(cid:173)
`I achieved the density and cost structure to
`! be used as data-file and application-program
`suited in the successful demonstration of a
`drive-like solid-state memory subsystems
`2.5-inch form-factor, integrated-drive- 1 that have attained sizes up to 200 megabytes.
`· storage in smaU form-factor mobile PCs and
`communication devices [Table 31.
`electronics- compatible NOR-based flash l
`Firmware updates were not practical
`THIEE APPRUCllES. The ETOX flash mem-
`hard drive.
`'I with ROM or EPROM, because the system
`Whereas the NOR architecture adds
`had to be taken apart to replace individual
`ory, which stands for EPROM tunnel oxide,
`was first introduced by Intel in 1988. ETOX- , functionality to EPROM designs. EEPROM-
`components. Flash memory allows for in(cid:173)
`like or EPROM-based flash memory is also ·1 based flash vendors have redesigned their ' system code revisions and updateable look(cid:173)
`known as the NOR architecture, because of
`products to simplify peripheral logic and
`up tables, minimizing the costs and risks as(cid:173)
`the way the cells are interconnected in- j minimize die size (and cost), resulting in
`sociated with field failures and permitting
`ternaUy. NOR flash memories add function-
`, per-block erase (instead of the per-byte
`future code enhancements. Some systems
`ality to basic EPROM designs by thinning
`erase used in EEPROMs). EEPROM-based ! manufacturers have integrated this capa(cid:173)
`the oxide, permitting both electrical pro- ; flash memories are available from several i bility into their business models. highlighting
`gramming and electrical erase. The ETOX [ vendors in densities up to 128K bytes, with I update flexibility to help differentiate their
`flash memory gate oxide, for example. is ap- I 512K-byte components currently sampling. products from those of their competitors.
`proximately 10 nm thick. whereas that of the
`In addition. most of these products are
`Another application, data acquisition,
`' single-supply voltage memories, a key . takes full advantage of flash memory's byte-
`EPROM cell is approximately 30 nm.
`benefit. EEPROM-based flash memories ' write capability and full nonvolatility. Any 1
`Apart from thinner oxide and a deeper
`source junction, ETOX flash memory cells
`also offer very-fine-granularity blocking (64
`kind of data logger or sensor that depends
`on some fonn of battery-backed RAM can
`are almost identical to EPROM cells. As a
`bytes), reflecting their EEPROM heritage.
`result, they can take advantage of the
`NAND EEPROM-based flash was pio-
`benefit from using nash memory. Flash
`neered by Toshiba Corp. and replaces the memory offers cost savings. higher density,
`EPROM manufacturing knowledge base
`and linear cell scalability with decreasing
`company's original triple-poly EEPROM ap- ' and critical data security by eliminating the
`lithographic feature sizes. Recent advances
`proach announced in 1985. In the NAND ar-
`battery for retaining memory contents.
`chitecture, ceUs are seriaUy interconnected NEW AICHntmllES. Mobile PC and com(cid:173)
`include per-block erasability and fully au-
`tornated program and erase on chip. Single-
`in the memory array. The approach is in- munications manufacturers are discovering
`voltage NOR flash memories, which
`tended specifically for silicon-based mass
`new ways to exploit flash memory's capa(cid:173)
`generate all high voltages for program/ : storage emulation, with fine-granularity
`bilities in their system designs. Placing ap(cid:173)
`blocking and access time that reflects disk-
`erase with on-chip regulator circuitry, are
`plications on the mother board in a resident
`also beginning to appear.
`drive roots. NAND EEPROM-based flash
`flash array configuration, directly connected
`NOR flash memories are available today memories program only on a per-page basis
`to the processor, dramatically speeds up sys(cid:173)
`using an on-chip buffer. [See "Filing in a
`tern performance. Frequently used software
`as components in densities from 32K bytes
`f becomes immediately available, eliminating
`~ up to IM byte, and as PCMCJA <Personal
`flash," p. 53.l
`l IARlm I f USES. It is difficult to point to
`' Computer Memory Card International
`the lengthy download step required by
`Association) memory cards, in densities up
`one characteristic that describes flash mem- RAM/disk-based system architectures. A
`ory's attractiveness; in fact, it is the com-
`to 20 me gabytes . Multiple sourcing is
`resident flash disk, acting as a nonvolatile
`available on some products, and the ma-
`bined features and benefits of these chips RAM drive, emulates disk drive functionality
`that make flash memory a fit in so many ap- ! with no spin-up time or seek/rotation delay.
`jority of memory companies not yet pro-
`l ducing flash memory are developing their
`plications. These include in-field updateable Finally, in systems designed with advanced
`
`CPU
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`ceu •• .., •• , .._..ng .,...., o-. .... , ., .... e RAM.
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`3. Flash memory evoJuUon and ns cmequences
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`hal1cements ttvouoh code update; gaw man-
`utacturers ftexible inventory control
`Enabled memoiy cards; was updatable
`120ns ~ HiQb-density
`sulface-mount
`wi1l1oot battery backup; protected boot codes;
`$200
`riiade PC BIOS updatable: enabled data
`paclc8ging; ailto
`~;chip IOgglng into nonvolatile memoiy; increased
`functionality in small systems
`SIC10ring
`Emulates highil8rformance disk; lengthens
`Symmetrical
`system batlel'y Ille; lowefs power COO·
`blocking; 3.l'V
`SUPPIY voltage:
`sumption; puts applicallon cache on moth·
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`greater"auto-
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`ibility and functionality of precise electro-
`
`flash memory technology and integrated
`
`Personal notebook and subnotebook com·
`power management, the contents of system 1 ness, removeability, small size, low power 1
`DRAM can be stored in resident flash I consumption, and high performance were
`puters with standard disk interfaces can also
`memory during system sleep mode for
`valued. For example, factory-floor equip· \ derive benefit from flash memory in a hard(cid:173)
`I use flash memory cards to increase the flex- I defined as a mass storage device based on
`longer battery life <DRAM refresh can be . ment, robots, and industrial control systems disk- drive configuration. A flash drive is
`disabled) and fast system wake-up.
`tecture is possible. Flash memory can I mechanical systems. But lower memory l with such industry-standard disk interfaces
`Using flash memory, a new system archi·
`replace system RAM in the latter's tradi· media prices and new packaging technology
`as integrated drive electronics <IDE), small
`tional role of direct-execute code storage, I have reduced costs and enhanced the · computer systems interface (SCSD, or
`completely plug-compatible with standa.rd l
`while some RAM is retained for data ma-
`density and functionality of flash memory PCMCINAT attachment. A flash drive is .
`nipulation and storage. This allows reduc-
`cards, making them attractive in main-
`tion of RAM content with no impact on the j stream pOrtabJe equipment and mobile corn·
`1.8-inch or 2.5-inch hard-disk drives. It
`total system's memory budget.
`, puters. Flash memory cards are now
`differs from the flash memory card in its '[
`feasible in data-file and application-program I system software and hardware
`For small form-factor systems, con-
`re-
`verting the application portion of system I storage or transfer.
`.
`quirements and in its relative cost.
`In mobile designs, the nonvolatility, up- . The widespread acceptance of flash ·
`· RAM to nonvolat ile memor y reduces :
`, overall system cost and size, since a disk I dateability, and removeability of the flash I memory solidifies its position among the
`: drive is no longer needed for nonvolatile ap- memory card suit it to file exchange be· mainstream silicon memory technologies.
`plication storage. The resident application 1· tween systems. Solid-state memory access · Flash memory's unique combination of high·
`can be upgraded by means of an interface
`speeds increase s