United States Patent
`Jeng
`
`[19]
`
`[54] LOW TEMPERATURE ANISOTROPIC
`ASHING OF RESIST FOR
`SEMICONDUCTOR FABRICATION
`
`[75]
`
`Inventor: Shin-pun Jeng, Plano, Tex.
`
`[73] Assignee: Texas Instruments Incorporated,
`Dallas, Tex.
`
`[21] Appl. No.: 242,922
`
`[22] Filed:
`
`May 16, 1994
`
`Int. Cl.6
`..................................................... HOlL 21/00
`[51]
`[52] U.S. Cl .......................................................... 156/659.11
`[58] Field of Search ..................................... 156/626, 627,
`156/643, 659.1, 661.1, 345
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,464,460
`5,312,717
`
`8/1984 Hiraoka et al. ......................... 156/643
`5/1994 Sachder et al .......................... 156/643
`
`FOREIGN PATENT DOCUMENTS
`
`394739 10/1990 European Pat. Off ..
`59-222929 12/1984
`Japan .
`60-262151 12/1985
`Japan .
`63-160227
`7/1988
`Japan .
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111
`US005453157A
`[11] Patent Number:
`[ 45] Date of Patent:
`
`5,453,157
`Sep. 26, 1995
`
`OTHER PUBLICATIONS
`
`"Electron Cyclotron Resonance Plasma Etching of Photo(cid:173)
`resist at Cryogenic Temperatures", J. Appl. Phys., vol. 72,
`No. 7, pp. 3050-3057; Oct.-1992-Varhue et al.
`
`Primary Examiner-R. Bruce Breneman
`Assistant Examiner-George A. Goudreau
`Attorney, Agent, or Firm-Kay Houston; James C. Kester(cid:173)
`son; Richard L. Donaldson
`
`[57]
`
`ABSTRACT
`
`This invention encompasses using anisotropic plasma at a
`low temperature to strip resist from a -semiconductor wafer.
`A semiconductor wafer 10 is placed in a reactor 26 which
`contains an oxygen plasma source 28. The oxygen plasma
`source 28 emits oxygen plasma 32 which is drawn towards
`the biased wafer 10, exposing the resist layer 22 of the wafer
`to anisotropic oxygen plasma. A sensor 30 detects when the
`ashing of the resist is complete, and then the plasma source
`is turned off.
`
`Advantages of the invention include the ability to remove
`resist from wafers without damaging polymeric dielectric
`layers, which are sensitive to the harsh effects of traditional
`resist removal methods. With the present invention, very
`little damage occurs to the material on the sidewalls of vias.
`
`4 Claims, 3 Drawing Sheets
`
`START
`
`BIAS WAFERS {e.g GROUND)
`
`PERFORM LOW-TEMPERATURE
`ANISOTROPIC PLASMA ASH
`
`NO
`
`END
`
` Ex.1015 p.1
`
`

`
`U.S. Patent
`
`Sep. 26, 1995
`
`Sheet 1of3
`
`5,453,157
`
`~10
`
`22
`20
`18
`16
`
`FIG. 1A
`(PRIOR ART)
`
`24 '
`
`14
`
`24 '
`
`FIG. 1B
`(PRIOR ART)
`
`~26
`
`+ + +
`+ + !r32
`+ + +
`+ +
`
`FIG. 2
`
` Ex.1015 p.2
`
`

`
`U.S. Patent
`
`Sep. 26, 1995
`
`Sheet 2 of 3
`
`5,453,157
`
`START
`
`BIAS WAFERS ( e.g GROUND)
`
`PERFORM LOW-TEMPERATURE
`ANISOTROPIC PLASMA ASH
`
`NO
`
`END
`FIG. 3
`
`24
`~
`
`.,110
`
`22
`20
`18
`16
`
`FIG. 4A
`
`Ex.1015 p.3
`
`

`
`U.S. Patent
`
`Sep. 26, 1995
`
`Sheet 3 of 3
`
`5,453,157
`
`24
`~
`
`H
`
`~10
`
`20
`18
`16
`
`FIG. 4B
`
`24 '
`
`,....__,.--.--...---.-.....--1
`l-"'--"----"--'.........,.__,.___,,.._-....1..~-:.........;:,_;:.._~
`
`22
`20
`18
`
`~10
`
`FIG. SA
`
`24
`~
`
`20
`18
`
`FIG. SB
`
` Ex.1015 p.4
`
`

`
`5,453,157
`
`1
`LOW TEMPERATURE ANISOTROPIC
`ASHING OF RESIST FOR
`SEMICONDUCTOR FABRICATION
`
`FIELD OF THE INVENTION
`
`This invention relates generally to the fabrication of
`semiconductor devices, and more specifically to resist strip
`processes.
`
`BACKGROUND OF THE INVENTION
`
`2
`and then the plasma source is turned off.
`One embodiment is a method for removing resist from a
`semiconductor wafer, including the steps of coating a sub(cid:173)
`strate with a polymeric dielectric layer, applying an inor-
`5 ganic layer over the polymeric dielectric layer, applying a
`resist layer over the inorganic layer, patterning the resist
`layer, etching the inorganic layer, and ashing the resist with
`an anisotropic oxygen plasma.
`Another embodiment is a system for removing resist from
`10 a semiconductor wafer, comprising a reactor, a wafer having
`a polymeric dielectric layer positioned within the reactor,
`and an oxygen plasma generator located inside the reactor.
`An advantage of the invention is the ability to remove
`15 resist from wafers with low-dielectric materials, which are
`sensitive to the harsh effects of traditional resist removal
`methods. The decomposition of low-dielectric constant
`materials, which may activate the oxidation reaction, is
`minimized by lowering the wafer (substrate) temperature.
`With the present invention, very little damage occurs to the
`material on the sidewall of the vias.
`
`Semiconductors are widely used in integrated circuits for
`electronic applications, including radios and televisions.
`Such integrated circuits typically use multiple transistors
`fabricated in single crystal silicon. Many integrated circuits
`now contain multiple levels of metallization for intercon(cid:173)
`nections. As geometries shrink and functional density
`increases, it becomes imperative to reduce the RC time
`constant within multi-level metallization systems.
`Although the dielectric typically used in the past to isolate 20
`metal lines from each other was silicon dioxide, recent
`trends have been towards using materials with low-dielectric
`constants in order to reduce the RC time constant. Many
`low-dielectric insulators are either pure polymers (e.g.
`parylene, BCB, tefion, polyimide) or organic spin-on glass 25
`(OSOG, e.g. silsequioxane and siloxane glass). The oxida(cid:173)
`tion resistance of these low-dielectric materials is generally
`poorer than the oxidation resistance of silicon dioxide.
`Conventional ash processes are available for high-aspect-
`ratio contacts and vias; however, such processes are dam-
`aging to dielectric materials, especially low-dielectric mate(cid:173)
`rials. Oxygen plasma (ash) is commonly used to remove
`photoresist from wafer surfaces. The conventional ash pro(cid:173)
`cess is performed in barrel and down-stream reactors, and is
`carried out at a high temperature (approximately 250° C.) for
`a long period of time to assure that all photoresist is
`completely cleared. Unfortunately, high temperature ash
`processes not only clear photoresist from the surface of the
`wafer, but also remove polymer contents from low-dielectric
`materials, resulting in problems such as shrinking, cracking,
`moisture absorption, via poisoning, undercutting, and gen(cid:173)
`eral degradation of the dielectric property of low-dielectric
`materials. Via integration has presented a problem in the use
`of low-dielectric materials.
`Thus, the use of low-dielectric constant materials in the
`semiconductor industry has resulted in the need for an ash
`process that does not damage polymeric dielectric materials
`while removing the photoresist.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`In the drawings, which form an integral part of the
`specification and are to be read in conjunction therewith, and
`in which like numerals and symbols are employed to des(cid:173)
`ignate similar components in various views unless otherwise
`indicated:
`FIG. 1 is a prior art drawing showing the effects of a
`conventional ash process on a cross-sectional view of a
`semiconductor via;
`FIG. 2 shows a typical environment in which the present
`invention may be performed;
`FIG. 3 is a flow chart of the process steps of the invention;
`FIG. 4 is a cross-sectional view showing the effects of the
`present invention on a semiconductor via; and
`FIG. 5 is a cross-sectional view of an example of an
`alternate semiconductor circuit.
`
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`30
`
`35
`
`40
`
`SUMMARY OF THE INVENTION
`
`This invention encompasses using anisotropic plasma at a
`low temperature to strip resist from a semiconductor wafer.
`A semiconductor wafer is placed in reactor which contains
`an oxygen plasma source and an optional sensor. The
`oxygen plasma source emits oxygen plasma which is drawn
`towards the wafer by an electric field, exposing the surface
`of the wafer to anisotropic oxygen plasma. A sensor detects
`when the ashing of the photoresist of the wafer is complete,
`
`45
`
`The making and use of the presently preferred embodi(cid:173)
`ments are discussed below in detail. However, it should be
`appreciated that the present invention provides many appli(cid:173)
`cable inventive concepts which can be embodied in a wide
`variety of specific contexts. The specific embodiments dis-
`50 cussed are merely illustrative of specific ways to make and
`use the invention, and do not delimit the scope of the
`invention.
`The following is a description of several preferred
`embodiments and alternative embodiments,
`including
`55 manufacturing methods. Corresponding numerals and sym(cid:173)
`bols in the different figures refer to corresponding parts
`unless otherwise indicated. Table 1 below provides an
`overview of the elements of the embodiments and the
`drawings.
`
` Ex.1015 p.5
`
`

`
`5,453,157
`
`4
`
`3
`
`TABLE 1
`
`Preferred or
`Drawing Specific
`Element Examples
`
`Generic
`Term
`
`Other Alternate Examples
`or Descriptions
`
`10
`
`12
`
`Silicon
`
`Semiconductor
`wafer
`Substrate
`
`14
`
`Aluminum
`alloy
`
`Metal layer
`
`16
`18
`
`PETEOS
`Organic Spin-
`on Glass
`
`Oxide layer
`Polymeric
`dielectric layer
`
`20
`22
`
`24
`26
`28
`
`30
`32
`
`PETEOS
`Polymer
`
`Oxygen
`plasma source
`CO detector
`Oxygen
`Plasma
`
`Inorganic layer
`Photoresist
`layer
`Via
`Reactor
`Plasma source
`
`Sensor
`Plasma
`
`May include other metal interconnect
`layers or other semiconductor elements,
`(e.g. transistors, diodes);
`Compound semiconductors (e.g. GaAs,
`InP, Si/Ge, SiC) may be used in place of
`Si.
`Titanium with an Aluminum bilayer
`(TiN/Al/TiN);
`Alloys of Al, Cu, Mo, W, Ti;
`Polysilicon, silicides, nitrides, carbides;
`AlCu alloy with Ti or TiN underlayers;
`Metal interconnect layer.
`Si02 ; Silicon nitride.
`Other polymers such as parylene, BCB,
`teflon, polyarnide;
`Organic spin-on glass (OSOG) such as
`silsequioxane and siloxane glass;
`Other polymer-containing dielectric
`materials.
`Oxide; Si02 ; Si0,!Si3N4 bilayer.
`Resist layer; other polymers; other light-
`sensitive materials.
`Ashable layer on a semiconductor wafer
`
`C02 detector
`
`FIG. 1 is a prior art drawing of a conventional ash process,
`which has typically in the past been performed at approxi(cid:173)
`mately 250° C. FIG. la shows a cross-section of a via 24 of
`semiconductor wafer 10 before a conventional ash process.
`The wafer 10 has a substrate 12 which may, for example,
`contain transistors, diodes, and other semiconductor ele(cid:173)
`ments (not shown) as are well known in the art. The
`substrate 12 may also contain other metal interconnect
`layers. Metal interconnect layer 14 has been deposited over
`the substrate 12. Metal interconnect layer 14 may comprise,
`for example, aluminum or a titanium-tungsten/aluminum
`bilayer. Oxide layer 16 has been deposited over metal layer
`14 and may be made of PETEOS (plasma-enhanced tetra(cid:173)
`ethoxysilane). Polymeric dielectric layer 18 has been depos(cid:173)
`ited over the oxide layer 16 and may comprise, for example,
`an organic polymer or organic spin-on glass (OSOG). The
`organic spin-on glass contains a mixture of organic-silicon
`and oxygen-silicon bondings. Inorganic layer 20 has been
`deposited over polymeric dielectric layer 18. Inorganic layer
`20 is an oxide, preferably Si02 and in this example,
`PETEOS. Photoresist layer 22 has been deposited over
`inorganic layer 20, which may be made of a light-sensitive
`polymer. Subsequent processing steps have been performed,
`leaving via 24 in the semiconductor wafer 10. The via 24 has
`typically been formed through the photoresist layer 22,
`inorganic layer 20, polymeric dielectric layer 18, and oxide
`layer 16. The top surface of metal layer 14 usually forms the
`bottom of the via 24.
`An ash process is performed on wafer 10 to remove the
`photoresist layer 22. FIG. lb shows the via profile after the
`conventional ash process, with damage to the polymeric 65
`dielectric layer 18 along the walls of the via 24.
`A typical environment in which the present invention may
`
`be performed is shown in FIG. 2. Semiconductor wafer rn
`35 containing a polymeric dielectric layer is placed in reactor
`26 which contains an oxygen plasma source 28 and a sensor
`30. The polymeric dielectric layer contains a percentage of
`polymer by weight sufficient to improve the dielectric con(cid:173)
`stant of Si02 . The polymeric dielectric layer generally
`40 contains at least 5% (and preferably between 10% and 50%)
`of organic polymer by weight. The wafer 10 is biased
`negatively with regard to the oxygen plasma source 28, for
`example, by connecting the wafer to ground, to direct
`positive ions towards the wafer. The ashing process of the
`45 present invention is generally performed at low temperature,
`between approximately -40° C. and 20° C., which is
`achieved, for example, by the use of liquid nitrogen. The
`positively-charged oxygen plasma source 28 emits oxygen
`plasma which is drawn towards wafer 10 by the electric
`50 field, exposing the surface of the wafer 10 to anisotropic
`oxygen plasma 32. The sensor 30 detects when the ashing of
`the photoresist of the wafer 10 is complete, and then the
`plasma source 28 is turned off. The sensor 30 may be a CO
`55 or C02 detector; when the intensity of CO or C02 emission
`decreases, the system is signalled to shut off. The sensor 31li
`provides endpoint capability for the ashing system, prevent(cid:173)
`ing over-ashing of the wafer.
`The flow chart for the process is shown in FIG. 3. The
`60 wafer is biased to establish a direction for the plasma, and
`then the low-temperature anisotropic plasma ash is per(cid:173)
`formed. When the endpoint is detected (e.g., when the
`photoresist has been ashed), then the ashing ceases.
`The results of the new ashing process on a typical
`semiconductor wafer 10 is shown in FIG. 4. FIG. 4a shows
`a via profile of a semiconductor before the new ash process,
`the same as described for FIG. la. FIG. 4b shows the via 24
`
` Ex.1015 p.6
`
`

`
`5,453,157
`
`5
`after the ashing method of the present invention has been
`performed, with no damage to the polymeric dielectric layer
`18.
`The structure shown in FIGS. 1 and 4 may vary. FIG. 5
`shows an example of another semiconductor wafer 10 that 5
`could be ashed with the present invention. Other semicon(cid:173)
`ductor structures could benefit from the low-temperature
`resist strip process.
`After the ashing of the photoresist is complete, further
`processing steps are performed as required. For example, the 10
`via is typically filled with metal to form an interconnect
`between layers.
`Performing an ash at the low temperatures (-20° to 20) as
`required of this invention may result in increased time
`required to perform the ash, compared to conventional
`ashing techniques. The flux, or ion current, may be varied to
`alleviate this increase in time required. For example, if the
`flux is increased, less time will be required to perform the
`ash process.
`The novel method of using a low-temperature anisotropic
`ash with endpoints to strip resist can offer definite advan(cid:173)
`tages over the conventional processes. First, the anisotropic
`ions can bombard the planar surface containing the resist to
`be ashed, and simultaneously clean any residue off the 25
`surface of the metal. Because the ash is anisotropic, very
`little damage will occur to the polymeric dielectric material
`on the sidewall. The directionality of the moving oxygen
`species co+) limits the reactivity of the sidewall with the
`oxygen.
`Second, the endpoint capability can stop the ashing pro(cid:173)
`cess before any damage occurs in undesirable locations, in
`this case to the polymeric dielectric layer sidewall of the via.
`The use of a sensor to attain the endpoint capability is
`optional and gives the benefit of more control to the ash 35
`process.
`Third, the low temperature can reduce the reactivity
`between the polymer and the sidewall of the dielectric layer
`with the oxygen plasma. The low temperature slows the
`activity of the molecules, allowing a more controlled ash
`process.
`This invention is beneficial to other materials, particularly
`material sensitive to conventional ash processes. The inven(cid:173)
`tion is particularly useful for the ashing of semiconductor
`wafers using polymeric dielectric materials, because the 45
`damage caused to the polymeric dielectric materials by
`traditional methods of removing resist is undesirable and
`extensive, causing many problems in semiconductor manu(cid:173)
`facturing. The present invention, a low temperature resist
`
`15
`
`20
`
`6
`strip process, eliminates or minimizes such damage to the
`polymeric dielectric material. In addition, the ash process of
`the present invention may remove native oxide on the metal
`layer.
`While the invention has been described with reference to
`illustrative embodiments, this description is not intended to
`be construed in a limiting sense. Various modifications and
`combinations of the illustrative embodiments, as well as
`other embodiments of the invention, will be apparent to
`persons skilled in the art upon reference to the description.
`It is therefore intended that the appended claims encompass
`any such modifications or embodiments.
`What is claimed is:
`1. A method for removing resist from a semiconductor
`wafer having a substrate, including the steps of:
`depositing a metal layer over said substrate;
`coating said substrate with a polymeric layer;
`applying an inorganic layer over said polymeric layer;
`applying a resist layer over said inorganic layer;
`patterning said resist layer;
`etching said inorganic layer; and
`ashing said resist with an anisotropic oxygen plasma.
`2. A system for removing resist from a semiconductor
`wafer, comprising:
`a reactor;
`a wafer having a polymeric layer positioned within said
`reactor;
`an oxygen plasma source located inside said reactor;
`a wafer biasing apparatus to anisotropically direct ions
`from a plasma toward said wafer; and
`a sensor located inside said reactor to detect when resist
`has been removed.
`3. The system of claim 2 wherein said system is shut off
`when said sensor detects completion of resist removal.
`4. A system for removing resist from a semiconductor
`40 wafer, comprising:
`a reactor;
`a wafer having a polymeric layer positioned Within said
`reactor;
`an oxygen plasma source located inside said reactor; and
`a wafer biasing apparatus to anisotropically direct ions
`from a plasma toward said wafer, wherein said wafer is
`biased to ground.
`
`30
`
`50
`
`55
`
`60
`
`65
`
`* * * * *
`
` Ex.1015 p.7