IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`Udo Hartmann, Sascha Nerger
`In re Patent of:
`7,124,325 Attorney Docket No.: 24069-0004IP1
`U.S. Patent No.:
`October 17, 2006
`
`Issue Date:
`Appl. Serial No.: 10/680,782
`
`Filing Date:
`October 7, 2003
`
`Title:
`Method And Apparatus for Internally Trimming Output
`Drivers and Terminations in Semiconductor Devices
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`PETITION FOR INTER PARTES REVIEW OF UNITED STATES PATENT
`NO. 7,124,325 PURSUANT TO 35 U.S.C. §§ 311–319, 37 C.F.R. § 42
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`Case IPR2017-00382
`Attorney Docket No: 24069-0004IP1
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`TABLE OF CONTENTS
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`
`Introduction .......................................................................................................... 1
`I.
`II. Requirements for IPR .......................................................................................... 1
` Standing ............................................................................................................ 1
` Challenge and Relief Requested ....................................................................... 1
`III. Background ....................................................................................................... 3
` Overview of the ’325 Patent ............................................................................. 3
`IV. Claim Construction ........................................................................................... 7
`V. Application Of Prior Art To Challenged Claims ................................................. 8
` GROUND 1: Claims 1-20 are obvious over Tanaka in view of Ikehashi under
`35 U.S.C. § 103 ....................................................................................................... 8
` GROUND 2: Claims 1, 8-14, and 16-17 are obvious over Garrett in view of
`Hassoun under 35 U.S.C. § 103 ............................................................................ 57
` GROUND 3: Claims 2-7, 15, and 18-20 are obvious over Garrett in view of
`Hassoun and Ishikawa under 35 U.S.C. § 103 ..................................................... 80
`VI. Statement Of Non-Redundancy ...................................................................... 90
`VII. Conclusion ...................................................................................................... 91
`VIII. Mandatory Notices Under 37 C.F.R § 42.8(a)(1) .......................................... 93
` Real Party-In-Interest Under 37 C.F.R. § 42.8(b)(1) ..................................... 93
` Related Matters Under 37 C.F.R. § 42.8(b)(2) ............................................... 93
` Lead And Back-Up Counsel Under 37 C.F.R. § 42.8(b)(3) .......................... 93
` Service Information ........................................................................................ 93
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`Case IPR2017-00382
`Attorney Docket No: 24069-0004IP1
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`EXHIBIT LIST
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`Exhibit No.
`
`Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`U.S. Patent No. 7,124,325 (“the ’325 patent”)
`
`Declaration of Nick Tredennick, Ph.D
`
`U.S. Patent No. 7,000,160 to Tanaka et al. (“Tanaka”)
`
`U.S. Patent No. 6,643,180 to Ikehashi et al. (“Ikehashi”)
`
`U.S. Patent No. 6,556,052 to Garrett et al. (“Garrett”)
`
`U.S. Patent No. 5,844,913 to Hassoun et al. (“Hassoun”)
`
`U.S. Patent No. 5,991,221 to Ishikawa et al. (“Ishikawa”)
`
`Return of Service for Complaint in Polaris Innovations Ltd. v.
`Dell Inc., and NVIDIA Corp., No. 5:16-CV-451-XR (W.D.
`Tex. 2016)
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`iii
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`I.
`
`INTRODUCTION
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`Case IPR2017-00382
`Attorney Docket No: 24069-0004IP1
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`NVIDIA Corporation (“Petitioner” or “NVIDIA”) petitions for Inter Partes
`
`Review (“IPR”) of claims 1-20 (“the Challenged Claims”) of Patent No. 7,124,325
`
`(“the ’325 patent”).
`
`II. REQUIREMENTS FOR IPR
`
`
`
`Standing
`
`Petitioner certifies that the ’325 patent is available for IPR. This petition is
`
`being filed within one year of service of a complaint against Petitioner on July 25,
`
`2016. See Ex. 1008, 6. Petitioner is not barred or estopped.
`
` Challenge and Relief Requested
`
`Petitioner requests IPR of the Challenged Claims on the grounds below, as
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`explained in this petition and in Ex. 1002.
`
`Ground
`Ground 1
`
`Ground 2
`
`Ground 3
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`
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` 
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`’325 Claims
`1-20
`
`1, 8-14, and 16-17
`
`2-7, 15, and 18-20
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`Basis
`Obvious over Tanaka
`and Ikehashi
`Obvious over Garrett
`and Hassoun
`Obvious over Garrett,
`Hassoun, and Ishikawa
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`1
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`The filing date of the ’325 patent is October 7, 2003. It claims foreign
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`priority to October 7, 2002. Each reference pre-dates this and qualifies as prior art,
`
`e.g., as follows:
`
`Reference
`
`Date
`
`Section
`
`Tanaka
`
`Ikehashi
`
`Garrett
`
`February 27, 2002 (filed)
`
`102(e)
`
`April 25, 2002 (published)
`
`102(b)
`
`June 13, 2002 (published)
`
`102(b)
`
`Hassoun
`
`December 1, 1998 (issued)
`
`102(b)
`
`Ishikawa
`
`November 23, 1999 (issued)
`
`102(b)
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`
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`2
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`III. BACKGROUND
`
` Overview of the ’325 Patent
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`Case IPR2017-00382
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`The ’325 patent describes a method and device for trimming semiconductor
`
`interface devices. Ex. 1001, Abstract. Interface devices, like output drivers and
`
`terminations (id., 3:18-21), have parameters that affect reading and writing from a
`
`data bus (id., 1:36-41). “[T]he impedance of the output drivers…[,] which a
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`semiconductor device uses to effect a write access to the data bus,” is an interface
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`parameter that, if trimmed correctly, can allow for a higher data transmission rate.
`
`Id., 1:42-54.
`
`These interface devices are subject to variation due to the manufacturing
`
`process, temperature variation during operation, and other such variations over
`
`time. Id., 1:63-2:5. Accordingly, as recognized by the ’325 patent, prior art
`
`methods of trimming existed to trim the interface devices “before or during the
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`initial startup…or repeatedly during [] operation.” Id. 2:6-17. Indeed, the ’325
`
`patent observes that interface devices have settable “control elements…in the form
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`of switchable impedances whose respective value can be programmed” based on a
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`value saved in a “trimming register.” Id.
`
`The ’325 patent describes a typical prior art setup that leverages a “test
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`apparatus” containing a current source and a voltmeter connected to the device to
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`be tested. Id., 2:30-50. With a variable impedance in the interface device set to a
`3
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`minimum value, a “measurement current” is “impress[ed]” on the device and the
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`Case IPR2017-00382
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`voltmeter measures the resulting voltage. Id. The test device compares the
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`measured voltage with a nominal voltage, and as long as the measured voltage is
`
`below the nominal voltage, the impedance is incremented. Id. Once the measured
`
`voltage is greater, the register value corresponding to the impedance level “is
`
`stored in a suitable manner for further use.” Id. The prior art test setup is shown in
`
`Figure 1:
`
`voltmeter in test
`apparatus
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`4
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`The ’325 patent purports to solve prior art issues by providing a “trimming
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`unit ... within the semiconductor device” rather than within the test device (as
`
`depicted in Fig. 1 above). Id., 3:53-67. Figure 3 shows the proposed integration of
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`the “trimming unit” into the semiconductor device:
`
`trimming unit
`in the device
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`5
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`As shown in Figure 3 above, trimming unit 5 is connected to the interface
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`devices 10a-10d, and to trimming registers 14. Id., Fig. 3, 8:4-11. Trimming
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`registers 14 are connected to the settable control elements of the interface devices,
`
`which are settable impedances. Id. To trim the interface devices, the trimming
`
`unit compares the measurement voltage, UM, with a nominal voltage, US, and if the
`
`measured voltage is smaller, the trimming unit increases the value of trimming
`
`registers 14, starting from a low value. Id., 8:12-22.
`
`Figure 4 (below) shows additional details of the trimming unit. In particular,
`
`comparator unit 56 compares the measured voltage UM with nominal voltage US.
`
`Id., 8:39-59. Based on that comparison, logic unit 57 either writes a new value to
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`trimming registers 14, or else it writes the existing trimming value to nonvolatile
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`memory unit 59. Id.
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`Case IPR2017-00382
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`comparator compares
`the measurement
`voltage UM with
`nominal voltage US
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`
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`IV. CLAIM CONSTRUCTION
`
`A claim subject to IPR is given its “broadest reasonable construction in light
`
`of the specification of the patent in which it appears.” 37 C.F.R. § 42.100(b).
`
`Under the broadest reasonable construction, Petitioner does not submit that any
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`claim terms require construction at this time. Petitioner reserves the right to assert
`
`claim construction positions in district court proceedings that apply a different
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`claim construction standard.1
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`V. APPLICATION OF PRIOR ART TO CHALLENGED CLAIMS
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`As detailed above (incorporated herein) and below, this request shows a
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`reasonable likelihood that Petitioner will prevail on the Challenged Claims.
`
` GROUND 1: Claims 1-20 are obvious over Tanaka in view of
`
`Ikehashi under 35 U.S.C. § 103
`
`Both Tanaka and Ikehashi are directed to techniques for trimming
`
`semiconductor interface devices. Ex. 1003, 1:5-12; Ex. 1004, 1:15-23, 11:7-12. In
`
`fact, both references disclose trimming in a very similar manner, using a variable
`
`resistor and a feedback circuit that iteratively adjusts the trimming value. See
`
`Ground 1:[14.3]. A POSITA would have been motivated to modify the system of
`
`Tanaka to implement features disclosed by Ikehashi. Ex. 1002, ¶¶ 25-27.
`
`                                                            
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` 1
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` The claim construction standard for district court (“ordinary and customary
`
`meaning”) is different than the broadest reasonable interpretation standard applied
`
`in IPR. Due to the different standards, disclosure of the references identified by
`
`Petitioner as teaching a claim term of the ’325 patent is not an admission that the
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`claim term is met by any disclosure for infringement purposes, or that the claim
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`term is enabled or meets the requirements for written description.
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`A POSITA would have found it obvious and been motivated to modify
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`Tanaka with Ikehashi because doing so entails the use of known solutions to
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`improve similar systems and methods in the same way. Ex. 1002, ¶¶ 25-27. Both
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`references disclose similar trimming units that compare a measured voltage with a
`
`nominal voltage in arriving at a trimming value. See Ground 1:[14.3]. In one
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`example, a POSITA would have been motivated because Ikehashi discloses a
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`simpler more direct feedback mechanism when compared to Tanaka. Compare Ex.
`
`1003, Fig. 4 with Ex. 1004, Fig. 16; Ex. 1002, ¶¶ 25-27. For instance, Tanaka
`
`provides a feedback mechanism that sends the output of its comparator to a
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`decision register that is readable by its CPU over a bus. Ex. 1003, Fig. 4. By
`
`contrast, Ikehashi directly connects the inverted output of its comparator with its
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`control logic, eliminating the need for bus reads contemplated by Tanaka, and thus,
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`simplifying the approach. Ex. 1004, Fig. 16; Ex. 1002, ¶ 26. Because they use the
`
`same general algorithm for arriving at a trimming value, a POSITA would have
`
`known that the teachings/features of Ikehashi could be combined into the systems
`
`of Tanaka to improve Tanaka’s similar system/method while staying true to
`
`Tanaka’s general approach. Ex. 1002, ¶¶ 25-27.
`
`Second, a POSITA would have been motivated to combine Tanaka with the
`
`teachings of Ikehashi to achieve additional benefits, such as the benefits that flow
`
`from integrating Ikehashi’s output terminal monitoring during testing. Ex. 1002, ¶
`9
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`27. Tanaka introduces the concept of monitoring outputs, as well as some
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`interactions between the test apparatus and the device under test. See, e.g., Ground
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`1:[5.0]. Ikehashi extends this concept by recognizing the appropriateness of
`
`monitoring different portions of the circuit than monitored by Tanaka. Ex. 1004,
`
`Fig. 16; Ex. 1002, ¶ 27. A POSITA would have recognized that additional benefits
`
`would arise from integrating the teachings of Ikehashi, given the context of testing
`
`and the benefits of gathering more data relating to disparate aspects of items under
`
`testing. Id. Accordingly, it would have been obvious to combine Tanaka and
`
`Ikehashi. Ex. 1002, ¶¶ 25-27.
`
`Thus, a POSITA would have combined the teachings of Tanaka and
`
`Ikehashi in a manner that would have integrated Tanaka’s disclosed test apparatus
`
`configuration/orientation/integration (e.g., including its device under test, trimming
`
`unit, trimming register, and interface device) with Ikehashi’s simplified trimming
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`unit feedback design, which provides feedback from the comparator’s output to the
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`control logic and connects the control logic with the trimming register. Id. In
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`addition, when combining these teachings, a POSITA would have integrated
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`Ikehashi’s voltage output monitoring into Tanaka’s design to enable improved
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`monitoring during testing. Id.
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`Claim 14 is the broadest claim of the ’325 patent. The prior art of Ground 1
`
`renders obvious each limitation of the claims, but because claim 14 is the broadest
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`claim, Ground 1 begins with claim 14. Thereafter, claims depending from claim
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`14 are addressed, followed by other independent claims and their dependents.
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`[14.0]: A semiconductor device comprising:
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`Tanaka discloses a semiconductor device. Ex. 1003, Abstract (“A
`
`semiconductor integrated circuit…”), Fig. 25. Ikehashi also discloses a
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`semiconductor device. Ex. 1004, Abstract (“a method of testing a nonvolatile
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`semiconductor memory integrated on a semiconductor chip”), Fig. 1.
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`[14.1]: at least one interface device having a settable control element;
`
`Tanaka discloses a semiconductor device having at least one interface device
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`that has a settable control element. For example, flash memory chip 5A (shown in
`
`Figure 25 below) contains timing controller 50 (“TCNT”) that is connected to
`
`boosting circuit 6A and voltage trimming circuit 7A. The timing controller
`
`receives memory commands and “generates internal timing signals and operating
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`voltages such as a write voltage and an erase voltage.” Id., 17:23-36. “The
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`operating voltages including the write voltage and erase voltage are generated by
`
`using the high voltage Vpp generated by the boosting circuit 6A.” Id.; see also id.
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`8:49-59.
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`timing
`controller
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`Id., Fig. 25.
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`The disclosed interface device comprises timing controller 50 and boosting
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`circuit 6 (items 60-66 in Fig. 4).2 As shown below in Figure 4, boosting circuit 6
`
`
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`                                                            
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` 2
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` For consistency in referencing Tanaka, Figure 4 is referenced with respect to the
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`trimming and boosting circuits. Figure 26 also references the same circuitry and
`
`method for the trimming and boosting circuits, but refers back to the explanation of
`
`Figure 4. Ex. 1003, 17:37-40.
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`contains a settable control element, including voltage dividing circuit 62, selector
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`63, and decoder 65. Id., 10:51-11:5. Based on a value in the trimming register,
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`these elements decode the value and set the variable impedance circuit (62). The
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`output of this boosting circuit is Vpp, which is used by the timing controller.
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`the settable control element includes voltage
`dividing circuit 62, selector 63, and decoder 65
`
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`Ikehashi also does. Ikehashi discloses semiconductor memory. Ex. 1004,
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`Abstract (“a method of testing a nonvolatile semiconductor memory integrated on
`
`a semiconductor chip”). Ikehashi discloses that the semiconductor has a plurality
`
`of interface devices, for example, Figure 1 shows control logic that manages
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`buffers and registers in order to read from and write to memory:
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`control
`logic
`managing
`buffers
`and
`registers
`
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`Id., Fig. 1; 8:60-10:18. The interface device also includes part of voltage generator
`
`circuit 20, which “generates a variety of voltages for use in chips. This voltages
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`[sic] include Vref (reference voltage), Vpgm (writing voltage), an internal fall
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`voltage (Vdd), an erasure voltage (Verase), a non-selected cell word line voltage
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`(Vread) supplied to a non-selected cell word line and the like.” Id., 9:51-56.
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`Ikehashi discloses multiple implementations of the voltage generator circuit,3 but
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`one example is shown in Figure 16 related to the read voltage:
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`the settable control
`element includes
`variable resistor
`circuit 73
`
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`With reference to Figure 16, the interface device includes the Vread charge
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`pump 71, settable resistor 73, and resistor 74. These work together in generating
`
`the read voltage. Id. 16:11-18. Because “variable resistor circuit 73” is settable
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`                                                            
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` 3
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` For consistency, the citations herein refer to the disclosure of a trimming circuit
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`for the read voltage Vread, but it should be noted that other similar circuits and
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`techniques are disclosed for trimming other memory interface voltages.
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`15
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`based on the trimming process (id., 16:3-38), Ikehashi discloses an interface device
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`Case IPR2017-00382
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`with a settable control element.
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`[14.2]: a trimming register connected to said control element; and:
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`Tanaka discloses a trimming register connected to the control element. In
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`particular, the trimming register 66 is connected to the control element 62 via the
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`circuitry that is used to set the control element (decoder 65 and selector 63):
`
`the trimming register is
`connected to the control element
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`Ikehashi also discloses this. In Ikehashi, trimming data register 21 is
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`connected to variable resistor circuit 73. Ex. 1004, Fig. 16:
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`the trimming data
`register is connected
`to the variable
`resistor circuit
`
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`[14.3]: a trimming unit for writing to said trimming register based on a
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`measured variable detected on said interface device;
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`Tanaka discloses a trimming unit in the semiconductor device for writing to
`
`the trimming register based on a measured variable detected on the interface
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`device. For example, the “Voltage Trimming Circuit,” which is the trimming unit,
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`is identified in Figures 1 (below) and 25 (reproduced in Ground 1:[14.1]). The
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`voltage trimming circuit “finely adjusts the write voltage obtained by the boosting
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`circuit.” Id., 8:57-59.
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`voltage trimming
`circuit
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`The trimming unit disclosed in Tanaka includes comparison circuit 70,
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`decision register 71, and the trimming program that manages the trimming process
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`from the CPU. Id., 11:6-57, Fig. 4 (below):
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`the trimming unit includes comparison circuit 70,
`decision register 71, and the trimming program
`
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`As discussed above, the interface device includes the boosting circuit
`
`disclosed by Tanaka. See Ground 1:[14.1]. The boosting circuit outputs a voltage,
`
`Vpp, which is measured by comparison circuit 70 of the trimming unit. Ex. 1003,
`
`Fig. 4 (above), 11:9-12. Thus Vpp is the claimed “measured variable” or
`
`“measurement voltage.” Tanaka discloses using comparison circuit 70 to compare
`
`the measurement voltage (“Vpp”) with a nominal voltage (“reference voltage” or
`
`“Vref”). Ex. 1003, 11:6-12 (“To enable the high voltage Vpp to be obtained at a
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`target value by the above-described fine adjustment, a comparison circuit 70,
`
`which operates as a decision circuit, and a decision register 71 are provided. The
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`comparison circuit 70 compares an expected voltage Vref supplied as a
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`comparative voltage from an external evaluation device 18 and the voltage Vpp
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`generated by the boosting section 60.”), Abstract (“Each LSI incorporates a
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`comparison circuit comparing an expected voltage value and a boosted voltage
`
`generated in itself.”). This is shown in Figure 4:
`
`comparison circuit 70 compares measurement
`voltage Vpp with nominal voltage Vref
`
`
`Tanaka further discloses writing to a trimming register based on a measured
`
`variable, using the difference between the measurement voltage (Vpp) and the
`
`nominal voltage (Vref). In particular, decision register 71 holds the result of the
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`comparison of the reference voltage and Vpp. Ex. 1003, 11:6-21. Based on that
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`result, the trimming program in the CPU will do one of two things. If the reference
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`voltage is greater than Vpp, the program will “updat[e] the control data in the
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`20
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`trimming register 66,” which the boosting circuit will then decode and use to
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`change the settable control element shown in Figure 4:
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`the value in the trimming register may be updated which
`is decoded and used to set the settable control element
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`
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`Id., Fig. 4, 2:40-65, 10:58-11:5, 11:36-57. The resulting change to voltage
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`dividing circuit 62 causes the value of Vpp to change. Id., 10:58-11:5. The
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`updated value is again compared by comparison circuit 70 and the process repeats.
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`Id., 11:27-57, Fig. 5. As depicted in Fig. 5, when Vpp reaches the value of the
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`reference voltage, the trimming process stops iterating, and the value in the
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`trimming register reflects the “trimming value at which the measurement voltage
`
`matches the nominal voltage” as recited by claim 1. Id., 11:27-57, Fig. 5:
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`when the
`measurement
`voltage reaches the
`nominal voltage,
`the trimming
`process stop
`iterating
`
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`The trimming value is available in trimming register 66, and can be used or
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`saved elsewhere. Ex. 1003, 11:66-12:9; 18:54-63.
`
`Ikehashi also discloses this element. Ex. 1004, 1:15-23 (“The present
`
`invention relates to a semiconductor device…being capable of adjusting values of
`
`a pulse width of the pulse generated by these circuits and a value of an internal
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`voltage. More particularly, the present invention relates to a nonvolatile
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`Case IPR2017-00382
`Attorney Docket No: 24069-0004IP1
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`semiconductor memory that internally generates a reference voltage, a writing
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`voltage, a erasure voltage, and a readout voltage.”), 15:41-16:48, Figs. 3, 13, 16,
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`11:7-12 (“This step carries out…trimming of a value of a voltage generated by the
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`internal voltage generator circuit 20. The voltages to be trimmed here include: a
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`reference voltage Vref, an internal fall voltage Vdd, and a non-selected cell work
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`line voltage Vread.”). In particular, the trimming unit is shown in Figure 16, and
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`consists of comparator 75, inverter 76, and control circuit 68, shown below: 
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`the trimming unit
`consists of comparator
`75, inverter 76, and
`control circuit 68
`
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`Ikehashi also discloses acquiring a “measured variable” or measurement
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`voltage. Specifically, voltage “VMON” is the measurement voltage, which is
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`acquired from connecting Vread with the voltage divider circuit formed by variable
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`resistor circuit 73 and resistor 74. Id., 16:11-24, Fig. 16; see also id., 15:47-50.
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`Case IPR2017-00382
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`Measurement voltage “VMON” is compared by comparator 75 to Vref, which is a
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`nominal voltage or reference voltage. Ex. 1004, 16:11-20 (“…The above divided
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`voltage VMON is compared with the reference voltage Vref by a comparator 75.”);
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`see also id., 15:47-50, Fig. 16: 
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`measurement voltage
`VMON is compared to
`nominal voltage Vref
`
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`The output of comparator 75 is inverted by inverter 76 and sent to the
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`control logic of the trimming unit. Ex. 1004, 16:11-24, Fig. 16. Based on this
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`“flag,” the control circuit either increments the value in the trimming data register,
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`or it resets the trimming data register. Id. The trimming data register holds the
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`trimming data that is used to set the settable control element, variable resistor
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`circuit 73. Id., 15:23-36. These connections are shown in Figure 16:
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`Case IPR2017-00382
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`the control logic can
`increment or reset the
`value in the trimming
`data register, which
`holds the trimming data
`
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`[14.4]: said trimming unit connected to said interface device and said trimming
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`register.
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`See Grounds 1:[14.1]-[14.3].
`
`The trimming unit of Tanaka (including comparison circuit 70, decision
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`register 71, and the trimming program) is connected to the trimming register and
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`the boosting circuit via the bus. Ex. 1003, Fig. 4 (below). It also connects to the
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`boosting circuit via the node with Vpp that connects to settable control element
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`(62) and boosting section 60. Id.
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`the trimming unit is connected to the trimming
`register and the interface device
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`As shown in Figure 25, voltage trimming circuit 7A is also connected to
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`timing controller 50, which is part of the interface device:
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`the voltage
`trimming
`circuit is
`connected
`to the
`timing
`controller
`
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`Ikehashi also discloses this. The interface device, trimming unit, and
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`trimming register were identified above in Grounds 1:[14.1]-[14.3]. As shown in
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`annotated Figure 16 below, the trimming unit (red) is connected to the trimming
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`register (green) and part of the interface device (blue):
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`the trimming unit
`(red) is connected to
`the trimming
`register (green) and
`part of the interface
`device (blue)
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`[15.0]: The semiconductor device according to claim 14, further comprising: a
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`monitor output for transmitting a value for said control element to a test
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`apparatus;
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`See Ground 1:[6].
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`[15.1]: said value being a measured variable and/or a trimming value; and
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`See Grounds 1:[5.0], [5.1], [6].
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`[15.2]: said value being ascertained by said trimming unit.
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`See Grounds 1:[1.5]-[1.8].
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`[16]: The semiconductor device according to claim 14, wherein said trimming
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`unit includes a reference voltage device and a voltage divider for producing a
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`nominal voltage.
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`Ikehashi discloses the use of a voltage divider in arriving at the measurement
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`voltage. Voltage “VMON” is the measurement voltage, which is acquired from
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`connecting Vread with the voltage divider circuit formed by variable resistor
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`circuit 73 and resistor 74. Id., 16:11-24, Fig. 16 (below); see also id., 15:47-50.
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`VMON is the
`measurement
`voltage
`
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`A POSITA would have found claim 16 to be obvious based on this disclosure and
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`also the knowledge in the prior art at the time. See Ex. 1002, ¶ 51. Using voltage
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`dividers to produce a reference voltage was very well known in the art. Id.
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`[17.0]: The semiconductor device according to claim 14, wherein: said trimming
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`unit has a comparator unit for providing an output signal obtained by comparing
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`a nominal voltage with a measurement voltage produced in said interface device;
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`and
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`See Grounds 1:[1.6]-[1.7].
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`[17.1]: said trimming unit has a logic unit for writing to said trimming register
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`based on said output signal from said comparator unit.
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`See Ground 1:[1.8].
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`[18]: The semiconductor device according to claim 14, wherein: said trimming
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`unit has a nonvolatile memory unit being programmed based on a trimming
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`value.
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`See Ground 1:[2].
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`[19]: The semiconductor device according to claim 18, wherein: said memory
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`unit is configured for directly controlling said control element.
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`See Grounds 1:[2], [7].
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`[20]: The semiconductor device according to claim 18, wherein: said memory
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`unit is configured for loading said trimming register.
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`See Ground 1:[3].
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`[1.0] A method for trimming interface devices, which comprises:
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`Tanaka discloses an invention that “relates to a trimming technique for
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`finely adjusting a voltage… and to a testing method of performing trimming on
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`such a semiconductor integrated circuit.” Ex. 1003, 1:5-12. The values being
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`trimmed relate to “programming voltage[s]” that affect parameters like “the width
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`of write pulses.” Id., 1:13-21, 41-49, 8:57-59. Tanaka also discloses trimming
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`interface devices that use the trimming information in generating and using the
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`memory interface voltages. Id., 17:23-36, Figs. 4-5 (showing trimming unit), 25
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`(showing interface device).
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`Ikehashi also discloses trimming interface devices, including values related
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`to read, write, and reference voltages used by controllers in flash memory. Ex.
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`1004, 1:15-23, 15:41-16:48, Figs. 3, 13, 16, 11:7-12 (“This step carries
`
`out…trimming of a value of a voltage generated by the internal voltage generator
`
`circuit 20. The voltages to be trimmed here include: a reference voltage Vref, an
`
`internal fall voltage Vdd, and a non-selected cell work line voltage Vread.”).
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`Accordingly, Tanaka and Ikehashi each disclose a method for trimming
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`interface devices.
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`[1.1] providing a semiconductor device having a plurality of interface devices
`
`and providing each one of the plurality of interface devices with a settable
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`control element;
`
`See Ground 1:[14.1].
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`[1.2] providing a test apparatus having a current source;
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`Tanaka discloses an evaluation device 18 that provides a constant current
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`through a resistor (Ex. 1003, 13:2-5) as shown below: 
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`constant
`current
`through
`a
`resistor
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`In addition, Tanaka states that “a trimmed value which coincides with a voltage or
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`a current of an expected value can be obtained by only supplying the expected
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`voltage or current value externally and executing a predetermined trimming
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`program.” Id., 19:6-9.
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`[1.3] connecting the current source in the test apparatus to an interface
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`connection on the semiconductor device, the interface connection being
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`connected to one of the plurality of interface devices;
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`As discussed in Ground 1:[1.2], Tanaka discloses a test apparatus having a
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`current source. Moreover, as shown in Figure 12, the current source is connected
`
`to a pin on the semiconductor device labeled “Pad,” which is an interface
`
`connection. Ex. 1003, 13:2-5. Tanaka also references supplying an expected
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` 
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`voltage or current value externally. Id., 19:6-9. The Pad interface connection is
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`Case IPR2017-00382
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`also connected to the interface devices as shown above and in Figures 4 and 25
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`(reproduced in Ground 1:[1.1]).4
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`[1.4] controlling a measurement current produced by the current source and
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`setting the control element of the one of the plurality of interface devices to an
`
`initial value;
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`Tanaka discloses controlling a measurement current produced by the current
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`source by directing “the current through the dummy MOS transistor 74” to produce
`
`a voltage. Id., 13:6-17. A POSITA would also have recognized this limitation to
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`                                                            
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` 4
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` Although Figure 12 relates to an embodiment showing “current trimming” rather
`
`than voltage trimming, Tanaka states that “[t]he same trimming procedure a