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`US005991221A
`
`United States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,991,221
`
`lshikawa ct al.
`
`[45] Date of Patent:
`
`Nov. 23, 1999
`
`[54] MICRXOMPUTER AND
`MICROPROCESSOR HAVING FLASH
`MEMORY OPERABLE FROM SINGLE
`EXTERNAL POWER SUPPLY
`
`FOREIGN l’A'l'l:'N'J' DOCUMENTS
`
`2-30?259
`8-13408
`
`12.51990
`1.51996
`
`Japan.
`Japan.
`
`[75]
`
`lnvenlors: Eilclti lsltikawsl, Princeton, N..l.;
`Yasnyuki Saitn, Kodaira, Japan;
`Masanao Sato. 'l'ol<yo, Japan; Naoki
`Yoda, Sayatna, Japan; Klyushi
`Matsuhara, Higashitnurayama, Japan
`
`[73] Assignec: Hitachi, Ltd., Tokyo, Japan
`
`[21] Appl. No.: 091’0l6,30l)
`
`[22]
`
`Filed:
`
`Jan. 30, 1998
`
`Int. Cl.“
`[5]]
`[52] U.S. C].
`[58] Field of Search
`
`
`
`G11-C 7100
`3653226; 3651'l89.0Ift; 3651’l89.O9
`365F226, 185.01,
`"38'5.='139.05, 139.11, 139.09
`
`[56]
`
`References Cited
`U.S. PA'l‘l;‘l'\I'l‘ D0(."UMl."N'l‘S
`
`8/1995 Kuroda et al.
`..
`5,444,504
`5_.537_.lTF3
`7/1996 Arimoto
`
`.. 365.-“Z26
`327.-“S46
`
`Prt'-nmrry E1crmtfner—David Nelms
`Assisttmf Exrm:irter—DaviLl Lam
`Att0rr1e}_',Agem, or Firm—Antonelli, Terry, Stout & Kraus,
`LLP
`
`[57]
`
`ABSTRACT
`
`A microcomputer incorporating a flash memory,-' which is
`erased and programmed electrically in a stable manner
`Within a relatively wide range of external power supply
`voltages including those for low-voltage operations. The
`microcomputer comprises a voltage clamp unit including a
`reference voltage generating circuit and a constant voltage
`generating circuit.
`In operation,
`the voltage clamp unit
`generates El voltage of at low dependency on -'cl$LIp1:Il'_\-' voltage
`and clamps the generated voltage to a voltage level which,
`within a tolerable range,
`is lower than ti single supply
`voltage externally furnished. This prevcn L4 voltages boosted
`by boosting circuits operating on the clamped voltage, i.e.,
`programming and erasure voltages, from being dependent
`on the externally supplied voltage.
`
`35 Claims, 29 Drawing Sheets
`
`40
`
`Vcc
`0 (2.7v~5.5v)
`
`VOLTAGE CLAMP
`MEANS
`
`Vfix (2.5v)
`
`RING
`OSCILLATOR
`
`CHARGE PUMP
`
`CHARGE PUMP
`
`I CIRCUIT
`I CIRCUIT
`
`CHARGE PUMP
`CIRCUIT
`
`1
`
`NVIDIA 1007
`
`NVIDIA 1007
`
`

`
`U.S. Patent
`
`N0v.23,1999
`
`Sheet 1 or 29
`
`5,991,221
`
`FIG.
`
`1
`
`40
`
`
`Vcc
`(2.7V~5.5V)
`
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`44
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`
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`
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`
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`
`

`
`U.S. Patent
`
`N0v.23,1999
`
`Sheet 2 or 29
`
`5,991,221
`
`FIG. 3
`
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`N0v.23, 1999
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`

`
`U.S. Patent
`
`Nov. 23, 1999
`
`Sheet 21 of 29
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`5,991,221
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`U.S. Patent
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`Nov. 23, 1999
`
`Sheet 22 of 29
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`5,991,221
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`

`
`U.S. Patent
`
`Nov. 23, 1999
`
`Sheet 24 of 29
`
`5,991,221
`
`FIG. 26
`
`ONE BLOCK ERASUFIE FLOWCHART
`
`START
`
`SET SWE—bit
`
`IN FLMCR1
`
`n=1
`
`SET EBFI1
`
`SET ESU—bit
`
`IN FLMCR1
`
`SET E—bi1 IN FLMCR1
`
`CLEAR E-bit IN FLMCR1
`
`CLEAR ESU-bit
`
`IN FLMCFI1
`
`25
`
`S1
`
`S2
`
`S3
`
`S4
`
`S5
`
`S6
`
`S7
`
`Efiifigfi
`
`EHASE
`STOP
`
`

`
`U.S. Patent
`
`Nov. 23, 1999
`
`Sheet 25 of 29
`
`5,991,221
`
`INCFIEMENT
`
` ADDRESS
`
`
`¢ O
`
`
`S1
`
`CLEAR EV—bit
`
`IN FLMCR1
`
`S15
`
`K
`
`31
`
`6
`
`CLEAR SWE-bit
`
`IN FLMCFI1
`
`ABNORMAL FINISH OF
`ERASUFIE
`
`
`
`
`
`
`
`LAST
`ADDRESS ?
`
`
`
`
`
`
`
`OK
`
`CLEAR EV—bil
`
`IN FLMCFI1
`
`CLEAFI SWE—bi1 IN FLMCFI1
`
`
`
`
`
`
`
`NORMAL COMPLETION
`OF EFIASUFIE
`
`26
`26
`
`
`
`
`
`DATA TO
`BE VERIFIED
`=ALL "1" '2
`
`

`
`U.S. Patent
`
`Nov. 23, 1999
`
`Sheet 26 M29
`
`5,991,221
`
`FIG. 28
`
`PROGRAMMING FLOWCHART
`
`STAHT
`
`SET SWE-bit IN FLMCFI1
`
`n==1
`
`f|ag=0
`
`WRITE DATA OF 32 BYTES
`CONTINUOUSLY
`
`SET PSU-bit IN FLMCR1
`
`SET P—bit
`
`IN FLMCR1
`
`CLEAR P—bit
`
`IN FLMCR1
`
`CLEAR PSU-bit IN FLMCR1
`
`T1
`
`T2
`
`T3
`
`T4
`
`T5
`
`T5
`
`T7
`
`T8
`
`27
`27
`
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`
`

`
`U.S. Patent
`
`Nov. 23, 1999
`
`Sheet 27 9129
`
`5,991,221
`
`FIG. 29
`
`9
`
`0
`
`SET PV-bit IN FLMCR1
`
`DUMMY WRITE TO VERIFY
`ADDRESS
`
`T9
`
`T10
`
`T1 1
`
`ADDRESS
`INCREMENT
`
`1E’éf’nE3“‘°BE
`
`T22
`
`T15
`
`
`
`OPERATE DATA
`TO BE REWRITE DATA
`
` NG
`
`
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`=ALL "1 "
`
`'?
`
`
`
`TRANSFER DATA TO BE
`REWRITE TO RAM
`
`T13
`
`
`
`:
`
`T14
`
`CLEAR PV-bit
`
`OK
`IN FLMCR1
`
`T17
`
`T18
`
`T20
`
`OK
`
`T19
`
`OK
`
`T21
`
`NG ® NG
`
`
`
`CLEAR SWE-bil
`
`IN FLMCR1
`
`CLEAR SWEb1t
`
`IN FLMCF11
`
`NORMAL COMPLETION
`OF PROGRAMMING
`
`PROGRAMMING ERROR
`
`
`
`28
`28
`
`

`
`U.S. Patent
`
`Nov. 23, 1999
`
`Sheet 23 of 29
`
`5,991,221
`
`FIG. 30
`
`(=::) ERASE STATE or THE MEMORY ceu. IS "1 -'
`PROGRAMMING IS EXECUTED TO THE MEMORY CELL WHOSE STATE
`IS TO BE DATA "0 "
`
`ORIGINAL
`
`DATA (V) DATA (X)
`
`COMMENT
`
`NO REPROGRAMMING IS
`EXECUTED TO THE MEMORY
`BIT THAT THE PROGRAMMING
`HAS BEEN COMPLETED
`
`THE PROGRAMMING IS
`NOT COMPLETED.
`RE—PROGRAMMlNG IS
`EXECUTED
`
`ERASE STATE,
`N0 PROGRAMMING IS
`EXECUTED
`
`29
`29
`
`

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`

`
`1
`MICROCOMPUTER AND
`MICROPROCESSOR HAVING FLASH
`MEMORY OPERABLE FROM SINGLE
`EXFERNAL POWER SUPPLY
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a semiconductor inte-
`grated circuit device cotnprising a non-volatile memory and
`a central processing unit. More particularly, the invention
`relates to techniques for providing a single-chip
`microcomputer, a data processing device, or a microproces-
`sor which includes a flash memory and a central processing
`unit having a single external power supply.
`Microcomputers incorporating a [lash memory are known
`lay the designations l"I8;’538F', I'I8r'3048 and II8r'34 34-F, avail-
`able from I-Iitachi ltd.
`
`Memory cell transistors constituting a flash memory each
`have a floating gate, a control gate, a source and a drain. As
`such, each memory cell transistor retains binary information
`representing a charge injection state of its floating gate. For
`example, electrically charging the floating gate of a memory
`cell transistor brings a threshold voltage of that memory cell
`into a high state. When the threshold voltage is raised
`relative to the control gate,
`the memory cell prevents a
`cttrrent h'om flowing. Electrically discharging the floating
`gate of the memory cell lowers the threshold voltage with
`respect to the control gate, which allows the current to flow
`through the memory cell. Illustratively, bringing the thresh-
`old voltage of the memory cell higher than a word line
`selecting voltage level of a read state is called an erasure
`operation (providing a logical “ 1" which signifies an erasure
`state); while, bringing the threshold voltage of the memory
`cell lower than the word line selecting voltage level of the
`read state is called a programming operation (providing a
`logical “(t" which signifies a programming state).
`Alternatively,
`the erasure state and the programming state
`may be defined inversely in terms of threshold voltage.
`Writing or erasing data to or from memory cell transistors
`presupposes that their floating gates are placed in a high
`electric field as needed. This requires that the voltage for
`erasure or programming purposes be higher than the com-
`mon power supply, such as 3 V or 5 V. Such a high voltage
`is provided as an external power supply.
`
`SUMMARY OF Tl-IE lNVEN'I‘ION
`
`To obtain a high voltage externally requires that a high
`voltage generating circuit be mounted on the printed circuit
`board on which the microcomputer is assembled. To handle
`high voltages involves use of a specialized printed circuit
`hoard design that typically detracts from general usability.
`The inventors of this invention investigated whether it
`was possible to use a single power supply, such as 3 V or 5
`J:‘J:
`V from which to operate a microcomputer incorporating a ‘
`llash memory‘. The inventors’ experiments involved gener-
`ating a high voltage for erasure and programming by inter-
`nally boosting the voltage from a single external power
`supply.
`Some manufacturers of microcomputers, conscious of
`today’s demand for lower power dissipation, have their
`devices operate on 3 V; while, manufacturers of some
`systems design their products to operate from a single 5 V
`power supply. Whetlter to use at 3V or a 5 V power supply
`is determined according to the specifications ol‘ the system
`to which the niicroconiputer in question is applied. In this
`respect, it is in a semiconductor manufacturers’ interest to
`
`60
`
`31
`31
`
`5,991,221
`
`2
`design microcomputers which are capable of operating with
`a relatively wide range of available power supplies, such as
`from 3 V to 5 V.
`
`l-TJ
`
`15
`
`25
`
`39
`
`35
`
`With the above points taken into consideration, the inven-
`tors proceeded with their studies and brought to light some
`problems of the related art. There are two major charge
`injection methods for charging flash memories: :1 channel
`injection method and a tunnel current method. The channel
`injection method involves letting a relatively large current
`flow through the channel of a given memory cell transistor
`to generate hot electrons near the drain, whereby the floating
`gate is electrically charged. The tunnel current method
`involves allowing a tunneling current
`to flow through a
`relatively thin tunnel oxide (insulating) film near the drain
`by application of an electric field of a predetermined inten-
`sity between the floating gate and the drain, whereby electric
`charging is accomplished. The inventors have found that the
`channel injection method was not suitable for internal volt-
`age boosting because of its need for a relatively large
`current. With the tunnel voltage current method, on the other
`hand, simply etfecting internal voltage boosting was found
`insuliicient to implement programming and erasure of an
`internal flash memory in a stable manner within a relatively
`wide range of external power supply voltages, including
`those for lowvvoltage operations.
`It is therefore an object ofthe present invention to provide
`a semiconductor
`integrated circuit device, such as a
`microcomputer, including a non-volatile memory, such as a
`flash memory, which can be erased and programmed elec-
`trically in a stable manner within a relatively wide range of
`external power supply voltages, including those for low-
`voltage operations.
`It is another object of the present invention to provide a
`semiconductor integrated circuit device, such as a
`microcomputer, which incorporates a non-votatile memory,
`such as a flash memory, which is capable of being erased and
`programmed electrically and which olfers higher usability
`than previously availabte.
`Other objects, features and advantages of the present
`invention will become apparent lrom the description pro-
`vided in the following specification with reference to the
`accompanying drawing.
`In carrying out the invention and according to one aspect
`thereof, there is provided a semiconductor integrated circuit
`device, such as a microcomputer, comprising a semiconduc-
`tor substrate incorporating a non—volatile memory, such as a
`‘flash memory, which is capable of being erased and pro-
`grammed electrically, and a central processing unit which is
`capable of accessing the non-volatile memory. The semi-
`conductor integrated circuit device operates on a single
`power supply voltage supplied to an external power supply
`terminal of the semiconductor substrate. The non—volatile
`memory includes: voltage clamp means which, using a
`reference voltage with a low dependency on a power supply
`voltage, clamps an output voltage to a first voltage lower in
`level than the single power supply voltage; boosting means
`for boosting the voltage output by the voltage clamp means
`to a positive and a negative high voltage; and a plurality of
`non—volatile memory cells which can be erased and pro-
`grammed by use of the positive and negative high voltages
`output by the boosting means.
`In the semiconductor integrated circuit device of the
`above constitution,
`the voltage clamp means generates a
`‘ voltage that is negligibly dependent on a supply voltage. The
`voltage thus generated is clamped to a voltage level which.,
`within a tolerable range of supply voltages for the semicon-
`
`

`
`5,991,221
`
`3
`ductor integrated circuit device, is lower than the single
`supply voltage externally furnished. The clamping prevents
`the voltages boosted by the boosting means operating on the
`clamped voltage, i.e., prograrrtming and erasure voltages,
`from being dependent on the externally supplied voltage.
`This in turn makes it possible to erase and program the
`incorporated non -volatile memory in a relatively wide range
`of externally supplied voitages, including those for low-
`voltage operations. Because these features are provided by
`use of a single external supply voltage, the semiconductor
`integrated circuit device incorporating the non-voltage
`memory is made easier and more convenient to use than
`before.
`
`l-TJ
`
`15
`
`25
`
`39
`
`35
`
`'lhe elficiency of boosting may be enhanced by changing
`a substrate bias voltage common to MOS transistors (metal-
`oxide semiconductors; MIS or metal-insulating semiconduc-
`tors may be used alternatively) carrying out charge pump
`operations when the boosted voltage has reached a prede-
`termined level.
`Illustratively,
`the boosting means may
`include: a charge pump circuit having boosting nodes for
`negative high voltage generation, the boosting nodes being
`connected to p-channel MOS transistors and capacitors so as
`to implement a charge pump action for generating the
`negative high voltage; and switching means for switching
`halfway through a boosting operation the substrate bias
`voltage common to the MOS transistors from the output
`voltage of the voltage clamp means to a second voltage
`lower in level than the output voltage. The second voltage is
`higher in level than the boosted voltage in elfecl at a time of
`switching the voltages. In this example, a decline in the
`substrate bias voltage lowers the threshold voltage of the
`MOS transistors through what is known as the substrate bias
`effect. The lowered threshold voltage promotes the move-
`ment ofelectric charges through the MOS transistors execut-
`ing charge pump operations. This in turn improves the
`elliciency of boosting operations and shortens the time it
`takes to reach a reqittred boosted voltage.
`The voltage being boosted by a charge pump operation
`fluctuates in amplitude in synchronism with the switching
`actions of the MOS transistors for charge pump operations.
`The resulting ripple effect may cause the substrate bias
`voltage to oscillate. Such oscillation is forestalled illustra-
`tively by the switching means pttssessing a hysteresis char-
`acteristic for maintaining the substrate bias voltage to the
`second voltage when the boosted voltage fluctuates in ampli-
`tude after the switching of the voltages. This kind of
`hysteresis characteristic may be acquired by use of a hys-
`teresis comparator or an SR tlip—flop circuit.
`Where a plurality of charge pump circuits operate from a
`single power supply,
`instantaneous drops in the powc-r
`supply voltage are minimized preferably by staggering the
`cha rge pump circuits in their operative phases. Illustratively,
`the boosting means may include: a negative voltage boosting
`charge pump circuit having boosting nodes for negative high
`J:‘J:
`voltage generation, the boosting nodes being connected to _
`MOS transistors and capacitors so as to implement a charge
`pump action for generating a negative high voltage; and a
`positive voltage boosting charge pttmp circuit having boost-
`ing nodes for positive high voltage generation, the boosting
`nodes being connected to MOS transistors and capacitors so
`as to implement a charge pump action for generating a
`positive high voltage. In this setup, the MOS transistors in
`the positive voltage boosting charge pump may be arranged
`so as to differ in on-state phase from the MOS transistors in
`the negative voltage boosting charge pump.
`Relatively large currents are needed to erase and program
`a non-volatile memory. For this reason, the power supply for
`
`_
`
`60
`
`‘
`
`32
`32
`
`4
`a boosting circuit should not be connected directly to the
`power supplies for other circuits. In this respect, the voltage
`clamp means may preferably include: a reference voltage
`generating circuit for generating a reference voltage with a
`low dependency on a power supply voltage; a first constant
`voltage generating circuit for generating a voltage by plac-
`ing an output circuit under control for negative feedback to
`the first voltage with respect to a reference voltage consti-
`tuted by the reference voltage generated by the reference
`voltage generating circuit; and a second constant voltage
`generating circuit For generating a voltage hy placing the
`output circuit under control for negative feedback to the first
`voltage with respect to a reference voltage constituted by the
`voltage output by the first constant voltage generating cir-
`cuit. The voltage output by the second constant voltage
`generating circuit may be supplied to the positive and
`negative voltage boosting means.
`The inventive semiconductor integrated circuit device
`may further comprise a third constant voltage generating
`circuit for generating El voltage by placing an output circuit
`under control for negative feedback with respect to a refer-
`ence voltage constituted by the voltage output by the lirst
`constant voltage generating circuit. In this setup, the voltage
`output by the third constant voltage generating circuit may
`serve as a power supply voltage for use by a read system.
`Variations in the voltage output by the voltage clamp
`means can result from di.tferences between processes. To
`line-adjust such output voltage variations, the voltage clamp
`means may preferably include: a trimming circuit; trimming
`control means for line-adjusting the trimming circuit
`in
`accordance with trimming adjustment information; and reg-
`ister means set with the trimming adjustment information to
`be supplied to the trimming control means. The register
`means may receive the trimming adjustment
`information
`that is transferred from a specific region of the non-volatile
`memory. This arrangement allows the output voltage to be
`trimmed as desired by software. The arrangement steers
`clear of lirnitations on conventional setups which, once
`programmed, cannot be modified subsequently because of
`their use of fuses.
`
`Where the trimming adjustment information is known to
`atfect
`the read voltage for the non-volatile memory,
`the
`transfer of the trimming adjustment information from the
`non-volatile memory to the register means should preferably
`be carried out when a
`read operation on the memory is
`allowed to take longer than the predeterrnined time. This
`arrangement
`is desirable with a view toward preventing
`malfunctions. Specifically, the information transfer may be
`performed in synchronism with reset operations of the
`semiconductor integrated circuit device. This permits inter-
`nal voltage fluctuations to settle within a reset operation
`before a trimming action is settled After the reset, a read
`operation is carried out
`in a stable manner. Where the
`trimming adjustment information affects only the voltages
`for programming and erasure of the non-volatile memory,
`the transfer of the information may be carried out before a
`first vector fetch (instruction fetch) during the reset period or
`following the release of the reset state.
`In view of the selection of trimming information in the
`test mode, the central processing unit should preferably be
`capable of accessing the register means mentioned above.
`Where the semiconductor integrated circuit device is
`programmed upon completion of a wafer (e.g_, logical ‘‘U‘' of
`a low threshold voltage) and is erased upon shipment (e.g.,
`logical "1” of a high threshold voltage), it is desirable to
`minimize variations that may occur in the output voltage of
`
`

`
`5,991,221
`
`6
`generating a high voltage for programming and erasure on
`the memory cell transistors; an address decoder for gener-
`ating a word line selection signal based on an address signal;
`a word driver circuit for establishing a word line selection
`level in effect upon a read operation as a first polarity with
`respect
`to the ground potential,
`the word driver circuit
`further establishing a word line selection level in etIect upon
`a write operation as a second polarity with respect to the
`ground potential; and timing control means acting upon a
`start and an end of a write operation to force all word lines
`to the ground potential, to invert logically the polarity of the
`selection level for the word line selection signal for the
`address decoder, and to switch operating power supplies of
`the word driver.
`
`These and other objects, features and advantages of the
`invention will become more apparent upon a reading of the
`following description and appended drawings.
`BRIEF DI.-‘.SCRlPTlON OF THE DRAWINGS
`
`FIG. 1 is a schematic block diagram outlining key parts of
`a power supply circuit:
`FIG. 2 is a block diagram of a conventional power supply
`circuit comparable to that in FIG. 1;
`FIG. 3 is a block diagram of a microcomputer according
`to the invention;
`FIG. 4 is an overall block diagram of a flash memory
`incorporated in the microcomputer;
`FIG. 5 is a circuit diagram of a memory cell array;
`FIG. 6 is a circuit diagram of a flash memory supplied
`with voltages for erasure;
`FIG. 7 is a circuit diagram of a flash memory supplied
`with voltages for programming;
`FIG. 8 is a block diagram of a flash memory cornprising
`operation voltage supplies;
`FIG. 9 is a table Eisting the symbols, names and descrip-
`tions of the operation voltage supplies shown in FIG. 8:
`FIG. 10 is a table showing how the voltage supplies in
`FIG. 8 and their operations are related;
`FIG. 11 is a table summarizing voltage levels that may be
`taken by the operation voltage supplies in FIG. 8;
`FIG. 12 is a circuit diagram of typical voltage clamp
`means;
`
`1-71
`
`15
`
`25
`
`39
`
`35
`
`5
`the voitage clamp means as a result of the voltages being
`extremely trimmed between the programming and the era-
`sure states. The minimizing of such output voltage variations
`may be effected illustratively by the trimming control means
`including selective logic for detennining trimming positions
`of the trimming circuit
`in accordance with the trimming
`adjustment information in such a manner that the trimming
`position in effect when the trimming adjustment information
`has an all-bit logic value of
`is adjacent to the trimming
`position in effect when the trimming adjustment information
`has an all-bit logic value of “O.” In this setup. the voltage
`output by the voltage clamp means may be minimized in
`terms of difference between where the non-volatile memory
`is programmed upon completion of a wafer, and where the
`non-volatile memory is erased upon shipment.
`It
`takes some time for the boosting means to gain a
`required boosted voltage. The required time is known to
`sutfer from process—dependent variations. A programming
`and an erasure operation must each be started after the
`boosted voltage has reached a predetermined voltage level.
`These aspects are controlled by the central processing unit
`running suitable software. Illustratively, the inventive semi-
`conductor integrated circuit device may comprise a control
`register for controlling the non -vola tile memory, the control
`register including: a programming set-up bit for instructing
`the boosting means to start a boosting operation For pro-
`gramming; a programming cnablc bit for designating a start
`of a programming operation by use of the boosted voltage;
`an erasing set-up bit for instructing the boosting means to
`start a boosting operation for erasure; and an erasing enable
`bit for designating a start of an erasing operation by use of
`the boosted voltage. This arrangement eliminates the need
`for additionally providing hardware, such as a timer, for
`controlling when to start the actual erasing or programming
`of the device after the erasure or the programming has been
`designated.
`Furthermore, the control register may include a program-
`ming enable bit for instructing the boosting me ans to prepare
`for a boosting operation, so that the instruction based on any
`of the erasing set-up bit and the programming set-up bit is
`accepted only if the programming enable bit isset to its true
`value. That is, a programming or erasure operation is carried
`out on condition that the programming enable bit he set to
`the true value. This arrangement helps prevent
`the non-
`volatile memory from getting inadvertently reprogrammed,
`for example, by a runaway central processing unit.
`Inadvertent reprogramming oftlte non-volatile memory is
`prevented more reliably by the control register including a
`protect bit, for example. which is set in accordance with an
`external terminal stat