(12) United States Patent
`
`Garrett, Jr. et al.
`
`(10) Patent N0.:
`
`([45) Date of Patent:
`
`US 6,556,052 B2
`Apr. 29, 2003
`
`US006556052B2
`
`SEMICONDUCTOR CONTROLLER DEVICE
`HAVING A CONTROLLED OUTPUT DRIVER
`CHARACTERISTIC
`
`(56)
`
`References Cited
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`FOREIGN PATENT DOCUMENTS
`
`EP
`
`0482392
`
`2/1991
`
`OTHER PUBLICATIONS
`
`Sasaki, H., et al., “High—Precision Automated Resistance
`Measurement Using A Modified Wheatstone Bridge,”
`CPEM, ’88 Digest, Japan, 1988, 1 page.
`Sasaki, H., et al., “Measurement of the Pressure Dependence
`of Standard Resistors Using A Modified Wheatstone
`Bridge,” Trans. IEE of Japan, vol. 109, No. 1/2, Jan./Feb.
`1989, 6 pages.
`
`(List continued on next page.)
`
`Primary Examiner—Jeffrey Zweizig
`
`(57)
`
`ABSTRACT
`
`A semiconductor controller device to control the operation
`of a semiconductor memory device. The controller device
`includes a first output driver coupled to a first output
`terminal, and a second output driver coupled to a second
`output terminal. In addition, the controller device includes a
`voltage divider, coupled between the first and second output
`terminals, to generate a control voltage based on a voltage
`level present on the first output terminal and a voltage level
`present on the second output
`terminal.
`In addition,
`the
`controller device also includes a comparator, coupled to the
`voltage divider,
`to compare the control voltage with a
`reference voltage, wherein an amount of voltage swing of
`the first output driver is adjusted based on the comparison
`between the control voltage and the reference voltage.
`
`40 Claims, 12 Drawing Sheets
`
`(54)
`
`(76)
`
`Inventors: Billy VVayne Garrett, Jr., 928 Wright
`Ave., No. 405, Mountain View, CA
`(US) 94043; John B. Dillon, deceased,
`late of Palo Alto, CA (US); by Nancy
`David Dillon, legal representative,
`PO. Box 89, Orlean, VA (US) 20128;
`Michael Tak-Kei Ching, 1283 Vicente
`Dr., No. 209, Sunnyvale, CA (US)
`94086; William F. Stonecypher, 1574
`Willowbrook Dr., San Jose, CA (US)
`95118; Andy Peng-Pui Chan, 2968
`Tantallon Ct., San Jose, CA (US)
`95132; Matthew M. Grifiin, 360
`Apricot La., Mountain View, CA (US)
`94043
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21)
`
`(22)
`
`(65)
`
`(63)
`
`(60)
`
`(51)
`
`(52)
`
`(58)
`
`Appl. No.: 09/954,561
`
`Filed:
`
`Sep. 12, 2001
`Prior Publication Data
`
`US 2002/0070771 A1 Jun. 13, 2002
`
`Related U.S. Application Data
`
`Continuation of application No. 09/559,115, filed on Apr.
`26, 2000, now Pat. No. 6,294,934, which is a continuation
`of application No. 09/141,675, filed on Aug. 27, 1998, now
`Pat. No. 6,094,075.
`Provisional application No. 60/073,353, filed on Feb. 2,
`1998, a11d provisional application No. 60/057,400, filed 011
`Aug. 29, 1997.
`
`Int. Cl.7 ................................................ .. H03B 1/00
`
`U.S. Cl.
`
`...................................... .. 327/108; 327/530
`
`Field of Search ............................ .. 326/30, 31, 33,
`326/34; 327/108, 109, 530,538
`
`RAC (Master)
`
`
`
`WW
`
`K2
`
`{M Devices per Chrrxel)
`(Slave)
`(Counter?
`UP/
`DcwnbQ
`Comp
`Q2
`
`1
`[NZ
`
`0
`
`Z
`
` 31.‘
`
`1
`
`NVIDIA 1005
`
`NVIDIA 1005
`
`

`
`US 6,556,052 B2
`Page 2
`
`Sasaki, H., et al., “A Modified Wheatstone Bride for High
`—Precision Automated Resistance Measurement,” IEEE
`Trans. on Instr. and Measurement, vol. 26, No. 2, Dec. 1987,
`pp. 947-949.
`Armstrong, David H., “Pitsfalls in Testing Digital ASIC
`Devices,” IEEE 1987 Custom Integrated Circuits Confer-
`cncc, pp. 573—578.*
`Mathews, John W and Erdelyi, Charles K., “Power Supply
`Voltages for Future VLSI,” IEEE 1986 Custom Integrated
`Circuits Conference, pp. 149-152?“
`Reynolds, C.B., “Analysis and Guidelines for High—Speed
`VLSI System Interconnections,” IEEE 1988 Custom Inte-
`grated Circuits Conference, pp. 23.5.1—23.5.4.
`Leung, Kam, “Controlled Slew Rate Output Buffer,” IEEE
`1988 Custom Integrated Circuits Conference,
`pp.
`5.5.1-5.5.4.
`
`Knight, Thomas F. Jr., and Krymm, Alexander, “A Self—Ter-
`minating LoW—Voltage Swing CMOS Output Driver,” Jour-
`nal of Solid State Circuits, vol. 23, No. 2, Apr. 1988, pp.
`457-464.
`
`Cox, Dennis T., et al., “VLSI Performance Compensation
`for Off—Chip Drivers and Clock Generation,” IEEE 1989
`Custom Integrated Circuits Conference, pp. 14.3.1-14.3.4.
`Douseki, Takakuni and Ohmori, Yasuo, “BiCMOS Circuit
`Technology for a High$peed SRAM,” IEEE Journal of
`Solid—State Circuits, vol. 23, No. 1 Feb. 1988, pp. 68-73.
`“Driver with Noise—Dependent Switching Speed Control,”
`IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug.
`1986, IBM Corporation, pp. 1243-1244.
`Biber, Alice I. “The Design of an Application Specific
`Interface Driver for a High Capacitive Load,”Masters Thesis
`at the Massachusetts Inst. of Technology, Dec. 1989.
`Raver, Norman, “Open—Loop Gain Limitations for Push
`—Pull Off—Chip Drivers,” Journal of Solid—State Circuits,
`vol. SC—22, No. 2, Apr. 1987, pp. 145-150.
`Senbon, T. and Hanabuchi, F., Instrumentation Systems:
`Fundamentals and Applications, Chapter 3: Detection and
`Covnersion of Industrial Variables; 1991, 11 pages.
`Johnson, C. and Richeh, H., “Highly Accurate Resistance
`Deviation to Frequency Converter with Programmable Sen-
`sitivity and Resolution,” IEEE vol. IM-35, No. 2, Jun. 1986,
`4 pages.
`
`* cited by examiner
`
`U.S. PATENT DOCUMENTS
`
`................ .. 307/475
`7/1987 Kobayashi
`4,680,487 A
`9/1987 Huizer
`..................... .. 307/475
`4,691,127 A
`11/1987 Sullivan et al.
`........... .. 307/270
`4,707,620 A
`12/1987 Keller et al.
`. 364/571
`4,715,003 A
`1/1988 Asano et al.
`. 307/443
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`3/1988 Evans et al.
`.............. .. 323/353
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`8/1988 Krechmery et al.
`........ .. 73/708
`4,765,188 A
`10/1988 Tanaka ............. ..
`.. 307/443
`4,779,013 A
`8/1989 Cooperman et al.
`. 307/443
`4,859,877 A
`8/1989 Takemaka ................. .. 364/200
`4,860,198 A
`1/1990 Cavaliere et al.
`......... .. 307/455
`4,894,562 A
`7/1990 Cox et al.
`......... ..
`. 307/443
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`9/1990 Trommler et al.
`..
`73/727
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`10/1990 Akamatsu et al.
`........ .. 307/448
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`12/1990 Suzuki et al.
`............. .. 307/243
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`2/1991 Hisanaga et al.
`. 323/367
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`6/1991 Gunning et al.
`. 307/475
`.
`5,023,488 A
`6/1991 Tanaka et al.
`.............. .. 73/766
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`9/1991 Coopernran et al.
`...... .. 307/475
`5,045,730 A
`9/1991
`.. 338/334
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`10/1991
`.. 307/443
`5,055,715 A
`12/1991
`307/270
`5,075,569 A
`1/1992
`{orteling .................. .. 307/530
`5,081,379 A
`3/1992 Gabara ..
`.. 307/443
`5,097,148 A
`4/1992
`{ing
`333/32
`5,107,230 A *
`5/1992 Shoji ........................ .. 307/443
`5,117,130 A *
`6/1992 Schenck ................... .. 307/443
`5,118,971 A *
`6/1992 Eller
`.. 324/601
`5,121,064 A *
`7/1992 Biber et al.
`. 307/270
`5,134,311 A *
`5,165,046 A ”‘ 11/1992 {esson ..................... .. 307/270
`5,185,538 A *
`2/1993
`{ondoh et al.
`........... .. 307/270
`5,194,765 A *
`3/1993 )unlop et al.
`. 307/443
`5,206,546 A *
`4/1993 Jsami .... ..
`.. 307/446
`5,237,214 A *
`8/1993 Jsami ...................... .. 307/446
`5,254,883 A * 10/1993
`Iorowitz et al.
`......... .. 307/443
`5,296,756 A *
`3/1994 ’atel et al.
`.... ..
`. 307/443
`5,387,824 A *
`2/1995 Michelsen
`326/83
`5,457,407 A * 10/1995 Shu et al.
`................... .. 326/30
`5,546,042 A *
`8/1996 Tedrow et al.
`............ .. 327/538
`5,568,068 A
`10/1996 om et al.
`...... ..
`326/82
`5,596,285 A
`1/1997 Marbot et al.
`326/30
`5,838,177 A
`11/1998 Keeth ....................... .. 327/108
`5,977,797 A
`11/1999 Gasparik ................... .. 326/86
`6,072,747 A
`6/2000 Yoon ................... .. 365/230.06
`OTHER PUBLICATIONS
`
`
`
`Sasaki, H., et al., “Automated Measurement System for
`1—.OMEGA. Standard Resistors Using A Modified Wheat-
`stone Bridge,” IEEE Trans. on Instr. and Measurement, vol.
`40, No. 2, Apr.’91, pp. 274-277.
`
`2
`
`

`
`U.S. Patent
`
`Apr. 29, 2003
`
`Sheet 1 of 12
`
`US 6,556,052 B2
`
`FIG. 7
`
`PRIOR ART
`
`3
`
`

`
`U.S. Patent
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`Apr. 29, 2003
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`Sheet 3 of 12
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`Us 6,556,052 B2
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`
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`
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`
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`
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`
`U.S. Patent
`
`Apr. 29, 2003
`
`Sheet 4 of 12
`
`US 6,556,052 B2
`
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`U.S. Patent
`
`Apr. 29, 2003
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`Sheet 5 of 12
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`US 6,556,052 B2
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`Apr. 29, 2003
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`U.S. Patent
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`Apr. 29, 2003
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`Sheet 9 of 12
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`Apr. 29, 2003
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`
`US 6,556,052 B2
`
`1
`SEMICONDUCTOR CONTROLLER DEVICE
`HAVING A CONTROLLED OUTPUT DRIVER
`CHARACTERISTIC
`
`This is a continuation of application Ser. No. 09/559,115,
`filed on Apr. 26, 2000 (now U.S. Pat. No. 6,294,934), which
`is a continuation of application Ser. No. 09/141,675, filed
`Aug. 27, 1998 (now U.S. Pat. No. 6,094,075), which claims
`priority to the provisional patent application Ser. No.
`60/073,353, filed Feb. 2, 1998, and the provisional patent
`application Ser. No. 60/057,400, filed Aug. 29, 1997.
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`
`The present invention relates to the field of integrated
`circuits and high-speed buses. More specifically, the present
`invention relates to a circuit for a high-speed driver and
`techniques for obtaining rapid switching speed with low
`power consumption and low noise on high-speed buses.
`2. Description of the Related Art
`To obtain rapid switching spccd on a bus with low power
`consumption and low noise, it is desirable for a current mode
`driver to set and control the current at which the driver
`operates. U.S. Pat. No. 5,254,883, assigned to the assignee
`of the present
`invention, and incorporated herein by
`reference, discusses an apparatus and method for setting and
`maintaining the operating current of a current mode driver
`for a bus. Essentially,
`for a bus with a master-slave
`architecture, there are two problems to be solved in setting
`the operating current on the bus. First, the operating current
`of the master’s current mode drivers should be properly set.
`Second, the operating current of the slave’s current mode
`drivers should be properly set. Once these currents are set,
`they are maintained at those settings despite process, voltage
`and temperature variations by circuitry in the master and
`slave devices.
`A master-slave bus architecture is discussed in the ’883
`
`patent in which a master may send data to and receive data
`from a slave. Aslave may send data to and receive data from
`a master, but not another slave. The master sets its operating
`current for its drivers and each slave sets the operating
`current for its drivers.
`
`The master employs an adjustable current sink as a driver
`for each bus line that it drives. The current sink turns on to
`
`drive the voltage on the bus line, Vow, to a voltage closer to
`ground and turns off to allow a termination resistor, Rmm, on
`the bus line to pull the bus line closer to the terminator
`voltage, Vmm. The current in the driver, Id, is set by a digital
`counter whose count is determined from a feedback circuit
`
`having a comparator. If the count is all zeros then no current
`flows in the driver and the voltage on the bus line, V0”, is
`the termination voltage, Vmm. If the count is all ones, then
`the maximum current flows in the driver and the voltage on
`term
`term '
`the bus line, VOW, equals V —Id*R
`The feedback circuit comprises a voltage reference, Vref,
`to a node voltage, V", derived from a scaled reference driver
`which receives the count from the counter. Feedback assures
`
`5
`
`10
`
`15
`
`40
`
`45
`
`the node voltage matches the reference voltage,
`that
`Vn=V,Ef. When the match occurs the reference driver has an
`output swing (i.e., change in voltage) of (V,E,,,,—V,Ef) and the
`actual output driver has a swing of 2*(Vmm—V,ef) due to the
`scaling between the reference driver and the actual output
`term
`driver. Therefore, VOW equals (V,€,m—2)*(V
`—Vref). Thus,
`by selecting a value for Vmm and Vref any size symmetric
`voltage swing about Vref may be achieved.
`The slave in the ’883 patent also employs an adjustable
`current sink as a driver for each bus line that it drives. A
`
`60
`
`65
`
`2
`counter similarly controls the value of the current in the
`driver such that the driver may swing between Vmm and
`Vm,m—Id*R,e,m, where Id is the current setting in the driver
`of the slave. However, the value in the counter is directly
`proportional to the value of an RC time constant whose
`capacitance, C, is set by the master. The master also deter-
`out
`mines whether the value of V from the driver matches Vref
`in the master. It adjusts the RC time constant so that the
`count in the counter will set a current in the driver and Vout
`
`In
`will match Vrgf. Thus VOW will equal Vmm—(Vmm—V,e
`order to produce a symmetric swing about V,,,f another step
`is required. The master should double the val11e of the RC
`timc constant which will doublc the count. This will product
`a VOW, which is equal to Vmm—2*(Vmm—VrEf).
`Maintenance of the current setting of the driver in the
`slave may be performed in a manner different from that in
`the master. In the slave, the effective R in the RC time
`constant is derived from a reference voltage and reference
`current. If due to variations in temperature or supply voltage,
`the reference current decreases then the efiective R in the RC
`time constant increases. This increases the count and the
`
`operational current setting of the driver in the slave, thus
`compensating for
`the effect. If the reference current
`increases,
`the effective R and the count decrease, again
`compensating for the change.
`While the above technique of setting and maintaining
`operating current in the master and slave bus line drives have
`met with substantial success, the techniques are not without
`certain shortcomings. For example, the technique of setting
`the current in the master requires an extra pin dedicated to
`receive the external resistor. Another shortcoming is select-
`ing the proper value of the external resistor to maintain the
`factor of two scaling between (V,e,m— n) and (Vmm—VOm).
`If the scaling is not precisely set, the output swing is not
`symmetric about Vrgf. Further, as process, voltage, or tem-
`perature variations occur, the value selected for the resistor
`may not be ideal. A further shortcoming is that an electro-
`static discharge structure (ESD) in series with the pin
`receiving the external resistor adds a variable amount of
`rcsistancc in scrics with the cxtcrnal rcsistor. This makes thc
`
`selection of the external resistance subject to variations in
`the ESD structure.
`
`Further, a shortcoming in the technique of setting the
`current in the slave is that a relatively complex algorithm
`between the slave and the master is required to correctly set
`the current in the slave. The master sets the RC time constant
`which in turn determines the count and the output value. The
`master then tests the output value to determine whether it
`matches Vrgf. If not, it increases the count and retests the
`output value. This cycle continues until a match occurs.
`However, a match of V0,” to Vref for one bus line, does not
`always insure that a match will occur on another bus line due
`to small differences in characteristics between output
`drivers, bus lines, and Vref comparison circuits.
`As can be seen, an improved output driver circuit and
`techniques for obtaining rapid switching speed with low
`power consumption and low noise is needed.
`SUMMARY OF THE INVENTION
`
`invention includes a circuit and current
`The present
`control technique to enable high-speed buses with low noise.
`This circuitry may be used in the interfacing of high-speed
`dynamic RAMs (DRAMs). Thc architecture of thc prcscnt
`invention includes the following components: an input iso-
`lation block (Isolation), an analog voltage driver (AVD), an
`input comparator, a sampling latch,
`a current control
`
`15
`15
`
`

`
`US 6,556,052 B2
`
`3
`counter, and a bitwise output driver (output driver A and
`output driver B).
`A fundamental operation of the current control mecha-
`nism is to evaluate the voltage levels V,“-, V,0w, and Vmf, and
`increment or decrement the current control counter accord-
`
`ingly to set an appropriate output level. When the current
`control circuitry is in an evaluation mode, output driver Ais
`off (not sinking current), and node BDA is at the output high
`voltage level (typically Vmm). Output driver B is active, and
`pulls node BDB to the low voltage output level. The voltage
`levels at nodes BDA and BDB are passed through the
`isolation block, and fed into the analog voltage divider. The
`analog voltage divider outputs a voltage level which is a
`weighed average of it’s input. I.e., Vo,,,=(A*V,,,-)+(B*V,ow).
`For example, in a specific case, VOm=(0.5*Vh,)+(0.5*V,oW).
`The input comparator compares V0”, and Vmf and gener-
`ates an up signal. The up signal is sampled, and used to
`increment or decrement the current control value held in the
`current control counter. By repeating this process the current
`control value will settle to a value where Vol=(Vref~
`A* Vtenn)/B ‘
`When the current control circuitry is not active, the input
`isolation block shields any interactions of the analog voltage
`divider circuitry and the output pad.
`The output driver is composed of a series of individual
`output transistors, an example of which is shown in FIG. 4.
`The number of active output transistor blocks are selected
`with control signal
`ictrl[n:O]. The width of the output
`devices may be sealed in a geometric fashion to allow
`encoding of the ictrl[n:O] signal.
`The input isolation gates may be implemented as CMOS
`pass gates, NMOS passages with boosted gate voltages,
`unity gain buffers, or operational amplifiers (op amps). The
`analog voltage divider may be implemented with a resistor
`divider, a digital-to-analog converter, or switched capacitor
`filter such as a sigma/delta modulator. The sampling latch
`may be implemented as a simple flip-flop or latch, or a series
`of sequential elements with logic to average the sampled
`value. The current control counter may be implemented as
`an up-down counter or a more sophisticated counter such as
`a saturating binary search counter.
`Other objects, features, and advantages of the present
`invention will become apparent upon consideration of the
`following detailed description and the accompanying
`drawings, in which like reference designations represent like
`features throughout the figures.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 illustrates a prior art implementation of a current
`control circuit having a master device and slave device;
`FIG. 2 shows a block diagram of current control circuitry
`in accordance with an embodiment of the present invention;
`FIG. 3 illustrates current control circuitry in accordance
`with an embodiment of the present invention;
`FIG. 4 illustrates an output driver which may be utilized
`in accordance with an embodiment of the invention;
`FIG. 5 is a detailed illustration of an implementation of
`the current control circuitry of the invention;
`FIG. 6 shows circuitry for the gxCCbst1 element of FIG.
`5, which may be used to generate a boosted voltage;
`FIGS. 7A and 7B show circuitry for an input comparator
`gxCComp of FIG. 5;
`FIG. 8 shows a resistor divider implementation for gxC-
`CDiv0 of FIG. 5; and
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`FIG. 9 shows a resistor divider implementation for gxC-
`CDiv1 of FIG. 5.
`
`FIG. 10 illustrates control and test mode logic circuitry
`that may be used in accordance with an embodiment of the
`invention.
`FIG. 11 illustrates a current control counter circuit that
`may be used in accordance with an embodiment of the
`invention.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`The present invention provides an improved apparatus
`and method of setting the current in master and slave devices
`connected to a common bus. FIG. 1 is a block diagram of a
`current control implementation with a master device (RAC)
`and a slave device (RDRAM), in accordance with the prior
`art. FIG. 1 is simplified to display only a single slave device
`RDRAM, however it should be appreciated that many slave
`devices may be used in connection with the master device
`RAC.
`
`In accordance with the prior art, the master device RAC
`has a dedicated output pin CC. The output pin CC is
`connected to a termination voltage V,E,.,,, through a resistor.
`Vmm/2. If the output driver is an ideal current source, then
`the voltage output will be the middle of the swing. This
`value is compared to Vmf and adjusted up or down accord-
`ingly.
`that
`there is a circuit
`For the slave device RDRAM,
`indirectly infers the amount to adjust the output current
`depending on variations of voltage and temperature. The
`original proper value is established by running a current
`control initialization routine which requires reading data
`back through the master device and detecting the first time
`valid ones are transmitted on the bus. This threshold is
`
`discovered and then doubled (approximately) before being
`sent to the slave device.
`
`The technique shown in FIG. 1 requires N+1 pins on the
`master device, and N pins on the slave device. The addi-
`tional pin on the master device is required for the CC
`connection shown in FIG. 1. The device of FIG. 1 also
`requires the resistor RT/2 on the printed circuit board upon
`which the master device is mounted. Unfortunately, the RT/2
`resistor may not have the desired value. The current pro-
`duced by the output transistor varies slightly as the voltage
`changes, which means there are non-ideal effects of the V-I
`characteristics of the output
`transistor, such as channel
`length modulation. So although it is desirable for the current
`control resistor to be Rm,”/2, its value is more likely about
`Rmm/2.2. The value also varies somewhat due to differences
`in process, vendor, and temperature.
`there is an input
`Internal
`to the master device RAC,
`comparator COMP. The comparator compares Vref to the
`voltage on the current control pin (CC). If the voltage
`comparison determines the output is too low, then a counter
`(Counter3) is incremented, thereby increasing the current of
`all the output drivers on the chip (during the next current
`control cycle). If the current is too high, then the counter
`(Counter3)
`is subsequently decreased. By selecting the
`proper resistor (which is difficult to do), the current control
`circuit adjusts the output drive at regular intervals to keep
`the full voltage swing of the remaining pins. This then tracks
`any drift of the transistors due to voltage or temperature
`effects, allows for different process variations chip to chip,
`and provides many similar benefits. However, selecting the
`proper resistor value to achieve this result is dillicult.
`A further technique involves using an expansion mecha-
`nism referred to as “y-channel.” However, this technique
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`the resistor value be changed (essentially
`requires that
`halved) when the module is inserted, compared to the case
`when it is not inserted. This may be achieved by adding a
`parallel current control resistor to the one on the mother-
`board which essentially changes the parallel resistance so
`that the output current is doubled. Unfortunately, the non-
`linear nature of the transistors again requires that a “special”
`resistor value be calculated in order to double the current.
`Once the proper resistor value is found, automatic tracking
`is still assured using the expansion mechanism.
`A consideration that needs to be addressed for some
`
`integrated circuits is that an electrostatic discharge (ESD)
`structure may be placed in series with the current control
`pin. This adds a variable amount of resistance, significant
`enough to change the needed external resistor value sub-
`stantially. The resistance of such an ESD structure needs to
`be accounted for.
`
`As known in the art, current control calibrations are
`performed during “quiet” times on the bus. That is,
`the
`current control calibrations are “scheduled” between activi-
`ties on the bus.
`
`FIG. 2 shows an overall diagram of an embodiment of the
`current control technique of the present invention. FIG. 3 is
`a schematic of the architecture utilized in accordance with
`the invention. FIGS. 4-8 show circuit schematics of a
`
`specific implementation of the present invention.
`The circuit of FIG. 2 includes the following components:
`an input isolation block (Isolation) 120, an analog voltage
`divider (AVD) 104, an input comparator 125, a sampling
`latch 130, a current control counter 115, and a bitwise output
`driver (output driver A 107 and output driver B 111).
`As shown in connection with FIG. 1, the prior art replied
`upon an input comparator COMP in performing its current
`control functions. The present invention also uses an input
`comparator 125 for current control functions. However,
`unlike the prior art which received a control voltage from a
`dedicated external pin connected to a printed circuit board
`mounted resistor RT/2, the present invention uses a simple
`R over R resistive divider placed between an active output
`and a nonactive output. The output of the divider circuit is
`voltage equal to (Vmm— Swing)/2. This is exactly the value
`desired to compare against Vref. It is desirable that these two
`are equal. If they are not, the current control circuit incre-
`ments or decrements the counter and tracks any output
`current variations due to changes in current drive of the
`transistors (because of temperature of VDD changes).
`The circuitry employs a voltage divider circuitry 104 on
`both the master and slave devices. As shown in FIG. 2, the
`voltage divider circuitry is connected between bus drivers A
`and B, driver 107 and 111, respectively. This circuitry is
`activated when the operating current must be set in the bus
`drivers and deactivated when the bus drivers are used in
`
`normal operation.
`Bus lines connected to the two selected drivers of the
`master are different from bus lines connected to the two
`
`the
`selected drivers of the slave device. Consequently,
`setting of an operating value of current in the master can
`proceed simultaneously with the setting of a value in the
`slave. If there are multiple slaves, each slave device may use
`bus drivers connected to a unique pair of bus lines so that the
`setting of the operating current in the several slaves may
`proceed concurrently. Preferably, all slave devices use the
`same pins.
`A counter (e.g., 115) in the master and in the slave
`determines the value of the current in the current driver as
`discussed above. The count
`in the master and slave is
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`determined by a feedback circuit which compares a voltage
`reference, Vref, to a common node voltage, VOW, which is
`derived from the voltage divider circuitry. The feedback
`circuit assures, via the counter, that Vrgf is equal to [View-
`(V,m,,—VO,,,)/(1+voltage divider ratio)] by adjusting current
`in a selected one of the drivers to which the voltage divider
`circuitry is connected. One of the drivers is left in the off
`condition, providing Vmm to the voltage divider. Thus, the
`common mode voltage swings a fixed amount equal
`to
`(V,m,,—V,€f) which is applied across the upper one of the
`resistors, R1 (FIG. 3), of the voltage divider when a resistive
`voltage divider is used. The lower one of the resistors, R2
`(FIG. 3), has g*(V,e,m—V,ef) across it, where g is the voltage
`divider ratio. I.e., g=R2/R1 where R1 is connected between
`the off driver and the center node and R2 is connected
`between the center node and the on driver. Typical values for
`R1 and R2 are approximately 10 K ohms. Thus, V0“, equals
`(_1+g,)*V,,f~g*V,€,m.
`If the resistors are equal then g equals
`renn 15
`one and V0“, equals 2*V,ef—V,e,m. For example, is V
`1.8 volts and Vre is 1.4 volts, then V0,” is 1.0 volts and the
`swing, VSM-fig, o V0“, is 0.8 volts. Also, the current in the
`output driver is now VSW,.,,g/Rtem, which equals 0.8 volts/
`28=28.6 milliamps. For example, Rm," may be about 28
`ohms. Typically, Rmm may be in the range from about 20
`ohms to about 50 ohms.
`
`When the voltage divider circuit is activated, the circuit
`itself creates a source of voltage error, caused by the current
`that flows through the voltage divider circuit from Vmm,
`through the termination resistor, through R1 and R2 and to
`the output driver which is in the on-state. This current causes
`the voltage of the driver in the off—state to be slightly less
`than Vmm, say e*V,e,m, where e is a number close to one.
`tcrm
`Specifically, e=I—[((V,€,m—VW,)N,€,m)*(R
`/(R1+R2+
`Rmm))]. This current also causes the voltage of the driver in
`the on-state to be slightly higher than VOW also by the same
`error term, say e*V,€,,,,,. Therefore, using the suggested
`resistor values, e=0.998882 and Vom=1.002, so VOW has a 2
`millivolt error.
`The feedback circuit assures that the common node of the
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`voltage divider is locked to Vref, so that the drop across R1
`is (e*V,e,m—V,ef). The voltage drop across R2 is e*V,e,m—
`term’
`Om,
`So the
`Vmf. The output voltage, V
`is 2*Vm,~e*V
`output voltage is slightly higher than its value in the absence
`term
`of the voltage divider. Vmmg is now (1+e) V —2*V,ef and
`the current
`in the output driver is VSM-,,g/R,e,,m+(Vmm—
`e*Vterm)/R,e,m=2*(V,e,m—V,ef),’R,e,m=30 milliamps, as
`before. Thus, while the output voltage is altered slightly
`when the voltage divider circuit is activated, it does not
`affect the setting of current in the output driver or the counter
`value that controls the current.
`
`Under ideal conditions the ratio of the resistors, g, is a
`precise value, such as unity. However, if some errors are
`present in the circuit, it is desirable to compensate for them
`by slightly altering the ratio. Some sources of error are
`currents into the comparator and hysteresis or offsets in the
`comparator. Another source of error is the circuitry used to
`activate the voltage divider circuitry, if the activation cir-
`cuitry is in the form of pass gates in series with R1 and R2
`of the voltage divider.
`Alternatively, the error current that flows in the divider
`circuit may be negligible compared to the amount of current
`controlled by one half of the least significant bit of the
`counter, if the resistance in the divider can be made large
`enough. The value of (Vmm—e*Vmm)/'R,e,m is approxi-
`mately 0.15 milliamps. The amount of current flowing
`though the voltage divider is [(Vmm—Vo,,,)/R1+R2+R,e,m)]
`or typically about 0.04 mA. Seven bits controlling 28.6
`milliamps makes 1/2LSB equal to 0.11 milliamps.
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`Another reason for altering the ratio, g, is that the edge
`rate for a rising signal may be different from a falling signal
`on the output of the bus driver. Altering the voltage divider
`ratio so that the swing is not symmetric about Vref may 3e
`necessary to obtain the best noise margin for receiving t1e
`signal on the bus.
`In one embodiment the relationship between the counter
`value and the current in the driver is li11ear. Such a driver
`uses binary weighted output transistor legs to adjust t1e
`current in single steps from 0 to 2" where N is the number
`of current control bits. In other embodiments there are other
`relationships between the counter value and current in tie
`driver. For example, a logarithmic relationship can be used.
`This allows more precision with smaller count values and
`less precision with larger count values.
`In another embodiment, the counter counts up until t1e
`proper current
`is reached. After
`the initial setting,
`t1e
`counter counts up or down to adjust the current in the driver.
`In another embodiment, more complex algorithms are
`employed to find the correct value for the count. One such ,
`algorithm is binary searching until a value close to t1e
`correct value is found and then co