IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`Udo Hartmann, Sascha Nerger
`In re Patent of:
`7,124,325 Attorney Docket No.: 24069-0004IP1
`U.S. Patent No.:
`October 17, 2006
`
`Issue Date:
`Appl. Serial No.: 10/680,782
`
`Filing Date:
`October 7, 2003
`
`Title:
`Method And Apparatus for Internally Trimming Output
`Drivers and Terminations in Semiconductor Devices
`
`
`
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`DECLARATION OF NICK TREDENNICK
`
`
`
`I, Nick Tredennick, declare as follows:
`
`I.
`
`Introduction
`
`1.
`
`I am making this declaration at the request of Petitioner NVIDIA
`
`Corporation in the matter of Inter Partes Review of U.S. Patent No. 7,124,325
`
`(“the ’325 patent”).
`
`
`
`1
`
`NVIDIA 1002
`
`
`
`
`Udo Hartmann, Sascha Nerger
`In re Patent of:
`7,124,325 Attorney Docket No.: 24069-0004IP1
`U.S. Patent No.:
`October 17, 2006
`
`Issue Date:
`Appl. Serial No.: 10/680,782
`
`Filing Date:
`October 7, 2003
`
`Title:
`Method And Apparatus for Internally Trimming Output
`Drivers and Terminations in Semiconductor Devices
`
`
`
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`DECLARATION OF NICK TREDENNICK
`
`
`
`I, Nick Tredennick, declare as follows:
`
`I.
`
`Introduction
`
`1.
`
`I am making this declaration at the request of Petitioner NVIDIA
`
`Corporation in the matter of Inter Partes Review of U.S. Patent No. 7,124,325
`
`(“the ’325 patent”).
`
`
`
`1
`
`NVIDIA 1002
`
`
`
`2.
`
` I am being compensated for my work. My compensation does not
`
`depend on the outcome of this proceeding.
`
`3.
`
` I have been asked to consider whether certain references disclose or
`
`render obvious the claims of the ’325 Patent, either alone or in combination with
`
`each other.
`
`4.
`
` I have been advised that a patent claim may be invalid as obvious if
`
`the differences between the subject matter patented and the prior art are such that
`
`the subject matter as a whole would have been obvious at the time of the invention
`
`to a person having ordinary skill in the art. I have also been advised that several
`
`factual inquiries underlie a determination of obviousness. These inquiries include
`
`the scope and content of the prior art, the level of ordinary skill in the field of the
`
`invention, the differences between the claimed invention and the prior art, and any
`
`objective evidence of non-obviousness.
`
`5.
`
` I have been advised that objective evidence of non-obviousness
`
`directly attributable to the claimed invention, known as “secondary considerations
`
`of non-obviousness,” may include commercial success, satisfaction of a long-felt
`
`but unsolved need, failure of others, copying, skepticism or disbelief before the
`
`invention, and unexpected results. I am not aware of any such objective evidence
`
`of non-obviousness that is directly attributable to the subject matter claimed in the
`
`’325 patent at this time.
`
`
`
`2
`
`
`
`6.
`
` In addition, I have been advised that the law requires a “common
`
`sense” approach of examining whether the claimed invention is obvious to a person
`
`skilled in the art. For example, I have been advised that combining familiar
`
`elements according to known methods is likely to be obvious when it does no more
`
`than yield predictable results. I have further been advised that this is especially true
`
`in instances where there are a limited numbers of possible solutions to technical
`
`problems or challenges.
`
`7.
`
` I have been informed that claims 1-20 of the ’325 Patent are subject
`
`to this inter partes review.
`
`II. Materials Reviewed
`
`8.
`
` In forming the opinions, I express below, I considered my own
`
`knowledge of the art and at least the following references:
`
`1001
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`
`
`
`
`U.S. Patent No. 7,124,325 (“the ’325 patent”)
`
`U.S. Patent No. 7,000,160 to Tanaka et al. (“Tanaka”)
`
`U.S. Patent No. 6,643,180 to Ikehashi et al. (“Ikehashi”)
`
`U.S. Patent No. 6,556,052 to Garrett et al. (“Garrett”)
`
`U.S. Patent No. 5,844,913 to Hassoun et al. (“Hassoun”)
`
`U.S. Patent No. 5,991,221 to Ishikawa et al. (“Ishikawa”)
`
`3
`
`
`
`III. Qualifications
`
`9.
`
` I summarize my relevant knowledge and experience below. My
`
`Curriculum Vitae contains additional information and is attached as Exhibit A.
`
`10.
`
`I have a background in electrical engineering that is primarily in the
`
`areas of logic design and microprocessor design and I have completed college
`
`work through a Ph.D. in electrical engineering. I worked in industry at Motorola
`
`and IBM designing microprocessors and at Altera in programmable logic. I taught
`
`electrical and computer engineering courses at the University of California,
`
`Berkeley and at the University of Texas, Austin. I wrote a graduate-level textbook,
`
`Microprocessor Logic Design. I spent twelve years as a member of the Army
`
`Science Board and sixteen years as an Aerospace Engineering Duty Officer for
`
`Naval Air Systems Command, Navy Reserve, studying military applications of
`
`science and technology.
`
`11.
`
`I was a senior design engineer for Motorola, where I did the logic
`
`design and microcode for the MC68000 microprocessor, which was the brains of
`
`the original Apple Macintosh computers. I was a research staff member at IBM’s
`
`T.J. Watson Research Center, where I did the logic design and microcode for the
`
`Micro/370 microprocessor. I was founder and director of engineering for Nexgen
`
`Microsystems, where I hired and managed the engineering groups that designed
`
`Nexgen’s Intel-compatible x86 processor. I founded and managed Tredennick,
`
`
`
`4
`
`
`
`Inc., a logic design and consulting company for a number of years. I was also
`
`chief scientist at Altera, a programmable logic company. I have nine patents from
`
`work at these companies.
`
`12. For the past three years, I have been at a startup company, Jonetix,
`
`working in the area of cryptography and online transaction security. I am a named
`
`inventor on more than a dozen patent applications and provisional applications
`
`filed for this work.
`
`IV. Person of Ordinary Skill in the Art and State of The Art
`
`13.
`
` In my opinion, a person of ordinary skill in the art as of the time of
`
`the ’325 Patent would have a Bachelor’s degree in Electrical Engineering and at
`
`least 2 years of experience working in the field of semiconductor logic design. I
`
`believe this to be a reasonable statement of the level of ordinary skill in the art for
`
`the patent and claims at issue. I also believe that I was one of ordinary skill in the
`
`art at the time the ’325 Patent was filed.
`
`14.
`
` The opinions that I provide in this declaration are consistent with the
`
`knowledge and experience of one of ordinary skill in the art at the priority date of
`
`the ’325 Patent.
`
`15.
`
` At the time of the ’325 Patent’s priority date, those of ordinary skill
`
`in the art recognized that trimming an interface device (based on a value measured
`
`on the interface device) could be done within the semiconductor device. This
`
`
`
`5
`
`
`
`technology for calibration or trimming of these values was well known in the
`
`industry and was disclosed in various references.
`
`V. Overview of the ’325 Patent
`
`16. The ’325 patent discusses calibrating or “trimming” interface devices
`
`within a semiconductor. Ex. 1001, Abstract. The patent says these interface
`
`devices include output drivers and terminations. Id., 3:18-21. Output drivers and
`
`terminations have parameters that control reading and writing from a data bus. Id.,
`
`1:36-41. As the speed of data transmission increases on a bus, for example in
`
`DRAM, the patent states that “narrower tolerances for the interface parameters” are
`
`required to “maintain the integrity of the data signals transmitted to the data bus.”
`
`Id. One such interface parameter is stated to be “the impedance of the output
`
`drivers…which a semiconductor device uses to effect a write access to the data
`
`bus.” Id., 1:42-54. If trimmed or calibrated correctly, it enables a higher data
`
`transmission rate. Id. In the case of terminations, “which terminate the data bus
`
`locally” and prevent reflections, greater precision allows for “a higher maximum
`
`data transmission rate is made possible.” Id., 1:55-62.
`
`17. The manufacturing process and temperature variations during
`
`operation cause variations in the interface devices. Id., 1:63-2:5. Before the ’325
`
`patent, methods of trimming existed in the prior art to trim interface devices
`
`“before or during the initial startup…or repeatedly during [] operation.” Id. 2:6-17.
`
`
`
`6
`
`
`
`The interface devices have settable “control elements…in the form of switchable
`
`impedances whose respective value can be programmed” using a value stored in a
`
`“trimming register.” Id.
`
`18. The ’325 patent states that a typical setup in the prior art used a “test
`
`apparatus” with a current source and a voltmeter connected to the device under
`
`test. Id., 2:30-50. To start, a variable impedance in the interface device is set to a
`
`minimum value. Id. According to the ’325 patent, a “measurement current” is
`
`“impress[ed]” on the device. Id. The voltmeter measures the resulting voltage and
`
`the test device compares the measured voltage and the nominal voltage. Id. While
`
`the measured voltage is less than the nominal voltage, the impedance is
`
`incremented. Id. When the measured voltage is higher, the value corresponding to
`
`the corresponding impedance level “is stored in a suitable manner for further use.”
`
`Id. Figure 1 illustrates the prior art approach:
`
`
`
`7
`
`
`
`
`19. The “relatively low throughput of test pieces,” “the time required for
`
`evaluating measurement and trimming data,” preparing test programs for the test
`
`apparatus, and the contact resistance from contact needles are identified as
`
`drawbacks to the approach. Id., 2:51-3:9.
`
`20. The ’325 patent claims that it solves these issues by including the
`
`trimming or calibration unit “within the semiconductor device” rather than on the
`
`test device. Id., 3:53-67. The patent states that this permits more devices to “be
`
`tested and trimmed simultaneously.” Id. It also is said to lessen the difficulties
`
`associated with the test apparatus’ test programs and the contact resistance issues
`
`(because the device under test itself does the measurement). Id., 4:1-10, 54-65.
`
`
`
`8
`
`
`
`This approach, is shown in Figure 3 (below) that indicates the “trimming unit” was
`
`moved into the semiconductor device:
`
`
`21. With reference to Figure 3 above, trimming unit 5 is connected to the
`
`interface devices 10a-10d, and to trimming registers 14. Id., Fig. 3, 8:4-11.
`
`Trimming registers 14 are connected to settable impedances in the interface
`
`devices, which are the settable control elements. Id. The trimming unit compares
`
`measurement voltage (UM) with nominal voltage (US). Id., 8:12-22. If the
`
`measured voltage is less than the nominal voltage, the trimming unit increases the
`
`
`
`9
`
`
`
`value stored in trimming registers 14. Id. That value initially starts at a minimum
`
`level Id. When they are within a “tolerable discrepancy,” the calibration or
`
`trimming is complete and the value is stored in nonvolatile memory or sent to the
`
`test device. Id., 8:12-33.
`
`22. The trimming unit is shown in Figure 4 (below). Comparator unit 56
`
`compares measured voltage (UM) with nominal voltage (US). Id., 8:39-59. Based
`
`on that comparison, logic unit 57 either increments trimming registers 14 or it
`
`stores the current trimming value in the nonvolatile memory unit 59. Id.
`
`
`VI. Certain References Render Obvious Claims 1-20 of the ’325 Patent
`
` Claims 1-20 are obvious based on Tanaka in view of Ikehashi
`
`23.
`
`I have been advised, and my understanding is, that Tanaka is eligible
`
`to serve as prior art for the ’325 Patent under 35 U.S.C. § 102(e) because it was
`10
`
`
`
`
`
`filed before the invention of the ’325 patent on February 27, 2002. I have also
`
`been advised, and my understanding is, that Ikehashi is eligible to serve as prior art
`
`for the ’325 Patent under 35 U.S.C. § 102(b). Ikehashi was published on April 25,
`
`2002, more than one year before the priority date of the ’325 patent.
`
`24.
`
`In my opinion, one of ordinary skill in the art would find every
`
`limitation of claims 1-20 of the ’325 patent to have been disclosed (taught) or
`
`rendered obvious by the disclosure of Tanaka in view of Ikehashi.
`
`25. Tanaka and Ikehashi teach techniques for trimming semiconductor
`
`interface devices. Tanaka, 1:5-12; Ikehashi, 1:15-23, 11:7-12. Each of them
`
`discloses trimming in a very similar manner, using a variable impedance and a
`
`feedback circuit that repeatedly adjusts the trimming value. See discussion of
`
`claim 14.3 below. A POSITA would have been motivated to modify the teachings
`
`of Tanaka to further implement the teachings of Ikehashi.
`
`26.
`
`It would have been obvious to modify Tanaka with Ikehashi because
`
`it involves using known solutions to improve similar systems and methods in the
`
`same way. For example, they each disclose similar trimming units that measure a
`
`voltage and compare it with a nominal voltage to arrive at the correct trimming
`
`value. See discussion of claim 14 below. One reason a POSITA would have been
`
`motivated to combine Tanaka and Ikehashi is that Ikehashi discloses a more direct
`
`feedback mechanism than Tanaka. Compare Tanaka, Fig. 4 with Ikehashi, Fig. 16.
`
`
`
`11
`
`
`
`For instance, Ikehashi has a simpler feedback mechanism that directly connects the
`
`comparator’s inverted output with the control logic, which a POSITA would have
`
`recognized is a more streamlined design than using a decision register and a bus.
`
`Id. This could result in size and cost savings, which are always concerns when
`
`designing semiconductor devices. In addition, both references use the same
`
`general algorithm to calculate a trimming value, so a POSITA would have
`
`naturally looked to combine teachings or features from Ikehashi into the system
`
`discussed in Tanaka.
`
`27. Additionally, a POSITA would have been motivated to combine
`
`Tanaka with Ikehashi for the additional benefits of including a monitor output
`
`terminal for the voltage output that the test apparatus could use. This would be
`
`helpful in monitoring the output voltage and the trimming process generally while
`
`the device is under test. It could also facilitate storing the relevant value to
`
`nonvolatile memory. Tanaka discloses monitor outputs and certain interactions
`
`between the device under test and the test apparatus. See, e.g., Claim 5 below. A
`
`POSITA would have recognized the added benefits that would arise from
`
`combining the disclosure of Ikehashi, which teaches a monitor output terminal in a
`
`different part of the circuit than Tanaka. Ikehashi, Fig. 16. Combining the two
`
`references could have also yielded benefits from the simpler feedback design of
`
`Ikehashi, thereby potentially reducing the cost and size of the circuit. As a result,
`
`
`
`12
`
`
`
`it would have been obvious to combine Tanaka and Ikehashi. A POSITA would
`
`have recognized that the resulting combination of Tanaka and Ikehashi would add
`
`Ikehashi’s more direct feedback for the trimming unit that connects the
`
`comparator’s output to the control logic and connects the control logic with the
`
`trimming register, to Tanaka’s disclosure of a test apparatus, device under test,
`
`trimming unit, trimming register, and interface device. A POSITA would also
`
`have understood the combination to permit a monitor output of Tanaka’s
`
`measurement voltage based on Ikehashi’s monitor output of the voltage output. A
`
`POSITA would have recognized additional benefits by obtaining additional data
`
`relating to a different part of the circuit under test.
`
`28. Claim 14 is the broadest claim of the ’325 patent. Because the
`
`petition begins with claim 14, I will also begin with claim 14 and then proceed to
`
`the discussion of the other claims.
`
`Claim 14
`
`a. A semiconductor device comprising:
`
`29.
`
`In my opinion, Tanaka and Ikehashi each disclose a semiconductor
`
`device. Tanaka, Abstract (“A semiconductor integrated circuit…”), Fig. 25;
`
`Ikehashi, Abstract (“a method of testing a nonvolatile semiconductor memory
`
`integrated on a semiconductor chip”), Fig. 1.
`
`b. at least one interface device having a settable control
`element;
`
`
`
`13
`
`
`
`30.
`
`In my opinion, Tanaka discloses a semiconductor device having at
`
`least one interface device that has a settable control element. Flash memory chip
`
`5A (in Figure 25 below) contains timing controller 50 (“TCNT”) that is connected
`
`to boosting circuit 6A and voltage trimming circuit 7A. The timing controller
`
`receives memory commands and “generates internal timing signals and operating
`
`voltages such as a write voltage and an erase voltage.” Id., 17:23-36. “The
`
`operating voltages including the write voltage and erase voltage are generated by
`
`using the high voltage Vpp generated by the boosting circuit 6A.” Id.; see also id.
`
`8:49-59, Fig. 25:
`
`
`
`
`
`14
`
`
`
`31. The interface device comprises timing controller 50 and boosting
`
`circuit 6. As shown in Figure 4 (below),1 boosting circuit 6 has a settable control
`
`element, including voltage dividing circuit 62, selector 63, and decoder 65. Id.,
`
`10:51-11:5. Using a value in the trimming register, these elements decode the
`
`value and set the variable impedance circuit (62). The output of the boosting
`
`circuit is Vpp, which is used by the timing controller.
`
`
`In my opinion, Ikehashi also discloses a semiconductor device that
`
`32.
`
`has at least one interface device having a settable control element. Ikehashi,
`
`Abstract (“a method of testing a nonvolatile semiconductor memory integrated on
`
`
`
` 1
`
` Figure 4 of Tanaka is referenced for the trimming and boosting circuits. Figure
`
`26 also references the same trimming and boosting circuits, but refers to the
`
`explanation of Figure 4. Tanaka, 17:37-40.
`
`
`
`15
`
`
`
`a semiconductor chip”). As shown in Figure 1, Ikehashi further discloses a
`
`semiconductor device with a plurality of interface devices (control logic that
`
`manages buffers and registers in order to read from and write to memory):
`
`
`Id., Fig. 1; 8:60-10:18. The interface device also includes part of voltage generator
`
`circuit 20, which “generates a variety of voltages for use in chips. This [sic]
`
`voltages include Vref (reference voltage), Vpgm (writing voltage), an internal fall
`
`voltage (Vdd), an erasure voltage (Verase), a non-selected cell word line voltage
`
`
`
`16
`
`
`
`(Vread) supplied to a non-selected cell word line and the like.” Id., 9:51-56. One
`
`example is shown in Figure 16 related to the read voltage:2
`
`
`33. The interface device includes Vread charge pump 71, settable resistor
`
`73, and resistor 74. Together they help generate the read voltage. Id. 16:11-18.
`
`“[V]ariable resistor circuit 73” is settable based on the trimming process. Id., 16:3-
`
`38.
`
`c. a trimming register connected to said control element;
`and
`
`
`
` 2
`
` The citations here focus on the trimming circuit for the read voltage Vread, but
`
`the reference discloses other similar circuits and techniques for trimming other
`
`memory interface voltages.
`
`
`
`17
`
`
`
`34.
`
`In my opinion, Tanaka discloses a trimming register connected to the
`
`control element. The trimming register 66 is connected to the control element 62
`
`with the circuitry that is used to set the control element (decoder 65 and selector
`
`63):
`
`
`In my opinion, Ikehashi also discloses this element. In Ikehashi,
`
`35.
`
`trimming data register 21 is connected to variable resistor circuit 73. Ikehashi, Fig.
`
`16:
`
`
`
`18
`
`
`
`
`d. a trimming unit for writing to said trimming register
`based on a measured variable detected on said interface
`device;
`
`36.
`
`In my opinion, Tanaka discloses a trimming unit in the semiconductor
`
`device for writing to the trimming register based on a measured variable detected
`
`on the interface device. The “Voltage Trimming Circuit” is the trimming unit and
`
`is identified in Figures 1 (below) and 25. The voltage trimming circuit “finely
`
`adjusts the write voltage obtained by the boosting circuit.” Id., 8:57-59.
`
`
`
`19
`
`
`
`
`37. The trimming unit includes comparison circuit 70, decision register
`
`71, and the trimming program in the CPU that manages the trimming process. Id.,
`
`11:6-57, Fig. 4:
`
`
`
`20
`
`
`
`
`38. As discussed above, the interface device includes the boosting circuit
`
`disclosed by Tanaka. The boosting circuit outputs voltage, Vpp, which is
`
`measured by comparison circuit 70 of the trimming unit. Tanaka, Fig. 4, 11:9-12.
`
`Vpp is the claimed “measured variable” or “measurement voltage.” Comparison
`
`circuit 70 is used to compare the measurement voltage (“Vpp”) with a nominal
`
`voltage (“reference voltage” or “Vref”). Tanaka, 11:6-12 (“To enable the high
`
`voltage Vpp to be obtained at a target value by the above-described fine
`
`adjustment, a comparison circuit 70, which operates as a decision circuit, and a
`
`decision register 71 are provided. The comparison circuit 70 compares an expected
`
`voltage Vref supplied as a comparative voltage from an external evaluation device
`
`18 and the voltage Vpp generated by the boosting section 60.”), Abstract (“Each
`
`
`
`21
`
`
`
`LSI incorporates a comparison circuit comparing an expected voltage value and a
`
`boosted voltage generated in itself.”); Fig. 4:
`
`
`39. Tanaka also discloses writing to a trimming register based on a
`
`measured variable, using the difference between the measurement voltage (Vpp)
`
`and the nominal voltage (Vref). Decision register 71 stores the result of the
`
`comparison of the reference voltage and Vpp. Tanaka, 11:6-21. Using that result,
`
`the CPU’s trimming program will do one of two things. If the reference voltage is
`
`greater than Vpp, the program will “updat[e] the control data in the trimming
`
`register 66,” which the boosting circuit will then decode and use to change the
`
`variable impedance shown in Figure 4:
`
`
`
`22
`
`
`
`
`Id., Fig. 4, 2:40-65, 10:58-11:5, 11:36-57. The change to voltage dividing circuit
`
`62 causes the value of Vpp to change. Id., 10:58-11:5. The new value is again
`
`compared by comparison circuit 70 and the process repeats. Id., 11:27-57, Fig. 5.
`
`When the voltages are equal to a certain tolerance, the trimming stops iterating,
`
`and the value in the trimming register reflects the “trimming value at which the
`
`measurement voltage matches the nominal voltage” as recited by claim 1. Id.,
`
`11:27-57, Fig. 5:
`
`
`
`23
`
`
`
`
`40. After this process completes, the trimming value is available in
`
`trimming register 66, and can be either used or stored elsewhere (for example,
`
`stored in flash memory). Tanaka, 11:66-12:9; 18:54-63.
`
`41.
`
`In my opinion, Ikehashi also discloses this element. Ikehashi, 1:15-23
`
`(“The present invention relates to a semiconductor device…being capable of
`
`adjusting values of a pulse width of the pulse generated by these circuits and a
`
`value of an internal voltage. More particularly, the present invention relates to a
`
`
`
`24
`
`
`
`nonvolatile semiconductor memory that internally generates a reference voltage, a
`
`writing voltage, a [sic] erasure voltage, and a readout voltage.”), 15:41-16:48, Figs.
`
`3, 13, 16, 11:7-12 (“This step carries out…trimming of a value of a voltage
`
`generated by the internal voltage generator circuit 20. The voltages to be trimmed
`
`here include: a reference voltage Vref, an internal fall voltage Vdd, and a non-
`
`selected cell work [sic] line voltage Vread.”). The trimming unit consists of
`
`comparator 75, inverter 76, and control circuit 68:
`
`
`Ikehashi further discloses acquiring a “measured variable” or
`
`42.
`
`measurement voltage. Voltage “VMON” is the measurement voltage, that is
`
`acquired from connecting Vread with the voltage divider circuit formed by variable
`
`resistor circuit 73 and resistor 74. Id., 16:11-24, Fig. 16; see also id., 15:47-50.
`
`Comparator 75 compares measurement voltage “VMON” to Vref, which is a
`
`
`
`25
`
`
`
`nominal voltage or reference voltage. Ikehashi, 16:11-20 (“…The above divided
`
`voltage VMON is compared with the reference voltage Vref by a comparator 75.”);
`
`see also id., 15:47-50, Fig. 16:
`
`
`Inverter 76 inverts the output of comparator 75 and sends it to the
`
`43.
`
`trimming unit’s control logic. Ikehashi, 16:11-24, Fig. 16 (see above). This
`
`“flag,” causes the control circuit to increment the value in the trimming data
`
`register, or else reset the trimming data register. Id. The trimming data register
`
`holds the trimming data used to set variable resistor circuit 73. Id., 15:23-36.
`
`e. said trimming unit connected to said interface device and
`said trimming register.
`
`44.
`
`45.
`
`See Section VI.A, Claim 14.b-d above.
`
`In my opinion, the trimming unit of Tanaka (comparison circuit 70,
`
`decision register 71, and the trimming program) is connected to the trimming
`
`
`
`26
`
`
`
`register and the boosting circuit via the bus. Tanaka, Fig. 4 (reproduced below). It
`
`also connects to the boosting circuit via the node with Vpp that connects to settable
`
`control element (62) and boosting section 60. Id.
`
`
`46. Figure 25 shows that voltage trimming circuit 7A is connected to
`
`timing controller 50 (part of the interface device):
`
`
`
`27
`
`
`
`
`In my opinion, Ikehashi also discloses that the trimming unit is
`
`47.
`
`connected to both the interface device and the trimming register. The interface
`
`device, trimming unit, and trimming register were identified above. Figure 16
`
`below illustrates that the trimming unit (red) is connected to the trimming register
`
`(green) and part of the interface device (blue):
`
`
`
`28
`
`
`
`
`
`Claim 15
`
`a. The semiconductor device according to claim 14, further
`comprising: a monitor output for transmitting a value
`for said control element to a test apparatus;
`
`48.
`
`See Section VI.A, claim 6 below.
`
`b. said value being a measured variable and/or a trimming
`value; and
`
`49.
`
`See Section VI.A, claims 5-6 below.
`
`c. said value being ascertained by said trimming unit.
`
`50.
`
`See Section VI.A, claim 14.d above.
`
`Claim 16: The semiconductor device according to claim 14,
`wherein said trimming unit includes a reference voltage device
`and a voltage divider for producing a nominal voltage.
`
`
`
`29
`
`
`
`51. As discussed above, each limitation of claim 14 is disclosed or
`
`rendered obvious by Tanaka in view of Ikehashi. In my opinion, the additional
`
`element of claim 16 would have been obvious to a POSITA. Voltage dividers
`
`were very commonly used in the art to produce a reference or “nominal” voltage.
`
`A POSITA would have understood this use of voltage dividers and would know
`
`that in order to generate a nominal voltage in a reliable way (for example,
`
`minimizing variations due to manufacturing or temperature), a voltage divider
`
`could be used. Garrett, a reference used in Petitioner’s other grounds, confirms
`
`that such a use of voltage dividers was well known in the art. Garrett, 8:10-13
`
`(stating that the nominal voltage “may also be generated with…a voltage divider of
`
`Vdd or another voltage supply.”).
`
`Claim 17
`
`a. The semiconductor device according to claim 14,
`wherein: said trimming unit has a comparator unit for
`providing an output signal obtained by comparing a
`nominal voltage with a measurement voltage produced in
`said interface device; and
`
`52.
`
`See Section VI.A, claim 14.d above.
`
`b. said trimming unit has a logic unit for writing to said
`trimming register based on said output signal from said
`comparator unit.
`
`53.
`
`See Section VI.A, claim 14.d above.
`
`
`
`30
`
`
`
`Claim 18: The semiconductor device according to claim 14,
`wherein: said trimming unit has a nonvolatile memory unit being
`programmed based on a trimming value.
`
`54.
`
`See Section VI.A, claim 2 below.
`
`Claim 19: The semiconductor device according to claim 18,
`wherein: said memory unit is configured for directly controlling
`said control element.
`
`55.
`
`See Section VI.A, claims 2 and 7 below.
`
`Claim 20: The semiconductor device according to claim 18,
`wherein: said memory unit is configured for loading said
`trimming register.
`
`56.
`
`See Section VI.A, claim 3 below.
`
`Claim 1
`
`a. A method for trimming interface devices, which
`comprises
`
`57.
`
`In my opinion, Tanaka discloses an invention that “relates to a
`
`trimming technique for finely adjusting a voltage… and to a testing method of
`
`performing trimming on such a semiconductor integrated circuit.” Tanaka, 1:5-12.
`
`These “programming voltage[s]” affect “the width of write pulses.” Id., 1:13-21,
`
`41-49, 8:57-59 (“The voltage trimming circuit 7 finely adjusts the write voltage”),
`
`17:23-36 (“the timing controller 50 generates internal timing signals and operating
`
`voltages such as a write voltage and an erase voltage according to supplied control
`
`information and bus commands on the basis of control procedures for performing a
`
`read operation, an erase operation, a write operation, etc., and supplies the
`
`
`
`31
`
`
`
`generated signal and voltages to the components of the flash memory.”), Figs. 4-5
`
`(showing trimming unit), 25 (showing interface device).
`
`58.
`
`In my opinion, Ikehashi also discloses trimming interface devices,
`
`including values related to read, write, and reference voltages used by controllers
`
`in flash memory. Ikehashi, 1:15-23 (“The present invention relates to a
`
`semiconductor device…being capable of adjusting values of a pulse width of the
`
`pulse generated by these circuits and a value of an internal voltage. More
`
`particularly, the present invention relates to a nonvolatile semiconductor memory
`
`that internally generates a reference voltage, a writing voltage, a [sic] erasure
`
`voltage, and a readout voltage.”), 15:41-16:48, Figs. 3, 13, 16, 11:7-12 (“This step
`
`carries out…trimming of a value of a voltage generated by the internal voltage
`
`generator circuit 20. The voltages to be trimmed here include: a reference voltage
`
`Vref, an internal fall voltage Vdd, and a non-selected cell work [sic] line voltage
`
`Vread.”).
`
`b. providing a semiconductor device having a plurality of
`interface devices and providing each one of the plurality
`of interface devices with a settable control element;
`
`59.
`
`See Section VI.A, claim 14.b above.
`
`c. providing a test apparatus having a current source;
`
`60.
`
`In my opinion, Tanaka discloses an evaluation device 18, which is a
`
`test device that provides a constant current through a resistor (Tanaka, 13:2-5):
`
`
`
`32
`
`
`
`
`Tanaka also states that “a trimmed value which coincides with a voltage or a
`
`current of an expected value can be obtained by only supplying the expected
`
`voltage or current value externally and executing a predetermined trimming
`
`program.” Id., 19:6-9.
`
`d. connecting the current source in the test apparatus to an
`interface connection on the semiconductor device, the
`interface connection being connected to one of the
`plurality of interface devices;
`
`61.
`
`In my opinion, Tanaka discloses connecting the current source in the
`
`test apparatus to an interface connection on the semiconductor device, the interface
`
`connection being connected to one of the plurality of interface devices. Figure 12
`
`(reproduced above) shows the current source is connected to a pin on the
`
`semiconductor device labeled “Pad,” which is an interface connection. Tanaka,
`
`
`
`33
`
`
`
`13:2-5. Tanaka references supplying an expected voltage or current value
`
`externally. Id., 19:6-9. The Pad interface connection is also connected to the
`
`interface devices as shown above and in Figures 4 and 25.
`
`62. Regarding Figure 12, Tanaka states that “[t]he same trimming
`
`procedure as that in the case of the arrangement shown in Fig. 4 [for voltage
`
`trimming] is used to obtain the same effect.” Tanaka, 12:57-13:19; see also id.,
`
`19:6-9. A POSITA would have readily combined the teachings of each
`
`embodiment based on this statement.
`
`e. controlling a measurement current produced by the
`current source and setting the control element of the one
`of the plurality of interface devices to an initial value;
`
`63.
`
`In my opinion, Tanaka discloses controlling a measurement current
`
`produced by the current source by directing “the current through the dummy MOS
`
`transistor 74” to produce a voltage. Id., 13:6-17. A POSITA would have also
`
`recognized this limitation to be met by the disclosures of an externally provided
`
`reference voltage (Tanaka, 11:32-39, 19:6-9), because it was well known that a
`
`measurement current could be provided using a reference voltage and a resistor as
`
`disclosed in Tanaka. Tanaka also discloses setting the variable impedance to an
`
`initial value. It is initially set to a minimum value. Tanaka 11:36-39; Fig. 5 (S5):
`
`
`
`34
`
`
`
`
`f. providing a trimming unit in the semiconductor device;
`
`64.
`
`See Section VI.A, claim 14.d above.
`
`g. using the trimming unit to acquire a measurement
`voltage produced by the measurement current in the one
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