US0074l5530Cl
`
`(12) INTER PARTES REEXAMINATION CERTIFICATE (671st)
`United States Patent
`Fallon
`
`(10) Number:
`US 7,415,530 C1
`(45) Certificate Issued:
`Aug. 16,2013
`
`(54) SYSTEM AND METHODS FOR
`ACCELERATED DATA STORAGE AND
`RETRIEVAL
`
`(75)
`
`Inventor:
`
`James J Fallon, Armonk, NY (US)
`
`(73) Assignee: Realtime Data LLC, New York, NY
`(US)
`
`Reexamination Request:
`No. 95/001,927, Mar. 2, 2012
`
`Reexamination Certificate for:
`Patent No.:
`7,415,530
`Issued:
`Aug. 19, 2008
`Appl. No.2
`11/553,426
`Filed:
`Oct. 26, 2006
`
`Certificate of Correction issued Dec. 2, 2008
`
`Related U.S. Application Data
`
`(63) Continuation of application No. 10/628,795, filed on
`Jul. 28, 2003, now Pat. No. 7,130,913, which is a
`continuation of application No. 09/266,394, filed on
`Mar. 11. 1999, now Pat. No. 6,601,104.
`
`(2006.01)
`
`Int. Cl.
`G06F 15/16
`U.S. Cl.
`USPC ........................................................ .. 709/231
`Field of Classification Search
`None
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`To View the complete listing of prior art documents cited
`during the proceeding for Reexamination Control Number
`95/001,927, please refer to the USPTO’s public Patent
`Application lnfomiation Retrieval (PAIR) system under the
`Display References tab.
`Primary Examiner — Mark Sager
`(57)
`ABSTRACT
`Systems and methods for providing accelerated data storage
`and retrieval utilizing lossless data compression and decom-
`pression. A data storage accelerator includes one or a plurality
`of l1igl1 speed data compression encoders that are configured
`to simultaneously or sequentially losslessly compress data at
`a rate equivalent to or faster than the transmission rate of an
`input data stream. The compressed data is subsequently
`stored in a target memory or other storage device whose input
`data storage bandwidth is lower than the original input data
`stream bandwidth. Similarly, a data retrieval accelerator
`includes one or a plurality of high speed data decompression
`decoders that are configured to simultaneously or sequen-
`tially losslessly decompress data at a rate equivalent to or
`faster than the input data stream from the target memory or
`storage device. The decompressed data is then output at rate
`data that is greater than the output rate from the target
`memory or data storage device. The data storage and retrieval
`accelerator method and system may employed:
`in a disk
`storage adapter to reduce the time required to store and
`retrieve data from computer to disk; in conjunction with ran-
`dom access memory to reduce the time required to store and
`retrieve data from random access memory; in a display con-
`troller to reduce the time required to send display data to the
`display controller or processor; and/or in an input/output
`controller to reduce the time required to store, retrieve, or
`transmit data.
`
`Determlne
`Compresslnn Ratio
`and Bandmdths
`
`Input Bandwidth er
`compresslun or
`
`1
`
`@
`
`Receive Next Date
`Block From Input
`stream
`
`1 5:.
`
`Veritas Techs. LLC
`Exhibit 1011
`Page 001
`
`

`
`US 7,415,530 C1
`
`1
`INTER PARTES
`REEXAMINATION CERTIFICATE
`ISSUED UNDER 35 U.S.C. 316
`
`THE PAT,JN1 IS IIER ‘BY AM ‘ND D AS
`INDICATED BELOW.
`
`l\/latter enclosed in heavy brackets [ ] appeared in the
`patent, but has been deleted and is no longer a part of the
`patent; matter printed in italics indicates additions made
`to the patent.
`
`AS A RESULT OF REEXAMINATION, IT HAS BEEN
`DETERMINED THAT;
`
`The patentability ofclaims 1. 2. 16-21 and 23 is confirmed.
`New claims 24-26 are added and determined to be
`patentable.
`Claims 3-15 and 22 were not reexamined.
`24. A system comprising:
`a memory device; and
`a data acceleratoi; wherein said data accelerator is
`coupled to said memory device, a data stream is received
`by said data accelerator in received form, wherein a '
`bandwidth of the received data stream is determined.
`said data stream includes afirst data bloclcand a second
`data block, said data stream is compressed by said data
`
`2
`accelerator to provide a compressed data stream by
`compressing saidfirst data block with afirst compres-
`sion technique and said second data block with a second
`compression technique, saidfirst and second compres-
`sion techniques are difierent, wherein a data rate ofthe
`compressed data stream is adjusted, by modifying a
`system parameter,
`to make a bandwidth of the com-
`pressed data stream compatible with a bandwidth ofthe
`memory device. said compressed data stream is stored
`on said memory device, said compression and storage
`occursfaster than said data stream is able to be stored
`on said memory device in said receivedform, afirst data
`descriptor is stored on said memory device indicative of
`saidfirst compression technique, and said‘/irst descrip-
`tor is utilized to decompress the portion o/‘said com-
`pressed data stream associated with said first data
`block.
`25. The system ofclaim 1, wherein the data accelerator is
`~ configured to append a type descriptor to thefirst and second
`compressed data blocks in the compressed data stream, and
`wherein the tipe descriptor includes values corresponding to
`a plurality ofencoding techniques that were applied to the
`compressed data stream.
`26. The system ofclaim I, wherein the data accelerator is
`configured to adjust the data rate of the compressed data
`stream by adjusting a compression ratio ofa lossless encoder.
`*
`*
`>l<
`=l<
`=l<
`
`Veritas Techs. LLC
`Exhibit 1011
`Page 002