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`US005745985A
`
`United States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,745,985
`
`Ghosh et al.
`[451 Date of Patent: May 5, 1998
`
`
`
`[54] METHOD OF ATTACHING A
`SEMICONDUCTOR MICROCHIP TO A
`CIRCUIT BOARD
`
`29/841 X
`.
`12/1996 Bakerctal.
`5,579,573
`8/1997 Berhardtetal. .......................... 29/840
`5,653,019
`FOREIGN PATENT DOCUMENTS
`
`[75]
`
`Inventors: Prosenjit Ghosh. Temple: Sunil
`Thomas. Austin. both of Tex.
`
`56-35448
`WO901399l
`
`Japan
`4/1981
`11/1990 WIPO
`
`................. .. 29/841
`................. .. 29/832
`
`Primary Examiner—Pcter Vo
`Attome); Agent, or Firm——Ronald O. Neaings; James C.
`Kesterson; Richard L. Donaldson
`
`[57]
`
`ABSTRACT
`
`A method of attaching a microchip onto a circuit board is
`described. The method may include: forming a core portion
`of thermally conductive and electrically conductive material
`50; forming a perimeter portion of thermally conductive and
`electrically nonconductive material 54', placing the core
`portion of thermally conductive and electrically conductive
`material 50 at a site on a circuit board 58 where the
`microchip 56 will be bonded; placing the perimeter portion
`of themrally conductive and electrically non—conductive
`material 54 around the core portion 50 on the circuit board:
`and attaching microchip component 56 to the core portion
`50 and the perimeter portion 54. The method may also
`include applying a catalyst on the circuit board before
`attaching the core and perimeter portions. The method may
`also include curing the core portion and the perimeter
`portion at 90 degrees C. for 10 minutes and then applying a
`catalyst on the core portion and the perimeter portion. The
`materials may once again be cured at 90 degrees C. for 10
`minutes. Other devices. systems and methods are also dis-
`closed.
`
`12 Claims, 4 Drawing Sheets
`
`[73] Assignee: Texas Instruments Incorporated.
`Dallas. Tex.
`
`[21] Appl. No.: 546,054
`
`[22] Filed:
`
`Oct. 20, 1995
`
`Related U.S. Application Data
`
`[60]
`
`Provisional application No. 60/000,455 Jun. 23, 1995.
`
`Int. Cl.‘ ............................ H05K 3/32; HOSK 13/04
`[51]
`[52] US. Cl. ............................... .. 29/834; 29/840; 29/841;
`174/260; 257/786; 361/719; 361/770; 361/771
`[58] Field of Search .............................. 29/832. 834. 854.
`29/830. 840. 841; 257/673. 709. 780. 782.
`784. 786; 361/767. 770. 771. 775. 707.
`717-720; 437/204. 209. 216; 174/260
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`2/1970 Goldstein ................................ 257/782
`6/1980 Nate et al.
`..
`.. 29/834 X
`3/1987 Smith .............
`29/854 X
`9/1992 Patterson et al.
`.. 29/830 X
`9/1995 Kodoh et al.
`257/780 X
`2/1996 Cognetti et al.
`.................... 361/770 X
`
`
`
`3,495,322
`4,208,005
`4,647,959
`5,147,210
`5,448,114
`5,489,752
`
`54
`
`52
`
`50
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`
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`NU MARK Ex.1018 p.1
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`U.S. Patent
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`May 5, 1998
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`Sheet 1 of 4
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`5,745,985
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`52
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`NU MARK Ex.1018 p.2
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`U.S. Patent
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`May 5, 1993
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`Sheet 2 of 4
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`NU MARK Ex.1018 p.3
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`U.S. Patent
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`May 5, 1998
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`Sheet 3 of 4
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`5,745,985
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`NU MARK Ex.1018 p.4
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`U.S. Patent
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`May 5, 1998
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`Sheet 4 of 4
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`1
`METHOD OF ATTACHING A
`SEMICONDUCTOR MICROCHIP TO A
`CIRCUIT BOARD
`
`This application claims priority under 35 USC § 119 (c)
`(l) of provisional application number 60/000,455. filed Jun.
`23. 1995.
`
`FIELD OF THE INVENTION
`
`This invention generally relates to an electro - thermal
`nested die-attach design for Tape-Automated Bonding
`(TAB) semiconductor microchips.
`
`BACKGROUND OF THE INVENTION
`
`Without limiting the scope of the invention. its back-
`ground is described in connection with TAB mounted semi-
`conductor microchips. as an example.
`Semiconductors are widely used in integrated circuits for
`electronic applications. including high speed computers and
`wireless communications. Such integrated circuits typically
`use multiple transistors fabricated in single crystal silicon.
`Many integrated circuits now contain multiple levels of
`metallization for interconnections. A single semiconductor
`microchip may have thousands. and even millions of tran-
`sistors. Logically. a single microchip may also have millions
`of lines interconnecting the transistors. In addition. modern
`microchips have numerous other elements that make up part
`of the integrated circuit. As electrical current runs through
`these elements at astronomical speeds. heat dissipation
`becomes a major concern. Therefore. thermal relief becomes
`a major design requirement for modern microchips.
`In
`addition to the thermal relief that modern microchips
`require. some of these microchips also require an electrical
`contact as the chip is mounted to the circuit board.
`In addition. increased miniaturization in the electronics
`industry is causing more and more components to be placed
`onto circuit boards by the Tape Automated Bonding (TAB)
`method. Securing the leads on the device to the board can be
`achieved by two processes—“Formed Lead” and “No Form”
`process. Each has its advantages and disadvantages.
`In the Formed Lead process. leads are excised and formed
`to a gull-wing shape. In this process. the leads are formed in
`such a way that the die-attach thickness is accommodated
`between the die and the printed wiring board. In this process.
`the consistency of the die-attach is very critical. Warpage of
`the board can cause delarnination or unsatisfactory cover-
`age.
`
`In the No Form process, leads are excised but not formed
`Leads have and act much like angular cantilever beams.
`However. die—attach thickness is less critical in this method
`since the cantilever shaped leads are bent down during the
`bonding process. Accordingly. die-attach thickness may
`vary in this process. Not surprisingly. industry is slowly
`switching over to the No Form lead process. One of the
`driving forces for the switch—over is the ease of machine
`vision rather than the ease of die-attach.
`
`SUMMARY OF THE INVENTION
`
`It has been discovered that a common problem for board
`components that require thermal relief as well as electrical
`contact. is achieving both without shorting leads. In order to
`achieve both. the general method has been to have a film or
`a paste of a homogenous thermally and electrically conduc-
`tive die-attach adhesive material sandwiched between the
`semiconductor device and the circuit board. For applications
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`using adhesive films. the generally accepted practice has
`been to cut the die-attach at some percentage smaller than
`the pad size. The smaller sized adhesive allows growth
`during processing. but is small enough to prevent shorting
`the leads. For applications requiring pastes. the applied area
`is also smaller than the actual pad size for the same reasons
`as above. Currently. industry has accepted the compromises
`and the problems associated with such a weak design and
`process: shorting. low yields. large voids. difficult process
`control. thermal and electrical in-eficiencies. etc. Moreover.
`industry has unsuccessfully attempted to work around and
`even questioned the need for the core electrical path.
`However. studies have repeatedly shown that the center core
`of these devices are required to provide a critical contact to
`a ground plane. Lack of a solid ground plane such as this
`breeds numerous problems including radio frequency and
`electro magnetic interferences.
`In addition. as the throughput for boards with die-attached
`components increase. achieving a good bond between the
`core of the semiconductor and printed circuit board. with a
`high degree of reliability. has become essentially an impos-
`sibility. With increased thermal
`transfer loads on
`components. this problem has been exasperated by requiring
`an eificient thermal transfer. In addition. the bond joints
`based on traditional methods such as. one piece thermal}
`electrical die-attach films. dispensed thermal/electrical
`paste. and various other methods. have numerous problems.
`These problems include: low reliability. sensitive design.
`low yield. and large voids in the bond joint. Using the best
`methods and practices available today. percentage voids. as
`compared to the total area of coverage. are in double digits
`(10%. 12%. etc.) at best. In most production environments.
`voids between the component and the board. are typically
`between 20% to 60%. Furthermore. since the size of the void
`is inversely proportional
`to the thermal and electrical
`conductivity. minimizing voids is essential to a good design.
`The design and process of the invention consistently
`reduces this voiding problem to single digits. For the first
`time it
`is not only conceivable. but very achievable to
`consistently have voids less than three (3) percent in a
`production environment. Another advantage of the invention
`is that it is a very forgiving design. It is a truly robust design
`from every perspective. The shorting problem. that was so
`prevalent with the previous designs. has been eliminated.
`Voids have been achieved as low as 0.19%. A major aspect
`of the design is the thermally conductive (electrically non-
`conductive) barrier around the electrically and thermally
`conductive core piece. Having both substrates fabricated
`from the same or molecularly compatible material and using
`the process of the invention. this new design eliminates
`shorting problem to leads and ensures an almost perfect
`electrical and thermal transfer. Additionally. the invention
`may be used with any semiconductor device that requires
`thermal and electrical conductivity through the printed cir-
`cuit board, but requires electrical insulation at the leads.
`Amethod of attaching a microchip onto a circuit board is
`described. The method may include: forming a center core
`portion of thermally conductive and electrically conductive
`material; forming a perimeter portion of thermally conduc-
`tive and electrically nonconductive material; placing the
`center core portion of thermally conductive and electrically
`conductive material on a circuit board; placing the perimeter
`portion of thermally conductive and electrically nonconduc-
`tive material around the center core portion on the circuit
`board; and attaching microchip component to the center core
`portion and the perimeter portion. The method may also
`include applying a catalyst on the circuit board before the
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`NU MARK Ex.1018 p.6
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`3
`center core and perimeter portions. The method may also
`include curing the center core portion and the perimeter
`portion at 90 degrees C. for 10 minutes and then applying a
`catalyst on the center core portion and the perimeter portion.
`The device may then be cured at 90 degrees C. for 10
`minutes. Other devices. systems and methods are also dis-
`closed.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`In the drawings:
`FIG. 1 is a top view of the center core and perimeter bond
`portions;
`FIG. 2 is a cross view of the center core and perimeter
`bond portions. as well as the microchip. and the circuit
`board;
`PIGS. 3(A)—3(E) are Scanning Acoustic Microscope
`(SAM) photographs of five microchips produced under the
`old method;
`FIGS. 4(A)—4(E) are photographs of five non-functional
`microchips produced under the invention; and
`FIGS. 5(A)—5(H) are photographs of eight functional
`microchips produced under the invention.
`Corresponding numerals and symbols in the difierent
`figures refer to corresponding parts unless otherwise indi-
`cated.
`
`DEI‘A]LED DESCRIPTION OF PREFERRED
`EMBODINIENTS
`
`Die-attach materials are made from thermoplastic as well
`as thermoset material. Because of difiiculties in using ther-
`moset rnataials in die-attach applications and the relative
`ease of use of thermoplastic materials. they have gained
`increased popularity.
`The die-attach materials used in the preferred embodi-
`ment fall in the general category of Thermoplastic Adhe-
`sives. These products typically are available in paste or film.
`For the preferred embodiment. film was used. Normally. the
`film is applied followed by pressure and a curing cycle.
`The new die-attach design is comprised of two chemically
`compatible pieces. a center core and a perimeter. The center
`core is highly thermally and electrically conductive.
`In
`addition.
`the center core portion (in the preferred
`embodiment. the core portion was about 25% smaller than
`the die size. although this percentage may vary). The specific
`material used in the preferred embodiment is Staystick 591
`made by Alpha Metals Inc. Other materials that may be used.
`in the Staysticlr 500 family.
`include 501. 581. & 571.
`However. other materials with similar properties may be
`used.
`
`The specific material used for the perimeter is a thermally
`conductive material like the center core. but is electrically
`insulating (in the preferred embodiment, the perimeter por-
`tion covered about 123% of die size. although this percent-
`age vary). This eliminates shorting of the leads to the
`electrical and thermal core of the TAB device and acts as a
`physical barrier for the center core. The specific material
`used in the preferred embodiment was Staystick 692. Other
`materials from this family include Staystick 611. 672. &
`682. However. like the center core material. other materials
`with similar properties may also be used.
`Now referring to FIG. 1. the center core piece of die-
`attach material 50 is shown with the perimeter piece of die
`attach material 54. The two bond pieces should join after
`cure produce one seamless pad to attach the microchip onto
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`the circuit board. Therefore. the bond joint 52 should be
`almost indistinguishable.
`FIG. 2 depicts the bond materials 50. 54 between the
`microchip 56 and the printed circuit board 58.
`FIG. 3 includes five SAM photographs that depict a core
`bond portion in the center. shown in the darker regions
`making up the rest of the rectangular. These SAM photo-
`graphs were taken of an Intel Pentium microprocessor
`attached to a printed circuit board. Note that the lighta
`regions within the core portion of the bond material denote
`voids. The corresponding percentage voids are listed under
`the SAM photographs of each of the five examples (3a—e).
`These five examples were processed normally with only a
`core portion of bond material cut about 25% smaller than the
`microchip bond site in order to avoid shorting (since the
`behavior of the material causes it to enlarge about 13% after
`processing).
`FIG. 4 includes five SAM photographs similar to that of
`FIG. 3. however these photographs were taken of printed
`circuit boards with Pentium processors attached by the
`method and materials of the preferred embodiment. Note
`that
`the darker regions.
`in this figure. Within the bond
`material denote voids and are almost non-existent. Not
`
`surprisingly. the corresponding percentage of voids listed
`under each example confirm this. In addition. the seams
`between the center core bond material and perimeter bond.
`material can not be visually detected. Furthermore. since the
`perimeter portion of the bond material is elecn-ically non-
`conductive. it may get closer to the leads of the microchip
`and thus evades any voids around the leads. Moreover. these
`first five examples were processed on non—functional printed
`circuit boards.
`
`FIG. 5 includes eight SAM photographs similar to that of
`FIG. 4. but using fully functional printed circuit boards and
`live microchips. Note the small percentage voids are shown
`as lighter portions within the center core portion and are
`almost non-existent. These small amounts of voids confirm
`the method and materials used in the preferred embodiment.
`In addition. as stated previously, the preferred embodi-
`ment is described in relation to bonding an Intel Pentium
`microprocessor to a printed circuit board. The steps used to
`attach the microchip to the board started with cutting a ring
`of thermally conductive and electrically non-conductive
`material to make the perimeter portion of the bond material.
`Then the electrically conductive and thermally conductive
`material was cut out. A spray solvent was then sprayed on
`the printed circuit board (the solvent used in the preferred
`embodiment was di-propolyne glycol methyl ether acetate
`made by Alpha Metals). The center core portion was then
`placed in the center of the microchip bond site using an
`automated machine or a template. Precise placement of this
`piece relative to the bond site is very critical since a
`misplacement might cause a short with the leads. The
`perimeter portion. which is not electrically conductive is
`then placed around the center core portion. The perimeter
`portion should be placed in a manner to ensure no overlap
`with the center core portion. and form a composite bond
`after full cure (after full cure. bond joint should be
`indistinguishable). The center core and perimeter portions
`are then cured inan oven at 90 degrees C. for 10 minutes.
`Solvent is then sprayed on both portions. The microchip is
`then placed over the bond materials. The die-attach material
`is cured for a second time, in an oven at 90 degrees C. for
`10 minutes.
`
`A few preferred embodiments have been described in
`detail hereinabove. It is to be understood that the scope of
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`NU MARK Ex.1018 p.7
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`the invention also comprehends embodiments ditferent from
`those described. yet within the scope of the claims. For
`example. a thermoplastic. as well thermoset material may be
`used as die-attach adhesive. In addition. other adhesives that
`are similar in characteristics to those listed may also be
`substituted in the invention. Moreover. the perimeter bond
`material may be placed onto the bond site as one unit or
`divided into pieces. Additionally. the invention may be used
`with any semiconductor device that requires thermal and
`electrical conductivity through the printed circuit board. but
`requires electrical
`insulation at
`the leads. Furthermore.
`words of inclusion are to be interpreted as nonexhaustive in
`considering the scope of the invention.
`While this invention has been described with reference to
`illustrative embodiments. this description is not intended to
`be construed in a limiting sense. Various modifications and
`combinations of the illustrative embodiments. as well as
`other embodiments of the invention. will be apparent to
`persons skilled in the art upon reference to the description.
`It is therefore intended that the appended claims encompass
`any such modifications or embodiments.
`What is claimed is:
`
`1. A method of attaching a semiconductor microchip to a
`circuit board. said method comprising:
`applying a catalyst on said circuit board;
`placing a center core bond portion of thermally conduc-
`tive and electrically conductive material on said circuit
`board where the catalyst has been applied thereon;
`placing a perimeter bond portion of thermally conductive
`and electrically nonconductive material around said
`center core bond portion on said circuit board where the
`catalyst has been applied thereon;
`at least partially curing the circuit board and the center
`core and perimeter bond portions;
`placing said semiconductor microchip on said center core
`and perimeter bond portions; and
`curing the semiconductor microchip. the center core bond
`portion and the perimeter bond portion.
`2. The method of claim 1. wherein said method further
`includes forming said perimeter bond portion of thermally
`conductive and electrically nonconductive material from
`thermoplastic material. and forming said center core bond
`portion of thermally conductive and electrically conductive
`material from thermoplastic material.
`3. The method of claim 1. wherein said method further
`includes forming said perimeter bond portion of thermally
`conductive and electrically nonconductive material from
`thermoset material, and fonning said center core bond
`portion of thermally conductive and electrically conductive
`material from thermoset material.
`4. The method of claim 1. wherein said method further
`comprises placing the center core bond portion on the circuit
`board by means of an automated machine or template.
`5. A method of attaching a semiconductor microchip to’ a
`circuit board. said method comprising:
`applying a solvent agent on said circuit board;
`placing a center core bond portion of thermally conduc-
`tive and electrically conductive material on said circuit
`board where the solvent agent has been applied
`thereon;
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`placing a perimeter bond portion of thermally conductive
`and electrically nonconductive mataial around said
`center core bond portion on said circuit board where the
`solvent agent has been applied thereon;
`at least partially curing the circuit board and the center
`core and perimeter bond portions;
`
`65
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`placing said semiconductor microchip on said center core
`and perimeter bond portions; and
`curing the semiconductor microchip. the center core bond
`portion and the perimeter bond portion.
`6. A method of attaching a semiconductor microchip to a
`circuit board. said method comprising:
`placing a center core bond portion of thermally conduc-
`tive and electrically conductive material on said circuit
`board;
`placing a perimeter bond portion of thermally conductive
`and electrically nonconductive material around said
`center core bond portion on said circuit board;
`ctning said center core bond portion and said perimeter
`bond portion at 90 degrees C. for 10 minutes;
`placing said semiconductor microchip on said center core
`and perimeter bond portions; and
`curing the semiconductor microchip. the center core bond
`portion and the perimeter bond portion.
`7. A method of attaching a semiconductor microchip to a
`circuit board. said method comprising:
`placing a center core bond portion of thennally conduc-
`tive and electrically conductive material on said circuit
`board;
`placing a perimeter bond portion of thennally conductive
`and electrically nonconductive material around said
`center core bond portion on said circuit board;
`at least partially curing the circuit board and the center
`core and perimeter bond portions;
`applying a catalyst on said center core bond portion and
`said perimeter bond portion;
`placing said semiconductor microchip on said center core
`and perimeter bond portions. and
`curing the semiconductor microchip. the center core bond
`portion and the perimeter bond portion.
`8. A method of attaching a semiconductor microchip to a ‘
`circuit boards said method comprising:
`placing a center core bond portion of thermally conduc-
`tive and electrically conductive material on said circuit
`board;
`placing a perimeter bond portion of thermally conductive
`and electrically nonconductive material around said
`center core bond portion on said circuit board;
`at least partially curing the circuit board and the center
`core and perimeter bond portions;
`applying a solvent agent on said center core bond portion
`and said perimeter bond portion;
`placing said semiconductor microchip on said center core
`and perimeter bond portions; and
`curing the semiconductor microchip. the center core bond
`portion and the perimeter bond portion.
`9. A method of attaching a semiconductor microchip to a
`circuit board. said method comprising:
`placing a center core bond portion of thermally conduc-
`tive and electrically conductive material on said circuit
`board;
`placing a perimeta bond portion of thermally conductive
`and electrically nonconductive material around said
`center core bond portion on said circuit board;
`at least partially curing the circuit board and the center
`core and perimeter bond portions;
`placing said semiconductor microchip on said center core
`and perimeter bond portions; and
`curing said semiconductor microchip. said center core
`bond portion and said perimeter bond portion at 90
`degrees C. for 10 minutes.
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`10. A method of attaching a semiconductor microchip to
`a circuit board. said method comprising:
`applying a solvent agent on said circuit board;
`placing a center core bond portion of thermally conduc-
`tive and electrically conductive material on said circuit
`board. where the solvent agent has been applied
`thereon. using an automated machine or a template;
`placing a perimeter bond portion of thermally conductive
`and electrically nonconductive material around said
`center core bond portion on said circuit board where the
`solvent agent has been applied thereon;
`at least partially curing said circuit board and the center
`core and perimeter bond portions at 90 degrees C. for
`10 minutes;
`
`applying a solvent agent to a surface. onto which the
`microchip will be placed. of said center core and
`perimeter bond portions;
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`8
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`placing said semiconductor microchip to said center core
`and perimeter bond portions; and
`curing said semiconductor microchip. said center core
`bond portion and said perimeter bond portion at 90
`degrees C. for 10 minutes.
`11. The method of claim 10. wherein said method further
`includes forming said perimeter bond portion of thermally
`conductive and electrically nonconductive material from
`thermoplastic material and forming said center core bond
`portion of themially conductive and electrically conductive
`material from thermoplastic material.
`12. The method of claim 10. wherein said method further
`includes forming said perimeter bond portion of thermally
`conductive and electrically nonconductive material from
`thermoset material and forming said center core bond por-
`tion of thermally conductive and electrically conductive
`material from thermoset material.
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