United States Patent £19]
`Iijima
`
`[11]
`
`[45]
`
`4,215,369
`Jul. 29, 1980
`
`[54] DIGITAL TRANSMISSION SYSTEM FOR
`TELEVISION VIDEO SIGNALS
`Inventor: Yukihiko Iijima, Tokyo, Japan
`(75]
`[73] Assignee: Nippon Electric Company, Ltd.,
`Tokyo, Japan
`[21] Appl. No.: 970,051
`[22] Filed:
`Dec. 15, 1978
`Foreign Application Priority Data
`[30]
`Dec. 20, 1977 [JP]
`Japan ................................ 52-153920
`Dec. 20, 1977 [JP]
`Japan ................................ 52-153932
`Mar. 28, 1978 [JP]
`Japan .................................. 53-36335
`Int. CI.2 ............................................... H04N 7/08
`[51]
`[52] U.S. CI •.................................................... 358/146
`[58] Field of Search ........................ 358/141, 142, 146
`References Cited
`U.S. PATENT DOCUMENTS
`5/1974 Lee ................................... 358/146 X
`
`3,811,008
`
`[56]
`
`Primary Examiner-Robert L. Richardson
`Attorney, Agent, or Firm-Sughrue, Rothwell, Mion,
`Zinn and Macpeak
`[57]
`ABSTRACI'
`A digital transmission system for television video sig(cid:173)
`nals of the type which comprises a transmitter and a
`receiver, the transmitter having a plurality of input
`terminals for receiving respective television video sig(cid:173)
`nals to be transmitted, a plurality of encoding units for
`encoding the respective video signals into digitized
`video signals, and a multiplexers for multiplexing the
`respective digitized video signals in a time division
`manner, and the receiver having a demultiplexer for
`receiving the multiplexed video signal from the multi(cid:173)
`plexer and for separating the same into said digitized
`video signals, and a plurality of decoding units for de(cid:173)
`coding the digitized video signals into said respective
`television video signals, is disclosed.
`
`11 Claims, 54 Drawing Figures
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`U.S. Patent
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`Jul. 29, 1980
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`Sheet 1 of 11
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`U.S. Patent
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`Jul. 29, 1980
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`U.S. Patent
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`Jul. 29, 1980
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`Sheet 6 of 11
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`U.S. Patent
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`Jul. 29, 1980
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`Sheet 10 of 11
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`Jul. 29, t9so
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`4,215,369
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`1
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`DIGITAL TRANSMISSION SYSTEM FOR
`TELEVISION VIDEO SIGNALS
`
`4,215,369
`
`2
`plurality of input terminals for rece1vmg respective
`television video signals to be transmitted, a plurality of
`encoding units for encoding said respective video sig(cid:173)
`nals into digitized video signals, and a multiplexer for
`multiplexing said respective digitzed video signals in a
`time division manner; and said receiver comprising a
`demultiplier for receiving the multiplexed video signal
`transmitted from said multiplexer and for separating the
`same into said digitized video signals, and a plurality of
`10 decoding units for decoding said digitized video signals
`given from said demultiplexer into said respective tele(cid:173)
`vision video signals, the improvement wherein:
`each of said encoding units comprises a synchroniza(cid:173)
`tion (sync) pulse separator for separating sync pulses
`involved in said video signal, an encoder responsive to
`the separated sync pulses for encoding said television
`video signal into predetermined codes, a generator for
`generating video-frame-sync codes each indicative of
`the end of one picture frame of said video signal, first
`means for multiplexing said video-frame-sync codes and
`the encoded codes of said encoder, a first buffer mem-
`ory for temporarily storing the multiplexed codes from
`said first means, a first read/write controller for supply(cid:173)
`ing write-in and read-out address signals to said first
`buffer memory and for measuring a buffer-occupancy
`state of said first buffer memory to produce a buffer-
`occupancy code, second means for measuring a time
`interval from a time point when said video-frame-sync
`code is written into said first buffer memory to a time
`point when said video-frame-sync code is read out of
`said first buffer memory and for producing a first time(cid:173)
`indicating code representative of said time interval,
`third means for multiplexing the codes read out from
`said first buffer memory and said first time-indicating
`code and for supplying the output therefrom to said
`multiplexer; and
`each of said decoding units comprises a second buffer
`memory for temporarily storing said digitized video
`signal supplied from the corresponding encoding unit, a
`second read/write controller for producing write-in
`address signals for writing said multiplexed codes and
`said time-indicting code into said second buffer mem(cid:173)
`ory, fourth means for detecting said first time-indicating
`code in said digitized video signal, fifth means for mea(cid:173)
`suring a time interval from a time point when said
`video-frame-sync code is written into said second buffer
`memory to a time point when said video-frame-sync
`code is read out of said second buffer memory and for
`producing a second time-indicating code representative
`of said time interval, and a buffer memory controller for
`comparing said first and said second time-indicating
`codes and for controlling said write-in address signals
`based on said comparison.
`
`FIELD OF THE INVENTION
`This invention relates to a digital transmission system
`for television video signals with high transmission effi(cid:173)
`ciency.
`BACKGROUND OF THE INVENTION
`To improve the transmission efficiency for digitized
`television video signals, a variable-length code tech(cid:173)
`nique has been used in prior arts such as variable-length
`differential pulse-code modulation systems and predic(cid:173)
`tive encoding transmission systems based on interframe 15
`correlation. In either case, video signals to be transmit(cid:173)
`ted are sampled at a sampling rate proportional to a
`predetermined scanning rate. However, since signifi(cid:173)
`cant information to be transmitted is distributed at ran(cid:173)
`dom with repsect to time, a buffer memory for tempo- 20
`rarily storing encoded digital signals is needed on the
`transmitter side to transmit them at a predetermined bit
`rate. Correspondingly, another buffer memory for tem(cid:173)
`porarily storing the digital signals transmitted is needed
`at the receiving end. Also, it is necessary to decode the 25
`received digital signals at the same sampling rate as that
`in the transmitter so as to avoid an overflow or under(cid:173)
`flow of the buffer memory at the receiver. In order to
`avoid such an overflow, the buffer memory of the re(cid:173)
`ceiver is required to have a capacity sufficiently larger 30
`than that of the transmitter.
`To remove this restriction imposed on the receiver, a
`transmission system for digitized video signals has been
`proposed in the U.S. Pat. No. 4,027,100 issued May 31,
`1977. According to this prior art, a buffer memory at 35
`the transmitter stores synchronization signals produced
`regularly, signals indicative of a buffer-occupancy state
`immediately following the respective synchronization
`signals, and information signals produced between each
`signal indicative of a buffer-occupancy state and the 40
`succeeding synchronization signal unevenly in response
`to the video signal to be transmitted. A buffer memory
`at a receiver stores the signals transmitted from the
`transmitter. A decoder coupled to the receiver-side
`buffer memory decodes the information signals at a 45
`decoding rate controlled with reference to the differ(cid:173)
`ence between an actual sum of buffer occupancies of
`both buffer memories and a value predetermined for the
`sum. However, this system can not be applied to the
`transmission whose transmission speed is constant.
`Besides, a television video signal transmission system
`based on a time-division multiplex technique has been
`disclosed by Kaneko et al, in "Digital Transmission of
`Broadcast Television with Reduced Bit Rate", National
`Telecommunications, volume 3, 1977, section No. 41, 55
`pages 4-1 to 4-6. With this prior art, each channel infor(cid:173)
`mation in one frame is assigned depending on the
`amount of information to be transmitted. However,
`because the transmission speed of information is not
`constant with respect to time, the improved technique 60
`disclosed in the U.S. Pat. No. 4,027,100 cannot be
`adapted to the second prior art.
`An object of this invention is therefore to provide a
`digital transmission system for television video signals.
`
`50
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`This invention will be described in greater detail in
`conjunction with the accompanying drawings in which:
`FIG. 1 is a block diagram of a transmitter for use in
`first embodiment of this invention;
`FIGS. 2, 5 and 6 show block diagrams illustrating
`detailed portions of the transmitter of FIG. 1;
`FIGS. 3a and 3b, FIGS. 4a through 4c, FIGS. 7a
`through 1d, and FIGS. Sa through 8n show waveforms
`65 for explaining the operation of the transmitter of FIG.
`1;
`
`FIG. 9 is a block diagram of a receiver for use in the
`first embodiment of this invention;
`
`SUMMARY OF THE INVENTION
`The present transmission system comprises a trans(cid:173)
`mitter and a receiver, said transmitter comprising a
`
`13
`
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`4,215,369
`
`3
`FIGS. 10 and 11 show block diagrams illustrating
`detailed portions of the receiver of FIG. 9;
`FIG. 12 is a block diagram of a transmitter of a sec(cid:173)
`ond embodiment of this invention;
`FIGS. 13a through 13v show waveforms for explain- 5
`ing the operation of the transmitter of FIG. 12;
`FIG. 14 is a block diagram of a receiver of the second
`embodiment of this invention;
`FIG. 15 is a block diagram of a third embodiment of
`this invention; and
`FIG. 16 is a block diagram of a fourth embodiment of
`this invention.
`
`lO
`
`through the second multiplexer 13 from the encoder 4
`and produces write-in address signals, and a second
`counter 72 which counts reading pulses 87 supplied
`through a third multiplexer 10 from the first multiplexer
`12 and produces read-out address signals, and a sub(cid:173)
`tractor 73 responsive to the output of the first and sec-
`ond counters 7t and 72 to perform a subtraction thereon
`and thereby to produce a buffer-occupancy code indica(cid:173)
`tive of a buffer occupancy state of the buffer memory 6.
`The write-in and read-out address signals given from
`the counters 7t and 12are applied to the buffer memory
`6. On the other hand, the output of the subtractor 73 is
`fed to the first multiplexer 12.
`A video-frame-sync code detector 9 receives the
`15 codes read out of the buffer memory 6 to detect the
`video-frame-sync codes involved therein. The detection
`signal 84 fed from the detector 9 is then sent to both a
`third multiplexer 10 and a timer 8. The timer 8 includes
`a clock generator for generating clock pulses, and a
`counter for initiating its counting upon receiving the
`vertical sync pulses 88 obtained from the separator 3
`and for terminating it upon ·receipt of the detection
`signal 84 given from the detector 9 to produce a code 85
`indicative of a time interval therebetween. The time(cid:173)
`indicating code 85 is supplied to the third multiplexer 10
`in response to the signal 84 for multiplexing the codes
`read out of the buffer memory 6 and said time-indicat(cid:173)
`ing code 85. The output of the third multiplexer 10 is
`applied to the next stage, that is, a parallel/serial con(cid:173)
`verter 11.
`Referring to FIG. 4a corresponding to FIG. 8(g)
`referred to hereafter, "A" denotes the time-indicating
`code 85; "c"', a portion of the significant codes C of
`FIG. 3b, and CHit to CHlJ, time slots assigned to the
`codes given from the encoding unit 2t.
`Each of the time slots CH1t to CH13 has a constant
`capacity of, for example, 256 bits. Whereas, the total bit
`number of the codes involved in one picture frame of
`FIG. 3b is, 256 bits in the case of a still picture, and
`otherwise more than 256 bits. As a result, the time slot
`CHit usually accommodates a portion c' of the codes of
`one picture frame and the remaining two time slots
`CH12 and CH13 (if necessary more than two) shares the
`other portion.
`The multiplexer 12 will be described in more detail in
`connection with FIGS. 5 and 8. It is assumed for sim(cid:173)
`plicity of description that the multiplexer 12 is con(cid:173)
`nected to three encoding units 2t to 23. A register 15
`responsive to frame sync pulses (FIG. 8a) supplied form
`a multiplexer controller 19 stores the first four signifi(cid:173)
`cant bits of the buffer-occupancy codes 83 given from
`the read/write controllers 7 of the respective encoding
`units 2t to 23. A channel-assignment-signal generator 16
`consisting of an ROM (read only memory) and coupled
`to the register 15 produces a channel-assignment signal
`(FIG. 8b) in response to the output of the register 15. A
`counter 18 coupled to both the multiplexer controller
`19 and a clock generator 20 for generating clock pulses
`for transmission control, counts the clock pulses and is
`reset by the frame sync signal (FIG. 8a). A read-out
`signal controller 17 coupled to the channel assignment-
`signal generator 16 and the counter 18 produces gate
`pulses (FIGS. 8e, 8h and 8k) based on the output
`thereof. These gate pulses are then fed to AND gates
`21, 22 and 23, respectively, to which the clock pulses
`are applied from the clock generator 20. The AND
`gates 21 to 23 produce respectively the signals 87, 87'
`and 87" (FIGS. 8/, 8i, and 8[) one of which is supplied
`
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS OF THIS INVENTION
`First, a transmitter 100A for use in a frrst embodiment
`is described referring to FIGS. 1 through 4. A plurality
`of television video signals are given to input terminals
`1t, h, ... , 1n As shown in FIG. 3(a), each of the video
`signals comprises vertical sync pulses Yo (odd field) 20
`and V E(even field) at a regular interval, horizontal sync
`pulses (not shown) equally distributed with respect to
`time between two adjacent vertical sync pulses, and an
`analog information signal (not shown) which follows
`each horizontal sync pulse and represents a flow of 25
`picture elements along a horizontal scanning line. Inci(cid:173)
`dentally, in every drawing hereinafter referred to, thick
`signal lines represent the paths for parallel binary sig(cid:173)
`nals and thin signal lines, those for either analog signals
`or time-serial binary signals. Further, signal lines and 30
`signals may be sometimes represented by the same
`terms.
`The video signals are respectively supplied to their
`corresponding encoding units 2t to 2n through input
`terminals 11.to 1n and encoded into digitized video sig- 35
`nals. Each of the digitized video signals produced from
`the encoding units 2t to 2n are supplied to a first multi(cid:173)
`plexer 12 for multiplexing the digitized video signals.
`The multiplexed video signal is transmitted to a receiver
`over suitable transmission means (not shown). Since the 40
`encoding units 2t to 2n are identical to each other, de(cid:173)
`scription of only the unit 2t will be made hereafter.
`The video signal is supplied through the input termi(cid:173)
`nal 11 to a sync pulse separator 3 used in the encoding
`unit 21, which separates sync pulses therefrom. Also, 45
`said video signal through the input terminal 1t is given
`to an encoder 4 responsive to the horizontal sync pulses
`fed from the separator 3 so that the analog video infor(cid:173)
`mation can be encoded into predetermined codes based
`on the interframe encoding and variable-length encod- 50
`ing operations at a predetermined sampling rate and in
`synchronism with the horizontal sync pulses. For the
`details of the encoder 4, reference is made to an article
`by lshiguro et al titled "Composite Interframe Coding
`of NTSC Color Television Signals" published in Na- 55
`tiona/ Telecommunications Conference Record, vol. 1,
`1976, pages 6.4-1 to 6.4-4. A video-frame-sync code
`generator 14 produces video-frame-sync codes 81 each
`indicative of a picture frame end. A multiplexer 13 is
`responsive to the odd field vertical sync pulse V o sup- 60
`plied from the separator 3 to multiplex the video-frame(cid:173)
`sync code 81 and the encoded codes 82 of the encoder
`4. The output of the multiplexer 13 is then fed to a frrst
`buffer memory 6. Referring to FIG. 3b, reference char(cid:173)
`acters P and C designate the video-frame sync code and 65
`significant codes, respectively.
`A read/write controller 7 of FIG. 2 is comprised of a
`first counter 7t which counts writing pulses 86 supplied
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`14
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`6
`5
`A serial/parallel converter 33 converts the serial
`to the read/write controller 7 through the third multi-
`plexer 10. NAND gates 24, 25, and 26 receive respec-
`digitized video signal of one channel given from the
`tively, at their one input terminals 24a, 25a, and 26a, the
`demultiplexer 31 into a time parallel digitized video
`codes fed from the parallel/serial converters 11 of the
`signal. The parallel digitized video signal is then fed to
`encoding units 21 to 23, and also receive respectively, at
`a second buffer memory 35 and temporarily stored
`their other input terminals 24b, 25b, and 26b, the signals
`therein. A decoder 40 coupled to the second buffer
`(FIGS. Se, 8h and 8k) given from the read-out signal
`memory 35 is responsive to sampling pulses supplied
`controller 17. A NAND gate 27 is supplied at its one
`from a sampling-clock-pulse generator 41 for decoding
`the output of the buffer memory 35. The decoder 40
`input terminal 27a with the channel-assignment signal
`through a parallel/serial converter 16' from the genera- lO will be again referred to later by reference to FIG. 11.
`tor 16, and, at its other input terminal27b, with an as-
`A video-frame-sync code detector 34 coupled to the
`signment-signal-multiplexing pulse (FIG. Sc) given
`converter 33 detects the video-frame-sync code in-
`from the multiplexer controller 19. On the other hand, a
`valved in the time parallel digitized video signal to
`NAND gate 28 receives, at its input terminals 28a and
`produce a detection signal 89. The signal 89 is supplied
`28b, a frame sync signal (FIG. 8d) and the frame-sync- 15 to a timer 36 and to a register 38. A read/write control-
`signal-multiplexing pulse (FIG. Sa) fed from the multi-
`ler 42 is identical to the read/write controller 7 (FIG. 2)
`plexer controller 19, respectively. The output terminals
`except that the former is not provided with the sub-
`of the NAND gates 24 to 28 are coupled to the input
`tractor 173. It is therefore understood that the read/-
`terminal of another NAND gate 29 which forms an OR
`write controller 42 responsive to writing pulses sup-
`gate together with its preceding NAND gates 24 to 28. 20 plied through the converter 33 from the demultiplexer
`Thus, the first multiplexer 12 multiplexes the digitized
`31 as well as reading pulses from the buffer controller
`video signals (FIGS. 8g, 8j and 8m) and the channel
`39 produces write-in and read-out address signals sup-
`assignment and frame sync signals (FIGS. Sb and 8d).
`plied to the second buffer memory 35 for controlling its
`writing/reading operations. Another video-frame-sync
`The multiplexed video signal appears at the output 25 code detector 37 connected to the buffer memory 35
`terminal of the NAND gate 29.
`detects the video-frame-sync code read out therefrom
`Referring now to FIGS. 6 and 7, a detailed construe-
`to produce a detection signal 88 to be sent to the buffer
`tion of the multiplexer controller 19 is ij.lustrated to-
`controller 39. The register 38, in response to the detec-
`gether with the clock generator 20. The clock pulses
`tion signal 89, stores a first time-indicating code trans-
`(FIG. 7a) of the generator 20 are applied to a 1/N fre- 30 mitted from the transmitter 100A. The controller 39,
`quency divider 19t (where N is an integer equal to the
`which will be described later in more detail by refer-
`number of clock pulses appearing during one frame time
`ence to FIG. 11, controls both the second buffer mem-
`interval from the generator 20) and to four delay cir-
`ory 35 and the decoder 40 based on the signals 90 and
`cuits 194 to 197 (the number four comes from the as-
`85. The video-frame-sync code detector 34 or 37 and
`sumption that the register 15 of FIG. 5 stores the four 35 the timer 36 are identical to their counterparts shown in
`FIG. 1.
`significant bits of the incoming codes 83). The output of
`the frequency divider 19t is given to the register 15, the
`The demultiplexer 31 will be described in more detail
`counter 18, and a half-frequency divider 192 as well as
`referring to FIG. 10. A frame-sync-signal detector 43
`the NAND gate 28 as the frame-sync-signal-multiplex-
`coupled to the input terminal 30 detects the frame sync
`ing pulse (FIG. 7b and FIG. Sa). The divider 19zdivides 40 signal given from the received multiplexed video signal
`for producing a signal 91 to be supplied to a demulti-
`the frequency of the frame-sync-signal-multiplexing
`pulse by ! to produce a channel-assignament-signal
`plexer controller 44 and to a counter 46. The controller
`multiplexing pulse supplied to the NAND gate 27 as the
`44, in response to the signal91 as well as clock pulses 95
`frame sync signal (FIG. 7d and FIG. 8c). The output of
`given from a clock generator 51 produces a channel-
`the 1/N frequency divider 19t is also fed to the delay 45 assignment-signal multiplexing pulse, and consists of the
`circuit 194, the output of which is applied to the next
`delay circuits 194 to 197 and the OR gate 193 shown in
`delay circuit 19s. The other delay circuits 196 and 197
`FIG. 6. The signal 92 is supplied to a register 45 for
`are responsive to the output of their preceding circuits
`storing the channel-assignment-signal in the received
`19sand 196, respectively. The output of the delay circits
`multiplexed video signal, resulting in producing a signal
`194 to 197 are then supplied to an OR gate 193 to give the 50 93 indicative of the channel-assignment signal. The
`channel-assignment-multiplexing pulse (FIG. 7c and
`counter 46 counts the clock pulses 95 given from a
`FIG. 8d).
`clock generator 51 and is reset by the signal91. A write-
`Referring to FIG. 9, a receiver 100B usd in the first
`in signal controller 47 consisting of a ROM produces
`embodiment of this invention is schematically illus-
`gate pulses in response to the signals 93 and 94 and the
`trated in block form. A demultiplexer 31 is supplied 55 clock pulses 95. The output of the controller 47 is sup-
`with the multiplexed video signal received from the
`plied to AND gates 48, 49 and 50 for selectively allow-
`transmitter 100A through an input terminal 30. The
`ing them to pass the clock pulses 95 therethrough. The
`demultiplexer 31 functions to separate the supplied mul-
`clock pulses passing through the AND gate 48 are sup-
`tiplexed video signal into n channels (only three chan-
`plied as the writing signals to the read/write controller
`nels are shown in FIG. 9) of digitized video signals 60 42 through the serial/parallel converter 33 as shown in
`which correspond respectively to the output of the
`FIG. 9, while the remaining clock pulses passing
`encoding units 2t to 2n. The demultiplexer 31 supplies
`through the AND gates 49 and 50 are supplied to coun-
`the n channels of digitized video signals to respective
`terparts (not shown) ofthe decoding units 322 and 323 of
`decoding units 32t to 32n, each of which serves to de-
`FIG. 9.
`code the received digitized video signal into its original 65
`FIG. 11 is a detailed block diagram of the buffer
`video signal. Since the decoding units 32t to 32n are
`memory controller 39 and its known peripheral blocks.
`identical to each other in their circuit configuration,
`The controller 39 comprises a register 52t. two compar-
`only the unit 32t will be described hereunder.
`ators 52z and 523, a buffer control circuit 53 consisting
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`15
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`of an ROM, and three NAND gates 54 to 56 function~
`ing as a whole as two AND gates and an OR gate. The
`register 52t responsive to the signal88 supplied from the
`detector 37 stores the first and the second time-indicat(cid:173)
`ing codes 85 (Ts) and 90 (TR), respectively. The compar(cid:173)
`ators 52z and 523 function to produce signals indicating
`the following three different formulae or conditions
`depending upon relations between Ts+TRand TDand .0.:
`
`TS+TR-TD<-6.
`
`(2)
`
`(3)
`
`(I) 10
`
`NAND gate 54 allows the clock pulses given from the
`clock generator 41 to pass the NAND gates 541. and 56.
`Therefore, the write-in signals corresponding to the
`passed clock pulses are fed to the second buffer memory
`35. This means that the codes stored in the memory 35
`are read out in response to the applied clock pulses. The
`codes thus read out are supplied to the decoder, but no
`decoding operation can be performed until the condi(cid:173)
`tion (1) is satisfied. This means that the codes are read
`out in vain from the buffer memory 35 because the rate
`of the clock pulse generation is greater than the that of
`the request signal generation.
`Finally, let us consider the case where the condition
`15 (3) is satisfied, wherein the amount of codes stored in
`the buffer memory 35 does not reach the predetermined
`level. It is apparent in this instance that the clock pulses
`given from the clock generator 41 are not allowed to
`pass the NAND gate 56. As a result, the codes stored in
`the memory 35 are not read out therefrom until the first
`time-indicating signal90 (TR) satisfies the condition (1).
`While the condition (3) is satisfied, the decoder 40 re(cid:173)
`mains in its non-decoding state without producing an
`output or, otherwise, it may be designed to produce the
`preceding picture frame information stored in a frame
`memory used in the decoder 40. However, this opera(cid:173)
`tion of the decoder 40 is not directly concerned with
`this invention, so further description thereof will be
`omitted.
`In the first embodiment, the supply of the write-in
`signal or clocks to the second buffer memory 35 is con(cid:173)
`trolled by the time-indicating codes TS, TR, and TD.
`However, the supply of the write-in signal to the second
`buffer memory 35 can be controlled by the buffer-occu(cid:173)
`pancy code and the read-our signal generation rates of
`both the first and the second buffer memories 6 and 35
`and by the write-in rate of codes into the first buffer
`memory 6.
`More specifically, it will be understood that the fol(cid:173)
`lowing equations are given:
`
`20
`
`where
`6.: a predetermined positive real number; and
`TD: a signal indicative of a predetermined time inter-
`val determined by transmission speed over a transmis(cid:173)
`sion line used as well as capacities of the buffer memo-
`ries 6 and 35.
`In response to the signals given from the comparators
`52z and 523, the controller 53 produces binary "1" and(cid:173)
`/or "0" depending on the above conditions. Specifi(cid:173)
`cally, the controller 53 consisting of a ROM produces
`the following logical values depending on the condi- 25
`tions (1) to (3):
`(a) If the condition (1) is satisfied, binary "0" appears
`on the lines 53t and 533, and a binary "1" appears on the
`line 53z;
`(b) If the condition (2) is satisfied, a binary "1" ap- 30
`pears on all the lines 53t to 533; and
`(c) If the condition (3) is satisfied, a binary "1" or "0"
`appears on the line 53t and binary "0" appears on the
`lines 53z and 533.
`·
`Therefore, the NAND gate 56 produces a binary "1" 35
`on its output terminal, if all the inputs of the NAND
`gate 54 are binary "1" or all the inputs of the NAND
`gate 56 are binary "1 ".
`Since the receiver 100B of FIG. 9 functions in just a
`reverse manner as the transmitter 100A except the 40
`buffer memory controller 39, for understanding of the
`operation of the receiver 100B, the operations limited to
`the controller 39 will be described in detail hereinafter.
`First of all, let us consider the case where the above
`condition (1) is satisfied, namely, the buffer memory 35 45
`has a proper amount of codes stored so that the decoder
`40 is requested to perform its decoding operation. In
`this case, the controller 53 produces binary "1" on the
`signal line 53z and binary "0" on the signal lines 53t and
`533. For this reason, the decoder 40 receives binary "0" 50
`appearing on the line 533, and as a reuslt, the decoding
`operation of codes read out from the second buffer
`memory 35 is not prohibited, allowing the request signal
`fed to the input terminal SSt of the gate 55 from the
`decoder 40 to become binary "1". On the other hand, 55
`since the input terminal Sz of the gate 55 receives a
`binary "1" through the signal line 53z, all the input
`signals to the NAND gate 55 become binary "1", so that
`the NAND gate 56 may produce the write signal re-
`sponsive to the request signal.
`Next, considering the case where the condition (2) is
`satisfied. In this instance, codes more than the predeter(cid:173)
`mined amount are stored in the buffer memory 35. Since
`binary "1" appearing on the line 533 makes the decoder
`40 stop its decoding operation, the decoder 40 produces 65
`bi