UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`AND MICRON TECHNOLOGY, INC.,
`Petitioners,
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`v.
`
`DANIEL L. FLAMM,
`
`Patent Owner.
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`PTAB Case No. IPR2017-00282
`Patent No. RE40,264 E
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`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. RE40,264 E
`
`Claims 56-63 & 70-71
`
`
`
`

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`TABLE OF CONTENTS
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`
`Page
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`
`I.
`Introduction ..................................................................................................... 1
`II. Mandatory notices .......................................................................................... 2
`A.
`Real party in interest............................................................................. 2
`B.
`Related matters ..................................................................................... 2
`C.
`Notice of counsel and service information ........................................... 2
`III. Requirements for inter partes review ............................................................. 4
`A. Ground for standing ............................................................................. 4
`B.
`Identification of challenge .................................................................... 4
`IV. Overview of the ’264 patent ........................................................................... 5
`A.
`The claims recite two-temperature etch processes and add only
`conventional features ............................................................................ 8
`The earliest priority date for the ’264 patent is September 1997 ......... 9
`B.
`V. Overview of the prior art .............................................................................. 11
`A. Kadomura (Ex. 1005) ......................................................................... 12
`B. Matsumura (Ex. 1003) ........................................................................ 14
`C. Muller (Ex. 1002) ............................................................................... 18
`D. Kikuchi (Ex. 1004) ............................................................................. 21
`E. Wang (Ex. 1010) ................................................................................ 24
`VI. Claims 56-63 and 70-71 of the ’264 patent are unpatentable....................... 25
`A. Ground 1: Claims 56 and 58 are obvious over Kadomura and
`Matsumura .......................................................................................... 25
`1.
`Claim 56 ................................................................................... 25
`2.
`Claim 58 ................................................................................... 43
`Ground 2: Claim 57 is obvious over Kadomura, Matsumura,
`and Muller .......................................................................................... 44
`1.
`Claim 56 ................................................................................... 44
`2.
`Claim 57 ................................................................................... 44
`
`B.
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`-i-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`C.
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`Ground 3: Claims 59-61 and 71 are obvious over Kadomura,
`Matsumura, and Wang ....................................................................... 48
`1.
`Claim 56 ................................................................................... 48
`2.
`Claim 59 ................................................................................... 49
`3.
`Claim 60 ................................................................................... 52
`4.
`Claim 61 ................................................................................... 56
`5.
`Claim 71 ................................................................................... 57
`D. Ground 4: Claim 62 is obvious over Kadomura, Matsumura,
`Muller, and Wang ............................................................................... 57
`1.
`Claim 60 ................................................................................... 57
`2.
`Claim 62 ................................................................................... 57
`Ground 5: Claims 63 and 70 are obvious over Kadomura,
`Matsumura, Kikuchi, and Wang ........................................................ 58
`1.
`Claim 60 ................................................................................... 58
`2.
`Claim 63 ................................................................................... 58
`3.
`Claim 70 ................................................................................... 61
`Ground 6: Claims 56-62 and 71 are obvious over Muller,
`Matsumura, and Wang ....................................................................... 62
`1.
`Claim 56 ................................................................................... 62
`2.
`Claim 57 ................................................................................... 77
`3.
`Claim 58 ................................................................................... 78
`4.
`Claim 59 ................................................................................... 79
`5.
`Claim 60 ................................................................................... 82
`6.
`Claim 61 ................................................................................... 84
`7.
`Claim 62 ................................................................................... 86
`8.
`Claim 71 ................................................................................... 87
`
`E.
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`F.
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`-ii-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`
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`G. Ground 7: Claims 63 and 70 are obvious over Muller,
`Matsumura, Wang, and Kikuchi ........................................................ 88
`1.
`Claim 60 ................................................................................... 88
`2.
`Claim 63 ................................................................................... 88
`3.
`Claim 70 ................................................................................... 90
`VII. Conclusion .................................................................................................... 92
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`-iii-
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`

`
`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`EXHIBIT LIST AND TABLE OF ABBREVIATIONS AND CONVENTIONS
`
`Petitioner’s Exhibits
`
`Exhibit
`
`Description
`
`Ex. 1001 U.S. Patent No. RE40,264 (“’264 patent”)
`
`Ex. 1002 U.S. Patent No. 5,605,600 (“Muller”)
`
`Ex. 1003 U.S. Patent No. 5,151,871 (“Matsumura”)
`
`Ex. 1004 U.S. Patent No. 5,226,056 (“Kikuchi”)
`
`Ex. 1005 U.S. Patent No. 6,063,710 (“Kadomura”)
`
`Ex. 1006 Declaration of Dr. John Bravman in Support of Petition for Inter
`Partes Review of U.S. Patent No. RE40,264
`
`Ex. 1007 U.S. Patent Application No. 08/567,224 (“’224 application”)
`
`Ex. 1008 Wright, D.R. et al., A Closed Loop Temperature Control System for
`a Low-Temperature Etch Chuck, Advanced Techniques for
`Integrated Processing II, Vol. 1803 (1992), pp. 321–329 (“Wright”)
`
`Ex. 1009 U.S. Patent No. 5,711,849 (“’849 patent”)
`
`Ex. 1010 U.S. Patent No. 4,992,391 (“Wang”)
`
`Ex. 1011
`
`Fischl, D.S. et al., Etching of Tungsten and Tungsten Silicide Films
`by Chlorine Atoms, J. Electrochemical Soc.: Solid-State Science and
`Technology, Vol. 135, No. 8 (August 1988), pp. 2016-2019
`(“Fischl”)
`
`Ex. 1012 U.S. Patent No. 4,331,485 (“Gat”)
`
`Ex. 1013 U.S. Patent No. 5,393,374 (“Sato”)
`
`
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`-iii-
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`

`
`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`EXHIBIT LIST AND TABLE OF ABBREVIATIONS AND CONVENTIONS
`(continued)
`
`PTAB Decision Denying Institution of Inter Partes Review, Lam
`Research Corp. v. Daniel L. Flamm, IPR2016-00469, Paper 6 (July
`1, 2016)
`
`Ex. 1014
`
`Ex. 1015
`
`Ex. 1016
`
`PTAB Institution of Inter Partes Review, Lam Research Corp. v.
`Daniel L. Flamm, IPR2015-01768, Paper 7 (February 24, 2016)
`
`Petition for Inter Partes Review of U.S. Patent No. RE40,264 E
`Fourth Petition, Lam Research Corp. v. Daniel L. Flamm, IPR2015-
`01768, Paper 1 (August 18, 2015)
`
`Ex. 1017 U.S. Patent No. 5,242,536 (“Schoenborn”)
`
`Ex. 1018 U.S. Patent No. 5,174,856 (“Hwang”)
`
`Ex. 1019 Declaration of Rachel J. Watters regarding Exhibit 1008
`
`Ex. 1020 Declaration of Rachel J. Watters regarding Exhibit 1011
`
`Other Abbreviations and Conventions
`Petitioners
`Intel Corporation, GLOBALFOUNDRIES U.S., Inc., and Micron
`Technology, Inc.
`Daniel Flamm
`
`Patent
`Owner
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`-iv-
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`
`
`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`I.
`
`Introduction
`
`Dr. Daniel Flamm sued Petitioners Intel Corporation,
`
`GLOBALFOUNDRIES U.S., Inc., and Micron Technology, Inc. for allegedly
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`infringing U.S. Patent No. RE40,264. Petitioners request that the Board institute
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`5
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`an IPR trial on claims 56-63 and 70-71 of the ’264 patent because prior art that was
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`not before the examiner during prosecution renders those claims unpatentable.
`
`The ’264 patent is titled “Multi-Temperature Processing.” The challenged
`
`claims all require etching a substrate (such as a semiconductor wafer) at multiple
`
`temperatures and with preselected processing times. Several references that were
`
`10
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`not previously before the Patent Office show that multi-temperature etching and
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`predetermined process times were known long before the critical date. The claims
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`also tack on conventional semiconductor tool components (temperature sensors
`
`and control circuits), ordinary semiconductor materials (silicon-containing,
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`polysilicon, or silicide layers), well-known etching methods (etching with chlorine
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`15
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`and heat transfer based on radiation or gas pressure), or temperature ranges (above
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`49ºC, above room temperature, 180ºC-220ºC, or 50ºC-100ºC), but there was
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`nothing unexpected or inventive about the addition of those elements either.
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`Each of the challenged claims is a combination of well-known elements
`
`arranged in a conventional way to produce predictable results. The challenged
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`20
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`claims are obvious.
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`
`
`-1-
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`
`
`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`II. Mandatory notices
`A. Real party in interest
`The real parties in interest are Intel Corporation, GLOBALFOUNDRIES,
`
`Inc., GLOBALFOUNDRIES U.S., Inc., and Micron Technology, Inc.
`
`5
`
`B. Related matters
`Patent Owner has asserted the ’264 patent against Petitioners and others in
`
`lawsuits (now stayed) in the Northern District of California: Case Nos. 5:16-cv-
`
`01578-BLF, 5:16-cv-1579-BLF, 5:16-cv-1580-BLF, 5:16-cv-1581-BLF, and 5:16-
`
`cv-02252-BLF. In addition, Lam Research Corporation has filed a declaratory
`
`10
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`judgment action against Patent Owner on the ’264 patent (N.D. Cal. Case No.
`
`5:15-cv-01277-BLF) and IPR petitions on the ’264 patent (IPR2015-01759;
`
`IPR2015-01764; IPR2015-01766; IPR2015-01768; IPR2016-00468; IPR2016-
`
`00469; and IPR2016-00470). Finally, Samsung Electronics, Co., Ltd. has filed
`
`IPR petitions on the ’264 patent (IPR2016-01510 and IPR2016-01512).
`
`15
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`C. Notice of counsel and service information
`Petitioners’ respective counsel are:
`
`Lead Counsel
`
`Jonathan McFarland
`Reg. No. 61,109
`PERKINS COIE LLP
`1201 Third Avenue, Suite 4900
`Seattle, WA 98101
`206-359-8000 (phone)
`206-359-9000 (fax)
`Attorney for Intel Corporation
`
`Back-Up Counsel
`Chad Campbell
`Pro hac vice to be submitted
`Tyler Bowen
`Reg. No. 60,461
`PERKINS COIE LLP
`2901 N. Central Ave, Suite 2000
`Phoenix, AZ 85012
`602-351-8000 (phone)
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`-2-
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`

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`
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`602-648-7000 (fax)
`Attorneys for Intel Corporation
`
`Daniel Keese
`Reg. No. 69,315
`PERKINS COIE LLP
`1120 NW Couch St., 10th Floor
`Portland, OR 97209
`503-727-2000 (phone)
`503-727-2222 (fax)
`Attorney for Intel Corporation
`
`Jeremy Jason Lang
`Registration No. 73,604
`WEIL, GOTSHAL & MANGES LLP
`201 Redwood Shores Parkway
`Redwood Shores, CA 94065
`650-802-3237 (phone)
`650-802-3100 (fax)
`Attorney for Micron Technology, Inc.
`
`Jared Bobrow
`Pro hac vice to be submitted
`WEIL, GOTSHAL & MANGES LLP
`201 Redwood Shores Parkway
`Redwood Shores, CA 94065
`650-802-3034 (phone)
`650-802-3100 (fax)
`Attorney for Micron Technology, Inc.
`
`David M. Tennant
`Registration No. 48,362
`WHITE & CASE LLP
`701 Thirteenth Street, NW
`Washington, DC 20005-3807
`202-626-3600 (phone)
`202-639-9355 (fax)
`Attorney for GLOBALFOUNDRIES
`U.S., Inc.
`
`
`-3-
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`

`
`
`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`Nathan Zhang
`Registration No. 71,401
`WHITE & CASE LLP
`3000 El Camino Real
`5 Palo Alto Square, 9th Floor
`Palo Alto, CA 94306
`650-213-0300 (phone)
`650-213-8158 (fax)
`Attorney for GLOBALFOUNDRIES
`U.S., Inc.
`
`Petitioners consent to electronic service. All services and communications
`
`to the above attorneys can be sent to: Intel-Flamm-Service-IPR@perkinscoie.com;
`
`micron.flamm.service@weil.com; and WCGlobalFoundries-
`
`FlammTeam@whitecase.com. A Power of Attorney for Petitioners will be filed
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`5
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`concurrently with this Petition.
`
`III. Requirements for inter partes review
`A. Ground for standing
`The ’264 patent qualifies for IPR, and Petitioners are not barred.1
`
`B.
`
`Identification of challenge
`
`
`
` 1
`
` Patent Owner did not name Petitioners in an infringement complaint until January
`
`15, 2016, and the court did not issue summonses for purposes of service until
`
`January 21, 2016. N.D. Cal. Case No. 5:15-cv-01277-BLF, Dkts. 50, 58, 60 & 61.
`
`Patent Owner did not serve any Petitioner with the complaint before January 21,
`
`2016.
`
`-4-
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`

`
`
`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`Claims 56-63 and 70-71 should be cancelled as obvious based on:
`
`Ground References
`
`1
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`Muller, Matsumura, Wang, & Kikuchi (Exs. 1002-
`1004, 1010)
`
`Kadomura & Matsumura (Exs. 1003, 1005)
`Kadomura, Matsumura, & Muller (Exs. 1002-1003,
`1005)
`Kadomura, Matsumura, & Wang (Exs. 1003, 1005,
`1010)
`Kadomura, Matsumura, Muller, & Wang (Exs. 1002-
`1003, 1005, 1010)
`Kadomura, Matsumura, Kikuchi, & Wang (Exs. 1003-
`1005, 1010)
`Muller, Matsumura, & Wang (Exs. 1002-1003, 1010) Claims 56-62,
`71
`Claim 63, 70
`
`Challenged
`Claims
`Claims 56, 58
`Claim 57
`
`Claims 59-61,
`71
`Claim 62
`
`Claims 63, 70
`
`Wright, Fischl, Sato, Schoenborn, Hwang, and other references illustrated
`
`the state of the art at the time of the alleged invention. Ariosa Diagnostics v.
`
`Verinata Health, Inc., 805 F. 3d 1359, 1365 (Fed. Cir. 2015) (“Art can legitimately
`
`5
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`serve to document the knowledge that skilled artisans would bring to bear in
`
`reading the prior art identified as producing obviousness.”) (citation omitted).
`
`None of the above references was before the Patent Office during the examination
`
`leading to the ’264 patent. Petitioners further rely on the Declaration of Dr. John
`
`Bravman (Ex. 1006) and other supporting evidence in Petitioners’ exhibit list.
`
`10
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`IV. Overview of the ’264 patent
`The ’264 patent issued April 29, 2008 from a reissue application filed May
`
`14, 2003. The sole named inventor is Daniel L. Flamm. The patent discloses
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`-5-
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`

`
`
`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`processing (e.g., etching) a semiconductor wafer at two different temperatures on a
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`substrate holder (e.g., chuck) in a single tool chamber. (Ex. 1001, 2:10-12, 18:54-
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`56.) Specifically, the patent describes temperature control system 700, shown in
`
`Figure 7 below. (Id., 15:65-66.) That system heats or cools wafer chuck 701
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`5
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`(purple), which holds a wafer during processing. (Id., 16:3-5.) The control system
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`measures wafer and chuck temperatures, and a controller (not shown in Figure 7)
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`adjusts set temperatures to match desired levels using a heater (red) and fluid (blue)
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`from reservoir 713. (Id., 14:62-63,15:10-13, 16:3-19, 16:36-46, Fig. 6.) Control
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`system 700 “us[es] conventional means” to change temperatures “to pre-
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`10
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`determined temperatures within specific time intervals….” (Id., 16:60-67, 18:22-
`
`26; Ex. 1006 ¶¶46-50.)
`
`
`
`-6-
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`

`
`
`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`The patent describes a single embodiment of a semiconductor substrate (e.g.,
`
`wafer) that includes layers of silicon dioxide, polysilicon, tungsten silicide, and
`
`photoresist, as shown below in Figure 9. (Ex. 1001, 17:58-60; Ex. 1006 ¶51.)
`
`5
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`Figure 10 below plots changes in temperature against processing time. (Ex.
`
`1001, 18:22-19:64.)
`
`
`
`-7-
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`

`
`
`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`
`A. The claims recite two-temperature etch processes and add only
`conventional features
`
`Independent method claims 56 and 60 both recite putting a substrate (e.g.,
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`5
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`wafer) on a substrate holder (e.g., chuck) and etching the substrate at two selected
`
`temperatures in the same chamber. The claims also recite “sensing a substrate
`
`holder temperature” and using a control circuit to set and change substrate
`
`temperature. (Ex. 1006 ¶¶26-27.) The claims further require changing
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`temperature within a “pre-selected” time and performing etch at “above 49ºC.”
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`10
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`(claim 56) or “above room temperature” (claim 60). In addition, claims 56 and 60
`
`recite that the substrate must include layers. Claim 56 requires processing “a stack
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`of layers” and each step etches a “silicon-containing layer.” Claim 60 requires
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`-8-
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`
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`etching “a stack of layers including a silicide layer” where the silicide layer is
`
`etched second.
`
`The claims that depend from claim 56 (57-59) and claim 60 (61-63, 70-71)
`
`recite minor, conventional variations to the general process outlined above:
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`5
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`• temperature change time of “less than about 5 percent of the total
`
`etching process time” (57);
`
`• etching using “a chlorine-containing ambient” (58);
`
`• etching a layer stack containing a polysilicon layer on top of a silicide
`
`layer, with the second etching temperature higher than the first, and
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`10
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`one layer “selectively etched relative” to an oxide layer (59);
`
`• temperature change is “by at least heat transfer to the substrate using
`
`at least an electrostatic chuck” (61);
`
`• heat transfer based on “a pressure of a gas behind the substrate” (62);
`
`• heat transfer using “radiation” (63);
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`15
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`• substrate temperature of 180ºC-220ºC during processing (70); and
`
`• substrate temperature of 50ºC-100ºC during processing (71).
`
`The earliest priority date for the ’264 patent is September 1997
`
`B.
`For purposes of this Petition, September 11, 1997 is the earliest possible
`
`priority date for the challenged claims. Although the ’264 patent also recites a
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`20
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`priority claim to U.S. Patent Application No. 08/567,224, filed on December 4,
`
`-9-
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`1995 (Ex. 1007), that date is unsupportable because the ’224 application did not
`
`disclose the claimed subject matter.2
`
`For example, claim 56 requires changing the temperature of a substrate on a
`
`substrate holder from a “first” to a “second substrate temperature with a control
`
`5
`
`circuit operable to effectuate the changing within a preselected time period.” But
`
`the ’224 application did not disclose changing temperature “within a preselected
`
`time interval,” much less with the same substrate holder. (Ex. 1006 ¶¶30-31.)
`
`Claim 56 also requires maintaining substrate temperatures and a “control circuit”
`
`for adjusting substrate temperatures. The claimed approach requires a sensor to
`
`10
`
`measure substrate temperature. (Id. ¶¶32-33.) The ’224 application disclosed a
`
`thermocouple to measure the substrate holder temperature, not one to measure
`
`substrate temperature. (Id. ¶33.) The ’224 application also did not disclose using a
`
`control circuit to effectuate changes to substrate temperature. (Id.)
`
`
`
` 2
`
` In earlier IPRs, the Board found that September 11, 1997 is the earliest priority
`
`date for the claims. (Ex. 1014, 10-12.) Although unimportant to this Petition,
`
`Petitioners do not concede that the claims are entitled to priority as of September
`
`11, 1997.
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`-10-
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`
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`Claim 60 includes requirements similar to those in claim 56. For the reasons
`
`explained above for claim 56, claim 60 is also not entitled to priority before
`
`September 1997.
`
`V. Overview of the prior art
`As Kadomura, Matsumura, Kikuchi, and Muller illustrate, multi-temperature
`
`5
`
`wafer processing in a chamber was well known in the prior art. Kadomura, Muller,
`
`Wright, and Wang also show that etching different wafer layers at different
`
`temperatures was well known and a matter of routine process optimization. Those
`
`references disclosed what is recited in independent claims 56 and 60 and their
`
`10
`
`dependents. (Id. ¶¶35-41.)
`
`In particular, Kadomura, Matsumura, Kikuchi, and Muller disclosed
`
`controlling temperature changes (Ex. 1002, Abstract; Ex. 1003, Abstract, 1:8-13;
`
`Ex. 1005, Title, Abstract) through heating (Ex. 1004, 7:25-34; Ex. 1005, 11:42-47)
`
`and cooling (Ex. 1002, 4:51-5:25; Ex. 1003, 6:20-32; Ex. 1005, 11:42-59), and
`
`15
`
`rapid temperature changes to minimize potential processing delays (Ex. 1002,
`
`5:17-25, 6:66-7:8; Ex. 1003, 7:50-53, Figs. 8, 9; Ex. 1004, Abstract, 7:62-8:14; Ex.
`
`1005, 5:18-25; Ex. 1006 ¶¶35-41). They disclosed etching tools with sensors and
`
`controllers that measured and regulated temperature. (Ex. 1003, 6:20-32; Ex. 1005,
`
`10:36-52; Ex. 1008, 321.) The references also disclosed using processing recipes
`
`20
`
`to pre-program control systems to process wafers at particular times or
`
`-11-
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`
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00282)
`
`temperatures and to change temperatures within preselected times. (Ex. 1003, 3:1-
`
`16, 5:58-6:2, 7:19-32, 8:25-35, 8:56-68, Figs. 8-9.)
`
`Kadomura, Muller, Kikuchi, and Wang each disclosed etching different
`
`wafer layers, including the common layer materials described in the patent (e.g.,
`
`5
`
`silicide, polysilicon, oxide, and photoresist), in different configurations and at
`
`different temperatures. (Ex. 1002, Abstract, 1:14-16, 1:48-55, 3:45-52, 3:56-61,
`
`4:6-32, 5:17-25, 5:62-66, Figs. 6A-6C; Ex. 1004, Abstract, 7:47-8:14; Ex. 1005,
`
`5:57-60, 6:5-12, 6:29, 7:7, 7:64-8:1, 8:16, 8:64, 9:37-45, 9:62, 10:27, Figs. 1A-1C,
`
`Fig. 3; Ex. 1008, 324-25; Ex. 1010, 4:19-24, Fig. 3; Ex. 1006 ¶40.)
`
`10
`
`A. Kadomura (Ex. 1005)
`Kadomura was filed in February 1997. Like the ’264 patent, Kadomura
`
`disclosed a multi-temperature process for etching portions of a semiconductor
`
`wafer. (Ex. 1006 ¶¶59-69.) As shown in annotated Figure 4 below, Kadomura
`
`disclosed an etching tool with a heater (not explicitly shown but represented in red)
`
`15
`
`in wafer holder stage 12 (purple), chiller 17 (blue) for cooling stage 12,
`
`thermometer 18 (yellow) for measuring wafer temperature, and control device 25
`
`(orange) for controlling the temperature of wafer W (green) based on temperature
`
`measurements from thermometer 18. (Ex. 1005, 11:36-59, 12:37-48.) Kadomura
`
`adjusted the wafer’s temperature by changing the temperature of stage 12. (Id.,
`
`20
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`3:24-49.)
`
`-12-
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`

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`Kadomura also disclosed several examples of multi-temperature etch
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`processes, including etching wafers at and above room temperature (20ºC, 50ºC)
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`and changing etching temperature within about 30 or 50 seconds. (Id., 6:18-7:7,
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`7:58-8:64, 9:33-10:27.)
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`Kadomura further taught etching different layer configurations at different
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`temperatures. Figure 1A below shows wafer W with substrate 30, silicon dioxide
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`film 31, polysilicon layer 32, tungsten silicide layer 33, and patterned photoresist
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`34. (Id., 6:5-16.) In one example, Kadomura’s tool etched the silicide layer 33
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`and part of polysilicon layer 32 at 20ºC and then the remaining part of the
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`polysilicon layer at -30ºC. (Id., 6:18-29, 6:63-7:7.) It was also within the state of
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`the art to etch a silicide layer at temperatures up to 140ºC, as described in Fischl.
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`(Ex. 1011, 2018.)
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`As depicted in Figure 3A below, Kadomura disclosed a wafer W with silicon
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`dioxide layer 50, polysilicon layer 51, and photoresist pattern 52. (Ex. 1005, 9:38-
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`44.) Kadomura’s tool first etched a portion of the polysilicon layer at -30ºC and
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`then the remainder of that layer at 50ºC. (Id., 9:62, 10:27.)
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`B. Matsumura (Ex. 1003)
`Matsumura issued in September 1992. Like Kadomura, Matsumura
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`disclosed multi-temperature wafer processing in a chamber. In addition,
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`Matsumura disclosed the well-known practice of using recipes to preselect process
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`parameters such as temperatures and temperature change times. Matsumura also
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`disclosed the use of a substrate holder temperature sensor in conjunction with
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`processing recipes. (Ex. 1006 ¶¶70-75.)
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`As shown in annotated Figure 5A below, Matsumura taught a processing
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`tool with thermometer 24 and sensor 25 (yellow) for measuring the temperature of
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`wafer holding stage 12 (purple); control system 20 (orange) for managing
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`temperature changes; conductive thin film 14 (red) in stage 12 to heat wafer W
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`(green); and cooling system 23 (blue) for cooling the wafer. (Ex. 1003, 5:60-63,
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`5:68-6:2, 8:18-35.)
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`Substrate temperature sensors, like Matsumura’s, were well known in the
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`prior art. Kikuchi similarly taught a sensor for maintaining the temperature of its
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`hot plate wafer holder. (Ex. 1004, 2:1-3.) In addition, Wright, a paper published
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`in 1992, disclosed a processing tool that used two separate sensors to measure the
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`temperature of the wafer and the wafer holder. (Ex. 1008, 321 (“The system
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`employs an optical fluorescence probe on the chuck (a second probe monitors the
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`wafer temperature as well)….”).) Wright’s Figure 6 below shows sensor
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`measurements for the wafer and the chuck over time.
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`Likewise, using recipes to preselect temperature changes and other
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`processing conditions was well known in semiconductor manufacturing.
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`Matsumura’s control system 20 followed “predetermined recipe[s]” that specified
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`temperatures, processing times, and temperature change times. (Ex. 1003, 3:1-7,
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`3:14-16.) Matsumura’s Figure 9 (below) charts a sample recipe with multiple
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`preselected processing temperatures (y-axis) and temperature change times (x-axis).
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`Matsumura expressly taught that its recipe-based temperature control techniques
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`could be used in etching processes. (Id., 10:3-7.)
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`C. Muller (Ex. 1002)
`Muller (issued February 1997) also disclosed etching a wafer at two
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`sequential temperatures in a chamber. (Ex. 1006 ¶¶82-86.) Muller disclosed
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`etching surface layers on a wafer and deep trenches into the wafer while varying
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`wafer temperature using an electrostatic chuck and coolant circulating through a
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`cathode. (Ex. 1002, 1:7-12, 1:44-55, 4:51-63.) Annotated Figure 4 below shows
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`wafer 104 (green), electrostatic chuck 105 (purple), and cathode 106 (blue).
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`Muller taught performing an initial etch at 125ºC or 145ºC. (Id., 3:45-52,
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`3:56-66.) Then, the gas pressure underneath the chuck was changed to increase
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`wafer temperature by 50ºC in “several seconds” during etching. (Id., 4:64-5:25,
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`5:41-48.) Due to the 50ºC increase, Muller’s second etching step was performed at
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`175ºC (e.g., 125ºC plus 50ºC) or 195ºC (e.g., 145ºC plus 50ºC). (Id., 5:17-25,
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`5:41-48; Ex. 1006 ¶85.) The two etching temperature examples corresponded to
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`different coolant temperatures––(a) with coolant at 10ºC, etch steps 1 and 2 were at
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`125ºC (step 1) and 175ºC (step 2), respectively; and (b) with coolant at 30ºC, etch
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`steps 1 and 2 were at 145ºC (step 1) and 195ºC (step 2), respectively. (Ex. 1006
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`¶85.) Figure 3 below shows the different step 1 etching temperatures achieved for
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`coolant at 10ºC versus 30ºC.
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`Muller taught that etching at lower temperatures produced sloped sidewalls
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`in mask openings and deep trenches, while etching at higher temperatures
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`produced more vertical sidewalls. (Ex. 1002, 3:34-52, 6:3-10, Figs. 1-2; Ex. 1006
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`¶¶225, 232.) Those different sidewall profiles are shown in Figure 6C below.
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`D. Kikuchi (Ex. 1004)
`Kikuchi (issued July 1993) also disclosed multi-temperature etching within
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`the same chamber. (Ex. 1006 ¶¶110-115.) Kikuchi described ashing3 a wafer’s
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`photoresist film at two sequential temperatures using either heat lamps or a hot
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`plate to raise temperature, in addition to measuring wafer and hot plate
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`temperatures using different thermometers. (Ex. 1004, 1:56-2:3, 7:20-33, 7:62-68,
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`8:8-14, 11:6-9, Figs. 12-13.) Annotated Figures 1, 11, and 19 below show lamps 5
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`(red), hot plate 7 (purple) with heater 6 (red), wafer 1 (green), and thermometers 10
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`and 66 (yellow).
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` Ashing is a type of etching that uses a plasma, typically at high temperatures, to
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`remove a photoresist film. (Ex. 1006 ¶111.) Flamm’s U.S. Patent 5,711,849
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`described “resist stripp[ing]” as etching and dependent claims 7 and 16 recited
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`“ashing” as a subset of “etching.” (Ex. 1009, 1:7-9.)
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`Kikuchi ashed a photoresist film over a range of temperatures. The outer
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`surface of the photoresist film was hardened by ion beams and etched at a “low
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`temperature” to avoid explosions. (Id., 2:23-26, 3:23-27, 5:50-54.) Then, the inner
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`layer was etched at 200ºC (“high temperature”) for a “high speed” etch. (Id., 5:55-
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`56, 9:64-67.) Figure 5 below shows resist film 11 with hardened surface layer 11a.
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`Kikuchi used etching temperatures well above room temperature, with an initial
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`step at 70ºC-160ºC and a rapid increase to 200ºC in 5 or 10 seconds. Figures 12
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`and 13 below show exemplary temperature changes.
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`E. Wang (Ex. 1010)
`Wang (issued February 1991) taught etching silicide, polysilicon, and oxide
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`wafer layers. (Ex. 1010, 4:12-14; Ex. 1006 ¶¶101-103.) As shown in Figure 3
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`below, the layers in Wang’s wafer included a silicide layer 20 between polysilicon
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`layers 18 and 22, with oxide layers 16 and 24 on top and bottom. (Ex. 1010, 4:19-
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`23.)
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`F.
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`Level of ordinary skill in the art
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`A person of ordinary skill in the art at the time of the alleged invention of
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`the ’264 patent (“skilled person”) would have had (i) a Bachelor’s degree in
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`chemical engineering, materials science engineering, electrical engineering,
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`physics, chemistry, or a similar field, and three or four years of work experience in
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`semiconductor manufacturing or related fields; or (ii) a Master’s degree in
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`chemical engineering, materials science engineering, electrical engineering,
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`15
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`physics, chemistry, or a similar field, and two or three years of work experience in
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`semiconductor manufacturing or related fields; or (iii) a Ph.D. in chemical
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`engineering, materials science engineering, electrical engineering, physics,
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`chemistry, or a similar field. (Ex. 1006 ¶21.)
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`VI. Claims 56-63 and 70-71 of the ’264 patent are unpatentable
`This Petition uses primary references (1) Kadomura, (2) Matsumura, and
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`(3) Muller, along with secondary references (4) Wang, and (5) Kikuchi, to form
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`distinct unpatentability grounds for claims 56-63 and 70-71.
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`A. Ground 1: Claims 56 and 58 are obvious over Kadomura and
`Matsumura
`1.
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`Claim 56
`a.
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`Preamble: “A method fo