Trials@uspto.gov
`571.272.7822
`
`
` Paper No. 32
`
`Filed: January 31, 2019
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`MICRON TECHNOLOGY, INC., and
`SAMSUNG ELECTRONICS COMPANY, LTD.1,
`Petitioner,
`
`v.
`
`DANIEL L. FLAMM,
`Patent Owner.
`
`____________
`
`Case IPR2017-00282
`Patent RE40,264 E
`____________
`
`
`
`Before CHRISTOPHER L. CRUMBLEY, JO-ANNE M. KOKOSKI, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`
`
`1 Samsung Electronics Company, Ltd. was joined as a party to this
`proceeding via a Motion for Joinder in IPR2017-01752.
`
`
`571.272.7822
`
`
` Paper No. 32
`
`Filed: January 31, 2019
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`MICRON TECHNOLOGY, INC., and
`SAMSUNG ELECTRONICS COMPANY, LTD.1,
`Petitioner,
`
`v.
`
`DANIEL L. FLAMM,
`Patent Owner.
`
`____________
`
`Case IPR2017-00282
`Patent RE40,264 E
`____________
`
`
`
`Before CHRISTOPHER L. CRUMBLEY, JO-ANNE M. KOKOSKI, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`
`
`1 Samsung Electronics Company, Ltd. was joined as a party to this
`proceeding via a Motion for Joinder in IPR2017-01752.
`
`
`
`IPR2017-00282
`Patent RE40,264 E
`
`
`I. INTRODUCTION
`
`In this inter partes review, instituted pursuant to 35 U.S.C. § 314,
`
`Intel Corporation, GLOBALFOUNDRIES U.S., Inc., Micron Technology,
`
`Inc., and Samsung Electronics Company, Ltd., (collectively “Petitioner”)
`
`challenge the patentability of claims 56–63, 70, and 71 of U.S. Patent
`
`No. RE40,264 E (Ex. 1001, “the ’264 patent”), owned by Daniel L. Flamm.
`
`(“Patent Owner”).
`
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`
`Decision, issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73,
`
`addresses issues and arguments raised during trial. For the reasons discussed
`
`below, we determine that Petitioner has shown by a preponderance of the
`
`evidence that claims 56–63, 70, and 71 of the ’264 patent are unpatentable.
`
`A. Procedural History
`
`On December 2, 2016, Intel Corporation, GLOBALFOUNDRIES
`
`U.S., Inc., and Micron Technology, Inc. (collectively, “Initial Petitioners”)
`
`filed a Petition requesting an inter partes review of claims 56–63 and 70–71
`
`of the ’264 patent. Paper 2 (“Pet.”). Patent Owner filed a Preliminary
`
`Response. Paper 8. On June 13, 2017, we instituted an inter partes review of
`
`the challenged claims. Paper 9 (“Decision on Institution” or “Dec. on Inst.”).
`
`Subsequent to institution, Samsung Electronics Company, Ltd. (“Samsung”)
`
`filed a petition and motion for joinder with the instant proceeding. Samsung
`
`Electronics Company, Ltd. v. Daniel L. Flamm, Case IPR2017-01752,
`
`Papers 1, 3. On September 15, 2017, we granted Samsung’s petition and
`
`motion for joinder, joining Samsung as a petitioner in this inter partes
`
`review. Paper 12, 7.
`
`2
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`IPR2017-00282
`Patent RE40,264 E
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`Thereafter, Patent Owner filed a Patent Owner Response (Paper 13,
`
`“PO Resp.”) and Petitioner filed a Reply (Paper 14, “Reply”). In support of
`
`their respective arguments, Petitioner relies upon the declaration testimony
`
`of Dr. John Bravman (Exs. 1006 and 1023), and Patent Owner relies upon
`
`the declaration testimony of Dr. Daniel L. Flamm2 (Ex. 2001).
`
`Oral hearing was requested by both parties. Papers 17, 18. A
`
`consolidated oral hearing for this proceeding and Cases IPR2017-00279,
`
`IPR2017-00280, and IPR2017-000281, involving the same parties and
`
`the ’264 patent, and Cases IPR2017-00391, IPR2017-00392, and IPR2017-
`
`00406, involving the same parties and unrelated patents, was held on
`
`March 7, 2018. A transcript of the consolidated hearing has been entered
`
`into the record. Paper 30 (“Tr.”).
`
`B. Related Proceedings
`
`Petitioner reports that the Patent Owner has asserted the ’264 patent in
`
`five proceedings in the Northern District of California (Case Nos. 5:16-cv-
`
`01578-BLF, 5:16-cv-1579-BLF, 5:16-cv-1580-BLF, 5:16-cv-1581-BLF, and
`
`5:16-cv-02252-BLF) and that Lam Research Corporation has filed a
`
`declaratory judgment action against Patent Owner on the ’264 patent, also in
`
`the Northern District of California (Case No. 5:15-cv-01277-BLF). Pet. 2.
`
`Petitioner also challenges certain claims of the ’264 patent in
`
`IPR2017-00279, IPR2017-00280, and IPR2017-00281, which were filed
`
`concurrently with the Petition in this proceeding. The parties also identified
`
`nine other IPR petitions for review of the ’264 patent, filed by Lam Research
`
`
`
`2 Daniel L. Flamm is both the Patent Owner and Patent Owner’s declarant in
`this proceeding.
`
`3
`
`
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`IPR2017-00282
`Patent RE40,264 E
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`Corporation or Samsung, none of which are currently pending. See Pet. 2;
`
`Prelim. Resp. 1–2 (identifying IPR2015-01759 (institution denied);
`
`IPR2015-01764 (terminated-settled); IPR2015-01766 (institution denied);
`
`IPR2015-01768 (terminated-settled); IPR2016-00468 (institution denied);
`
`IPR2016-00469 (institution denied); and IPR2016-00470 (institution
`
`denied); IPR2016-01510 (institution denied) and; IPR2016-01512 (Final
`
`Written Decision – challenged claims unpatentable)).
`
`C. The ’264 Patent
`
`The ’264 patent, titled “Multi-Temperature Processing,” reissued
`
`April 29, 2008 from U.S. Patent Application No. 10/439,245 (“the ’245
`
`application”), filed on May 14, 2003. Ex. 1001, at [54], [45], [21], [22]. The
`
`’264 patent is a reissue of U.S. Patent No. 6,231,776 B1 (“the ’776 patent”),
`
`which issued on May 15, 2001, from U.S. Patent Application No.
`
`09/151,163 (“the ’163 application”) filed September 10, 1998. Id. at [64].
`
`The ’264 patent is directed to a method “for etching a substrate in the
`
`manufacture of a device,” where the method “provide[s] different processing
`
`temperatures during an etching process or the like.” Id. at Abstract. The
`
`apparatus used in the method is shown in Figure 1, reproduced below.
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`4
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`IPR2017-00282
`Patent RE40,264 E
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`
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`Figure 1 depicts a substrate (product 28, such as a wafer to be etched) on a
`
`substrate holder (product support chuck or pedestal 18) in a chamber
`
`(chamber 12 of plasma etch apparatus 10). Id. at 3:24–25, 3:32–33, 3:40–41.
`
`Figures 6 and 7, reproduced below, depict a temperature-controlled
`
`substrate holder and temperature control systems.
`
`
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`5
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`IPR2017-00282
`Patent RE40,264 E
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`Figures 6 and 7 depict temperature-controlled fluid flowing through
`
`substrate holder (600, 701), guided by baffles 605, where “[t]he fluid [is]
`
`used to heat or cool the upper surface of the substrate holder.” Ex. 1001,
`
`14:28–63, 16:5–67. Figure 6 also depicts heating elements 607 underneath
`
`the substrate holder, where “[t]he heating elements can selectively heat one
`
`or more zones in a desirable manner.” Id. at 15:10–26. Referring to Figure 7,
`
`the operation of the temperature control system is described as follows:
`
`The desired fluid temperature is determined by comparing the
`desired wafer or wafer chuck set point temperature to a measured
`wafer or wafer chuck temperature . . . . The heat exchanger, fluid
`flow rate, coolant-side fluid temperature, heater power, chuck,
`etc. should be designed using conventional means to permit the
`heater to bring the fluid to a setpoint temperature and bring the
`temperature of
`the chuck and wafer
`to predetermined
`temperatures within specified time intervals and within specified
`uniformity limits.
`
`Id. at 16:36–39, 16:50–67.
`
`An example of a semiconductor substrate to be patterned is shown in
`
`Figure 9, reproduced below.
`
`
`
`6
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`IPR2017-00282
`Patent RE40,264 E
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`Figure 9 depicts substrate 901 having a stack of layers including oxide layer
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`903, polysilicon layer 905, tungsten silicide layer 907, and photoresist
`
`masking layer 909 with opening 911, from the treatment method shown in
`
`Figure 10, reproduced below. Id. at 17:58–18:57.
`
`Figure 10 depicts the tungsten silicide layer being etched between
`
`points B and D at a constant temperature; the polysilicon layer being
`
`exposed between Points D and E; the polysilicon layer being etched at a
`
`constant temperature beyond point E; and the resist being ashed beyond
`
`
`
`7
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`IPR2017-00282
`Patent RE40,264 E
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`Point I. Ex. 1001, 18:58–19:64. The plasma’s optical emission at 530
`
`nanometers is monitored to determine when there is breakthrough to the
`
`polysilicon layer (Point D) and a lower etch temperature is required to etch
`
`the polysilicon layer (Point E). Id. at 19:8–24, 19:45–52.
`
`D. Illustrative Claims
`
`
`
`Of the challenged claims, claims 56 and 60 are the only independent
`
`claims at issue. Claim 56 is directed to a method of processing layers which
`
`are included in a stack of layers positioned on a substrate, and claim 60 is
`
`directed to a method for manufacturing a device comprising an integrated
`
`circuit. Claim 56 and 60, with bracketed material added,3 are reproduced
`
`below:
`
`56. A method for processing layers which are included in a
`stack of layers positioned on a substrate, the method
`comprising:
`
`[a] placing the substrate on a substrate holder;
`
`[b] sensing a substrate holder temperature;
`
`[c] etching at least a portion of a first silicon-containing layer
`in a chamber while the substrate is maintained at a
`selected first substrate temperature; and
`
`[d] etching at least a portion of a second silicon-containing
`layer in the chamber while the substrate is maintained at
`a selected second substrate temperature;
`
`[e] wherein the substrate holder is heated to a temperature
`operable to maintain at least one of the selected first and
`the selected second substrate temperatures above 49° C.,
`and the substrate temperature is changed from the first
`
`
`
`3 Although the bracketed material is not present in the text of claims 56 or
`60, for clarity and consistency, this Decision will use the bracketed
`nomenclature as utilized by both Petitioner and Patent Owner.
`
`8
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`IPR2017-00282
`Patent RE40,264 E
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`substrate
`second
`the
`to
`temperature
`substrate
`temperature with a control circuit operable to effectuate
`the changing within a preselected time period that is less
`than the overall process time associated with the etching
`the first silicon-containing layer and the second silicon-
`containing layer.
`
`60. A method for manufacturing a device comprising an
`integrated circuit, the method comprising:
`
`[a] transferring a substrate comprising a stack of layers
`including a silicide layer into a chamber, the chamber
`comprising a substrate holder;
`
`[b] sensing the substrate holder temperature;
`
`[c] heating the substrate holder with a substrate holder control
`circuit and a heating device to maintain the substrate
`holder at a temperature that is operable to effectuate a
`substrate temperature above room temperature while
`processing the substrate;
`
`[d] processing the substrate on the substrate holder at a first
`substrate temperature; and
`
`[e] processing the substrate on the substrate holder at a
`second substrate temperature to etch at least a portion of
`the silicide layer;
`
`[f] wherein the first substrate temperature is different from
`the second substrate temperature and the first substrate
`temperature is changed
`to
`the second substrate
`temperature with a substrate temperature control circuit
`within a preselected time to etch the silicide layer.
`
`9
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`IPR2017-00282
`Patent RE40,264 E
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`E. Instituted Grounds
`
`We instituted an inter partes review of claims 56–63, 70, and 71 on
`
`the following grounds of unpatentability:
`
`(1) Whether claims 56 and 58 are unpatentable under § 103(a) over
`
`the combination of Kadomura4 and Matsumura5;
`
`(2) Whether claim 57 is unpatentable under § 103(a) over the
`
`combination of Kadomura, Matsumura, and Muller6;
`
`(3) Whether claims 59–61 and 71 are unpatentable under § 103(a)
`
`over the combination of Kadomura, Matsumura, and Wang7;
`
`(4) Whether claim 62 is unpatentable under § 103(a) over the
`
`combination of Kadomura, Matsumura, Muller, and Wang;
`
`(5) Whether claims 63 and 70 are unpatentable under § 103(a) over
`
`the combination of Kadomura, Matsumura, Kikuchi8, and Wang;
`
`(6) Whether claims 56–58 are unpatentable under § 103(a) over the
`
`combination of Muller and Matsumura;
`
`(7) Whether claims 59–62 and 71 are unpatentable under § 103(a)
`
`over the combination of Muller, Matsumura, and Wang; and
`
`(8) Whether claims 63 and 70 are unpatentable under § 103(a) over
`
`the combination of Muller, Matsumura, Wang, and Kikuchi.
`
`II. DISCUSSION
`
`A. Principles of Law
`
`To prevail in challenging Patent Owner’s claims, Petitioner must
`
`demonstrate by a preponderance of the evidence that the claims are
`
`
`
`4 U.S. Patent No. 6,063,710, filed Feb. 21, 1997, issued May 16, 2000
`(Ex. 1005, “Kadomura”).
`
`10
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`unpatentable. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d). A claim is
`
`unpatentable under 35 U.S.C. § 103(a) if the differences between the
`
`claimed subject matter and the prior art are such that the subject matter, as a
`
`whole, would have been obvious at the time of the invention to a person
`
`having ordinary skill in the art. KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398,
`
`406 (2007). The question of obviousness is resolved on the basis of
`
`underlying factual determinations including: (1) the scope and content of the
`
`prior art; (2) any differences between the claimed subject matter and the
`
`prior art; (3) the level of ordinary skill in the art; and (4) objective evidence
`
`of nonobviousness, i.e., secondary considerations.9 See Graham v. John
`
`Deere Co., 383 U.S. 1, 17–18 (1966). The level of ordinary skill in the art
`
`may be reflected by the prior art of record. See Okajima v. Bourdeau, 261
`
`F.3d 1350, 1355 (Fed. Cir. 2001).
`
`B. Level of Ordinary Skill in the Art
`
`Citing Dr. Bravman’s testimony, Petitioner contends that a person of
`
`ordinary skill in the art at the relevant time (a “POSITA”) would have had
`
`(i) a Bachelor’s degree in chemical engineering, materials science
`
`
`
`5 U.S. Patent No. 5,151,871, filed Jun. 15, 1990, issued Sept. 29, 1992
`(Ex. 1003, “Matsumura”).
`6 U.S. Patent No. 5,605,600, filed Mar. 13, 1995, issued Feb. 25, 1997 (Ex.
`1002, “Muller”).
`7 U.S. Patent No. 4,992,391, filed Nov. 29, 1989, issued Feb. 12, 1991 (Ex.
`1010, “Wang”).
`8 U.S. Patent No. 5,226,056, filed Jan. 9, 1990, issued July 6, 1993 (Ex.
`1004, “Kikuchi”).
`9 The record does not contain evidence or argument of objective evidence of
`non-obviousness.
`
`11
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`IPR2017-00282
`Patent RE40,264 E
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`engineering, electrical engineering, physics, chemistry, or a similar field,
`
`and three or four years of work experience in semiconductor manufacturing
`
`or related fields; or (ii) a Master’s degree in chemical engineering, materials
`
`science engineering, electrical engineering, physics, chemistry, or a similar
`
`field, and two or three years of work experience in semiconductor
`
`manufacturing or related fields; or (iii) a Ph.D. in chemical engineering,
`
`materials science engineering, electrical engineering, physics, chemistry, or
`
`a similar field. Pet. 24–25 (citing Ex. 1006 ¶ 21).
`
`Patent Owner does not contest Petitioner’s description of the level of
`
`ordinary skill in its Response. See generally PO Resp. Based on our review
`
`of the ’264 patent, the cited prior art, and the testimony of the parties’
`
`declarants, we agree with Petitioner’s assessment of the level of ordinary
`
`skill in the art and apply it for purposes of this Decision. See Okajima, 261
`
`F.3d at 1355 (explaining that specific findings regarding ordinary skill level
`
`are not required “where the prior art itself reflects an appropriate level and a
`
`need for testimony is not shown”).
`
`C. Claim Construction
`
`The’264 patent has expired.10 For claims of an expired patent, the
`
`Board’s claim interpretation is similar to that of a district court. See In re
`
`
`
`10 The ’264 patent expired no later than December 4, 2015, which is twenty
`years after December 4, 1995, the earliest filing date of an application to
`which the ’264 claims priority. See Ex. 1001 [63]; 35 U.S.C. § 154(a)(2)
`(2012 & Supp. III 2015) (stating patent term ends twenty (20) years from the
`date on which the application for the patent was filed in the United States,
`“or, if the application contains a specific reference to an earlier filed
`application or applications under section 120, 121, 365(c), or 386(c), from
`the date on which the earliest such application was filed”).
`
`12
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`Rambus, Inc., 694 F.3d 42, 46 (Fed. Cir. 2012). Claim terms are given their
`
`ordinary and customary meaning as would be understood by a person of
`
`ordinary skill in the art at the time of the invention, and in the context of the
`
`entire patent disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257
`
`(Fed. Cir. 2007). Only those terms in controversy need to be construed, and
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`only to the extent necessary to resolve the controversy. See Vivid Techs., Inc.
`
`v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`
`For purposes of our Decision on Institution, we determined that none
`
`of the claims terms requires an explicit construction. Dec. on Inst. 10.
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`During the instituted trial, neither party disagreed with this assessment, and
`
`we again see no need to provide an express construction for any of the terms
`
`in the challenged claims.
`
`D. Priority Date for the Challenged Claims of the ’264 Patent
`
`The ’264 patent is a reissue of U.S. Patent No. 6,231,776 B1, which
`
`issued from U.S. Patent Application No. 09/151,163 (“the ’163 application”)
`
`filed on September 10, 1998. Ex. 1001, [64]. The ’163 application claims
`
`priority to both (1) U.S. Provisional Application No. 60/058,650 (“the ’650
`
`provisional application”), filed on September 11, 1997 and (2) U.S. Patent
`
`Application No. 08/567,224 (“the ’224 application”), filed on December 4,
`
`1995. Id. at [60], [63], [64], 1:11–15.
`
`Petitioner contends that the challenged claims of the ’264 patent are
`
`not entitled to claim priority to a filing date any earlier than the
`
`September 11, 1997, filing date of the ’650 provisional application, and,
`
`therefore, each of the asserted references qualifies as prior art to the
`
`challenged claims. See Pet. 9–11. Specifically, Petitioner contends that the
`
`’264 patent is not entitled to claim priority to the December 4, 1995, filing
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`13
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`date of the ’224 application because the ’224 application fails to disclose
`
`changing the temperature of a substrate on a substrate holder from a first to a
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`second substrate temperature using a measured substrate temperature
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`“within a preselected time interval” as required by independent claim 27,
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`and a “substrate temperature control circuit effectuates the change from the
`
`first substrate temperature to the second substrate temperature within a
`
`preselected time period” as required by independent claim 51. Id. at 9–10
`
`(citing Ex. 1006 ¶¶ 30–33).
`
`Patent Owner has not introduced any evidence or argument that
`
`the ’224 application provides written description support for the independent
`
`claims. See generally PO Resp. Nor does Patent Owner contend that any of
`
`the asserted references are not prior art to the ’264 patent. Evaluating
`
`Petitioner’s unchallenged arguments, we determine that the challenged
`
`claims of the ’264 patent are not entitled to claim priority to the December 4,
`
`1995, filing date of the ’224 application. As a consequence, we find that
`
`Kadomura, which was filed on February 21, 1997, and the remaining
`
`asserted references, each of which issued before the September 11, 1997,
`
`filing date of the ’650 provisional application, qualify as prior art to the
`
`challenged claims of the ’264 patent.
`
`E. Asserted Art
`
`1. Kadomura
`
`Kadomura, titled “Method and Apparatus for Dry Etching with
`
`Temperature Control,” discloses, inter alia, a multi-temperature process for
`
`etching portions of a semiconductor wafer. Ex. 1005 at [54], [57]. The
`
`etching tool of Kadomura shown in Figure 4 has a wafer stage for holding
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`14
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`IPR2017-00282
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`the wafer/substrate during processing, thermometer for measuring wafer
`
`temperature, and a control device, having a PID controller, for controlling
`
`the temperature of wafer based on temperature measurements from the
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`thermometer. See id. at 11:36–59, 12:37–48, Fig. 4. Kadomura adjusts the
`
`wafer temperature by adjusting the temperature of wafer stage 12, using a
`
`heater or chiller 17. See id. at 10:7–10 (stating the change in temperature of
`
`specimen W is controlled by “the cooling means and the heater disposed to
`
`the stage 12”); see also id. at 12:37–38 (the “cooling degree for the
`
`specimen [] is controlled by the flow rate of the coolant supplied from the
`
`chiller”). The temperature sensed by thermometer 18 is detected by a
`
`feedback control device (feedback control means) 25 comprising a
`
`[proportional-integral-derivative] PID controller. Id. at 12:39–43. Kadomura
`
`explains that feedback control device 25 controls the cryogenic valve “to
`
`obtain a gas coolant flow rate previously determined by experiment or
`
`calculation based on the difference between the detected temperature and the
`
`predetermined temperature for the specimen.” Id. at 12:43–49.
`
`Kadomura discloses several examples of multi-temperature etch
`
`processes. For example, one process includes a first step of etching silicide
`
`and polysilicon at room temperature (20°C) and a second step of etching
`
`polysilicon at a lower temperature (-30°C). Id. at 6:18–7:7; Figs. 1A–1C. In
`
`between these etching steps, gases remaining in the diffusion chamber are
`
`exhausted and the etching gas used in the second step is introduced; the gas
`
`is stabilized and the inside of the diffusion chamber is controlled to a
`
`constant pressure. Id. at 6:36–44. During “a series of such operations, that is
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`directly after the completion of the etching of the first step,” gas coolant at
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`-140°C from the chiller is supplied to the wafer stage to rapidly cool the
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`15
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`wafer. Id. at 6:44–51. The temperature of the wafer reaches -30 ºC “within a
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`short period of time of about 30 sec by such rapid cooling.” Id. at 6:52–55.
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`After completing these two steps, a heater within substrate holder
`
`stage 12 returns the wafer specimen temperature back up to 20 ºC. Id. at
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`7:31–47. The tool then repeats the same two-temperature etch process. Id. at
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`6:63–7:7, 7:31–47.
`
`In another embodiment, the first etching step occurs at a low
`
`temperature (i.e., -30ºC) and the second etching step is applied at a much
`
`higher temperature (i.e., 50ºC). Id. at 9:54–10:27. A control mechanism for
`
`the cooling means and the heater disposed to the wafer stage are controlled
`
`to rapidly heat the specimen W between the etching steps. See id. at 10:7–
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`10. The temperature of the wafer reaches 50ºC “within a short period of time
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`of about fifty (50) seconds.” Id. at 10:11–27.
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`2. Matsumura
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`Matsumura generally relates to heat-processing semiconductor wafers
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`and, in particular, to controlling the temperature of a semiconductor wafer
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`during processing. See Ex. 1003, 1:8–13; see also id. at 2:60–65 (stating one
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`objective is to provide a “simpler method of heat-processing semiconductor
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`devices whereby temperatures of the semiconductor devices can be
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`controlled at devices-heating and -cooling times so as to accurately control
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`their thermal history curve”).
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`Matsumura’s temperature control system uses a central processing
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`unit (“CPU”) having a PID controller that stores “as a predetermined recipe,
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`information showing a time-temperature relationship and applicable for
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`either heating [a wafer] to a predetermined temperature for a predetermined
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`period of time or cooling the [wafer] from a predetermined temperature over
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`a predetermined period of time.” See id. at 3:1–7, 5:64–6:6, 8:56–62; see
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`also id. at [57] (stating a “control system controls either the heating of the
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`wafer or the cooling thereof, or both, in accordance with the detected
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`temperature signal and the [stored] information”).
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`An example of a predetermined recipe is shown in Figure 9 below.
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`See id. at 8:56–57.
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`Figure 9, shown above, is a diagram showing a “recipe relating to a thermal
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`history curve of a wafer-stage,” showing temperature as a function of time.
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`See id. at 4:42–43; see also id. at 8:56–68 (stating “Points P10 to P19 shown
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`in figure 9 are set in the recipe to surely reproduce the thermal history curve
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`of the wafer”). The information “relating to temperatures and times at these
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`points P10 to P19 is inputted as a command temperature table to the CPU.”
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`Id. at 8:59–62.
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`Figure 5A, reproduced below, is a schematic diagram of an adhesion
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`unit included in a resist processing system of Matsumura that includes wafer
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`stage 12 for heating and cooling wafer W in accordance with recipes
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`inputted into a CPU. See id. at 4:28–29, 5:13–17, 6:6–9.
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`Figure 5A, reproduced above, depicts adhesion unit 42 having wafer-stage
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`12 that can heat and cool the semiconductor wafers (e.g., wafer W). Id. at
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`5:14–16. Recipes, including heating and other conditions, are inputted to the
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`CPU by keyboard 20a. Id. at 6:6–9. Thermometer 24, which has thermal
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`sensor attached to thin film 14, is attached to a control system 20. See id. at
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`5:57–6:4. Based on the recipe and temperature detecting signal, control
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`system 20 controls the amount of coolant supplied from the cooling system
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`to cooling jacket 22 under stage 12 and the current applied to conductive
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`thin film 14 to raise the temperature of the wafer. Id. at 5:64–6:61.
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`Matsumura states that, although “the present invention has been
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`applied to the adhesion and baking processes for semiconductor wafers in
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`the above-described embodiments . . . , it can also be applied to any of the
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`ion implantation, [chemical vapor deposition (“CVD”)], etching and ashing
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`processes.” Id. at 10:3–7.
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`3. Muller
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`Muller is directed to methods of shaping etch profiles by controlling
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`wafer temperature using an electrostatic chuck and coolant circulating
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`through a cathode and by changing the pressure of the gas filled in the gaps
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`between the wafer and the cathode. Ex. 1002 at [54], Abstract, 1:7–12, 1:44–
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`64, 4:51–5:25. Figure 4 of Muller, which depicts an example of an apparatus
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`used to accomplish the multi-temperature etching methods, is reproduced
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`below.
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`Figure 4 depicts wafer 104, electrostatic chuck 105, cathode 106, and gas
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`filled gap 110 between cathode 106 and wafer 104. Id. at 4:33–54.
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`Muller teaches that the change in taper angle of etched trenches
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`correlates with increasing wafer temperature during the etching processes.
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`Ex. 1002, 3:33–66, Figs. 1, 2. Muller explains that changing pressure of the
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`gas filled in the gaps between the wafer and cathode, which can be
`
`accomplished in a very short period of time, results in an immediate effect
`
`on wafer temperature. Id. For example, wafer temperature can be increased
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`by approximately 50ºC over a time of “several seconds” during etching. Id.
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`at 4:64–5:25, 5:41–48.
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`In one example, Muller teaches performing an initial etch at either
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`125ºC or 145ºC. Id. at 3:45–52, 3:56–66. The two etching temperature
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`examples correspond to two different coolant temperatures. For example,
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`use of a cathode coolant at 10ºC results in a wafer temperature of
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`approximately 125°C, while use of a cathode coolant at 30ºC results in a
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`wafer temperature of approximately 145ºC. Id. at 3:45–52. Figure 3 below
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`shows the wafer temperature at the two cathode coolant temperatures as a
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`function of time.
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`Figure 3 depicts a graph illustrating the change in wafer temperature for
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`various coolant temperatures as a function of etch time.
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`In another example of an etching process, the gas-filled gap is
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`pressurized for a first time period and then the pressure in the gap is rapidly
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`changed to a second pressure for a second period of time. Id. at 4:64–5:3.
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`Then, the gas pressure underneath the chuck is changed to increase wafer
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`temperature by 50ºC in “several seconds” during etching. Id. at 4:64–5:25,
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`5:41–48. In this example, using a 30°C coolant, the initial pressure is
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`maintained for 70 seconds, after which the gap pressure is decreased for the
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`remaining 6 minutes of etch time. Id. at 5:26–33.
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`4. Kikuchi
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`Kikuchi is directed to methods for plasma ashing a resist film by
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`initially controlling the temperature of the substrate below that at which
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`explosion of the resist film occurs until after a surface portion of a resist film
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`has been removed. Ex. 1004, Abstract. Kikuchi describes ashing a wafer’s
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`photoresist film at two sequential temperatures using either infrared heat
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`lamp 5 or hot plate 7 to raise the temperature, and thermometers 10, 66 to
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`measure the wafer and hot plate temperatures. See, e.g., id. at 1:56–2:3,
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`7:20–34, 7:62–68, 8:8–14, 11:6–9, Figs. 12, 13. Figure 1 of Kikuchi is
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`reproduced below.
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`Figure 1 depicts a “conventional ashing method” in which a substrate is
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`placed on rack 8 and is heated by infrared lamps 5 to a predetermined
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`temperature in about 5 seconds (as shown by curve A in Figure 3). See id. at
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`1:56–60. The temperature of the substrate is controlled by infrared
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`thermometer 9. Id. at 1:56–65, 4:62–63. Kikuchi explains that in this
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`embodiment, it is difficult to coat the resist film 11 on only the front surface
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`of substrate 1 as film will also be deposited on the rear surface of substrate
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`1. See id. at 2:47–61. Kikuchi states that if substrate 1 is heated in contact
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`with hot plate 7 to remove the resist film by ashing, hot plate 7 prevents the
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`reactive radicals from working on that resist film and the resist film may
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`remain on the rear surface of substrate 1. See id. at 2:61–67; Figs. 8, 9.
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`Figure 11, shown below, depicts a sectional side view of an embodiment of
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`the invention of Kikuchi.
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`Figure 11 depicts a semiconductor substrate (wafer) 1, thermometer
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`10, pins 16, and heating means 51 having hot plate 7, inside of vacuum
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`treatment chamber 4. Id. at 7:19–33. Kikuchi describes using the pins to
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`suspend the substrate being ashed above the hot plate to remove a surface
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`layer of photoresist, lowering pins 16 to place the substrate on the hot plate,
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`and then raising the temperature to ash the remaining portion of the
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`photoresist at a high temperature. Id. at 8:1–14; see also Ex. 1006 ¶ 86.
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`Kikuchi describes etching a photoresist over a range of temperatures,
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`with an initial step of 70°C–160°C and a rapid increase to 200°C over a time
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`period of 5 to 10 seconds. See, e.g., Ex. 1004, 2:37–46, 3:33–44, 5:46–54,
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`Figs. 12, 13.
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`5. Wang
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`Wang is directed to a process for forming a floating gate field-effect
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`transistor having a multi-layered stack. Ex. 1010, [57]. Figure 3 of Wang is
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`reproduced below.
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`Figure 3 illustrates a multi-layer stack that includes oxide layers 16
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`and 24 and silicide layer 20, which is in between polysilicon layers 18 and
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`22. Id. at 4:19–23, Fig. 3.
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`F. Asserted Obviousness of Independent Claim 56
`over Kadomura and Matsumura and of Independent Claim 60 over
`Kadomura, Matsumura, and Wang
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`Claim 56 is directed to a method of processing layers which are
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`included in a stack of layers positioned on a substrate. In general, claim 56
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`requires [a]11 placing a substrate on the substrate holder, [b] sensing a
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`substrate holder temperature, [c] etching a portion of a layer while the
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`substrate is maintained at a selected first substrate temperature, [d] etching a
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`second portion of the layer at a selected second substrate temperature. Claim
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`56 also requires [e] that the substrate holder is heated to maintain at least the
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`first or second selected substrate temperatures above 49ºC and that the
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`
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`11 For clarity and consistency, the bracketed letters refer to claim elements as
`identified in Section I.D.
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`substrate temperature is changed from the first substrate temperature to the
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`second substrate temperature with a control circuit operable to effectuate the
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`temperature change “within a preselected time period” that is less than the
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`overall process t
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