UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`AND MICRON TECHNOLOGY, INC.,
`Petitioners,
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`v.
`
`DANIEL L. FLAMM,
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`Patent Owner.
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`PTAB Case No. IPR2017-00281
`Patent No. RE40,264 E
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`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. RE40,264 E
`
`Claims 37-50 & 67
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`

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`TABLE OF CONTENTS
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`Page
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`
`I.
`Introduction ..................................................................................................... 1
`II. Mandatory notices .......................................................................................... 2
`A.
`Real party in interest............................................................................. 2
`B.
`Related matters ..................................................................................... 2
`C.
`Notice of counsel and service information ........................................... 2
`III. Requirements for inter partes review ............................................................. 4
`A. Ground for standing ............................................................................. 4
`B.
`Identification of challenge .................................................................... 5
`IV. Overview of the ’264 patent ........................................................................... 5
`A.
`The claims recite two-temperature etch processes and add only
`conventional features ............................................................................ 7
`The earliest priority date for the ’264 patent is September 1997 ......... 9
`B.
`V. Overview of the prior art .............................................................................. 10
`A. Kadomura (Ex. 1005) ......................................................................... 11
`B. Matsumura (Ex. 1003) ........................................................................ 12
`C.
`Kikuchi (Ex. 1004) ............................................................................. 16
`D. Muller (Ex. 1002) ............................................................................... 18
`E. Moslehi ’824 (Ex. 1010) .................................................................... 20
`F.
`Oka (Ex. 1011) ................................................................................... 23
`G.
`Level of ordinary skill in the art ......................................................... 24
`VI. Claims 37-50 and 67 of the ’264 patent are unpatentable ............................ 24
`A. Ground 1: Claims 37-46 are obvious over Kadomura and
`Matsumura .......................................................................................... 25
`1.
`Claim 37 ................................................................................... 25
`2.
`Claim 38 ................................................................................... 40
`3.
`Claim 39 ................................................................................... 40
`4.
`Claim 40 ................................................................................... 41
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`-i-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`B.
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`5.
`Claim 41 ................................................................................... 45
`Claim 42 ................................................................................... 46
`6.
`Claim 43 ................................................................................... 46
`7.
`Claim 44 ................................................................................... 47
`8.
`Claim 45 ................................................................................... 48
`9.
`10. Claim 46 ................................................................................... 49
`Ground 2: Claims 40, 42, 45, 49, and 67 are obvious over
`Kadomura, Matsumura, and Muller ................................................... 49
`1.
`Claim 37 ................................................................................... 49
`2.
`Claim 40 ................................................................................... 49
`3.
`Claim 42 ................................................................................... 51
`4.
`Claim 45 ................................................................................... 52
`5.
`Claim 49 ................................................................................... 53
`6.
`Claim 67 ................................................................................... 55
`Ground 3: Claim 50 is obvious over Kadomura, Matsumura,
`and Kikuchi ........................................................................................ 56
`1.
`Claim 37 ................................................................................... 56
`2.
`Claim 50 ................................................................................... 56
`D. Ground 4: Claims 37-46, 50, and 67 are obvious over Kikuchi
`and Matsumura ................................................................................... 58
`1.
`Claim 37 ................................................................................... 58
`2.
`Claim 38 ................................................................................... 67
`3.
`Claim 39 ................................................................................... 67
`4.
`Claim 40 ................................................................................... 67
`5.
`Claim 41 ................................................................................... 70
`6.
`Claim 42 ................................................................................... 71
`7.
`Claim 43 ................................................................................... 72
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`C.
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`-ii-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`
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`E.
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`F.
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`8.
`Claim 44 ................................................................................... 73
`Claim 45 ................................................................................... 73
`9.
`10. Claim 46 ................................................................................... 74
`11. Claim 50 ................................................................................... 74
`12. Claim 67 ................................................................................... 76
`Ground 5: Claims 41 and 49 are obvious over Kikuchi,
`Matsumura, and Muller ...................................................................... 76
`1.
`Claim 37 ................................................................................... 76
`2.
`Claim 41 ................................................................................... 76
`3.
`Claim 49 ................................................................................... 78
`Ground 6: Claims 37 and 47-48 are obvious over Moslehi
`’824, Matsumura, and Oka ................................................................. 81
`1.
`Claim 37 ................................................................................... 81
`2.
`Claim 47 ................................................................................... 93
`3.
`Claim 48 ................................................................................... 94
`VII. Conclusion .................................................................................................... 94
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`-iii-
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`
`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
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`EXHIBIT LIST AND TABLE OF ABBREVIATIONS AND CONVENTIONS
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`Petitioner’s Exhibits
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`Exhibit
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`Description
`
`Ex. 1001 U.S. Patent No. RE40,264 (“’264 patent”)
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`Ex. 1002 U.S. Patent No. 5,605,600 (“Muller”)
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`Ex. 1003 U.S. Patent No. 5,151,871 (“Matsumura”)
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`Ex. 1004 U.S. Patent No. 5,226,056 (“Kikuchi”)
`
`Ex. 1005 U.S. Patent No. 6,063,710 (“Kadomura”)
`
`Ex. 1006 Declaration of Dr. John Bravman in Support of Petition for Inter
`Partes Review of U.S. Patent No. RE40,264
`
`Ex. 1007 U.S. Patent Application No. 08/567,224 (“’224 application”)
`
`Ex. 1008 Wright, D.R. et al., A Closed Loop Temperature Control System for
`a Low-Temperature Etch Chuck, Advanced Techniques for
`Integrated Processing II, Vol. 1803 (1992), pp. 321–329 (“Wright”)
`
`Ex. 1009 U.S. Patent No. 5,711,849 (“’849 patent”)
`
`Ex. 1010 U.S. Patent No. 5,446,824 (“Moslehi ’824”)
`
`Ex. 1011 U.S. Patent No. 6,235,563 (“Oka”)
`
`Ex. 1012 U.S. Patent No. 5,628,871 (“Shinagawa”)
`
`Ex. 1013 U.S. Patent No. 5,393,374 (“Sato”)
`
`Ex. 1014
`
`PTAB Decision Denying Institution of Inter Partes Review, Lam
`Research Corp. v. Daniel L. Flamm, IPR2016-00470, Paper 6 (July
`1, 2016)
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`
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`-iii-
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
`
`EXHIBIT LIST AND TABLE OF ABBREVIATIONS AND CONVENTIONS
`(continued)
`
`PTAB Institution of Inter Partes Review, Lam Research Corp. v.
`Daniel L. Flamm, IPR2015-01768, Paper 7 (February 24, 2016)
`
`Ex. 1015
`
`Ex. 1016
`
`PTAB Institution of Inter Partes Review, Lam Research Corp. v.
`Daniel L. Flamm, IPR2015-01764, Paper 7 (February 24, 2016)
`
`Ex. 1017 U.S. Patent No. 5,242,536 (“Schoenborn”)
`
`Ex. 1018
`
`Petition for Inter Partes Review of U.S. Patent No. RE40,264 E
`Fourth Petition, Lam Research Corp. v. Daniel L. Flamm, IPR2015-
`01768, Paper 1 (August 18, 2015)
`
`Ex. 1019 U.S. Patent No. 5,174,856 (“Hwang”)
`
`Ex. 1020 U.S. Patent No. 4,331,485 (“Gat”)
`
`Ex. 1021 Declaration of Rachel J. Watters regarding Exhibit 1008
`
`Other Abbreviations and Conventions
`Petitioners
`Intel Corporation, GLOBALFOUNDRIES U.S., Inc., and Micron
`Technology, Inc.
`Daniel Flamm
`
`Patent
`Owner
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`-iv-
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
`
`I.
`
`Introduction
`
`Dr. Daniel Flamm sued Petitioners Intel Corporation,
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`GLOBALFOUNDRIES U.S., Inc., and Micron Technology, Inc. for allegedly
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`infringing U.S. Patent No. RE40,264 E. Petitioners request that the Board institute
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`5
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`an IPR trial on claims 37-50 and 67 of the ’264 patent because prior art not before
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`the examiner during prosecution renders those claims unpatentable.
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`The ’264 patent is titled “Multi-Temperature Processing.” The challenged
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`claims require etching a substrate (such as a semiconductor wafer) at multiple
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`temperatures and with preselected processing times. Several references that were
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`10
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`not previously before the patent office show that multi-temperature etching and
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`predetermined process times were known long before the date of the alleged
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`invention. The various claims also tack on: conventional semiconductor tool
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`components (temperature sensors and control circuits), longstanding processing
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`techniques (etching, deposition), well-known heat transfer methods (from a
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`15
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`substrate to a holder or vice versa, using gas pressure or radiation), or
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`straightforward temperature ranges (above room temperature, 300ºC-500ºC). But
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`there was nothing unexpected or inventive about those trivial variations.
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`Each of the challenged claims is a combination of well-known elements
`
`arranged in a conventional way to produce predictable results. The challenged
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`20
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`claims are obvious.
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`-1-
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`
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
`
`
`II. Mandatory notices
`A. Real party in interest
`The real parties in interest are Intel Corporation, GLOBALFOUNDRIES,
`
`Inc., GLOBALFOUNDRIES U.S., Inc., and Micron Technology, Inc.
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`5
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`B. Related matters
`Patent Owner has asserted the ’264 patent against Petitioners and others in
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`lawsuits (now stayed) in the Northern District of California: Case Nos. 5:16-cv-
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`1579-BLF, 5:16-cv-01578-BLF, 5:16-cv-1581-BLF, 5:16-cv-1580-BLF, and 5:16-
`
`cv-02252-BLF. In addition, Lam Research Corporation has filed a declaratory
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`10
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`judgment action against Patent Owner on the ’264 patent (N.D. Cal. Case No.
`
`5:15-cv-01277-BLF) and IPR petitions on the ’264 patent (IPR2015-01759;
`
`IPR2015-01764; IPR2015-01766; IPR2015-01768; IPR2016-00468; IPR2016-
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`00469; and IPR2016-00470). Samsung Electronics, Co., Ltd. has filed IPR
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`petitions on the ’264 patent (IPR2016-01510 and IPR2016-01512).
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`15
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`C. Notice of counsel and service information
`Petitioners’ respective counsel are:
`
`Lead Counsel
`
`Jonathan McFarland
`Reg. No. 61,109
`PERKINS COIE LLP
`1201 Third Avenue, Suite 4900
`Seattle, WA 98101
`206-359-8000 (phone)
`206-359-9000 (fax)
`Attorney for Intel Corporation
`
`Back-Up Counsel
`Chad Campbell
`Pro hac vice to be submitted
`Tyler Bowen
`Reg. No. 60,461
`PERKINS COIE LLP
`2901 N. Central Ave, Suite 2000
`Phoenix, AZ 85012
`602-351-8000 (phone)
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`
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`-2-
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
`
`
`602-648-7000 (fax)
`Attorneys for Intel Corporation
`
`Daniel Keese
`Reg. No. 69,315
`PERKINS COIE LLP
`1120 NW Couch St., 10th Floor
`Portland, OR 97209
`503-727-2000 (phone)
`503-727-2222 (fax)
`Attorney for Intel Corporation
`
`Jeremy Jason Lang
`Registration No. 73,604
`WEIL, GOTSHAL & MANGES LLP
`201 Redwood Shores Parkway
`Redwood Shores, CA 94065
`650-802-3237 (phone)
`650-802-3100 (fax)
`Attorney for Micron Technology, Inc.
`
`Jared Bobrow
`Pro hac vice to be submitted
`WEIL, GOTSHAL & MANGES LLP
`201 Redwood Shores Parkway
`Redwood Shores, CA 94065
`650-802-3034 (phone)
`650-802-3100 (fax)
`Attorney for Micron Technology, Inc.
`
`David M. Tennant
`Registration No. 48,362
`WHITE & CASE LLP
`701 Thirteenth Street, NW
`Washington, DC 20005-3807
`202-626-3600 (phone)
`202-639-9355 (fax)
`Attorney for GLOBALFOUNDRIES
`U.S., Inc.
`
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`-3-
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
`
`
`Nathan Zhang
`Registration No. 71,401
`WHITE & CASE LLP
`3000 El Camino Real
`5 Palo Alto Square, 9th Floor
`Palo Alto, CA 94306
`650-213-0300 (phone)
`650-213-8158 (fax)
`Attorney for GLOBALFOUNDRIES
`U.S., Inc.
`
`Petitioners consent to electronic service. All services and communications
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`to the above attorneys can be sent to: Intel-Flamm-Service-IPR@perkinscoie.com;
`
`micron.flamm.service@weil.com; and WCGlobalFoundries-
`
`FlammTeam@whitecase.com. A Power of Attorney for Petitioners will be filed
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`5
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`concurrently with this Petition.
`
`III. Requirements for inter partes review
`A. Ground for standing
`The ’264 patent qualifies for IPR, and Petitioners are not barred.1
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`
`
` 1
`
` Patent Owner did not name Petitioners in an infringement complaint until January
`
`15, 2016, and the court did not issue summonses for purposes of service until
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`January 21, 2016. N.D. Cal. Case No. 5:15-cv-01277-BLF, Dkts. 50, 58, 60 & 61.
`
`Patent Owner did not serve any Petitioner with the complaint before January 21,
`
`2016.
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
`
`
`Identification of challenge
`
`B.
`Claims 37-50 and 67 should be cancelled as obvious based on:
`
`Challenged Claims
`Claims 37-46
`Claims 40, 42, 45, 49,
`67
`Claim 50
`
`Claims 37-46, 50, 67
`Claims 41, 49
`
`Claims 37, 47, 48
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`6
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`Ground References
`1
`Kadomura & Matsumura (Exs. 1003, 1005)
`2
`Kadomura, Matsumura, & Muller (Exs. 1002-
`1003, 1005)
`Kadomura, Matsumura, & Kikuchi (Exs. 1003-
`1005)
`Kikuchi & Matsumura (Exs. 1003-1004)
`Kikuchi, Matsumura, & Muller (Exs. 1002-
`1004)
`Moslehi ’824, Oka, & Matsumura (Exs. 1003,
`1010-1011)
`
`3
`
`4
`5
`
`Wright, Sato, Shinagawa, Hwang, and other references illustrate the state of
`
`the art at the time of the alleged invention. Ariosa Diagnostics v. Verinata Health,
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`5
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`Inc., 805 F. 3d 1359, 1365 (Fed. Cir. 2015) (“Art can legitimately serve to
`
`document the knowledge that skilled artisans would bring to bear in reading the
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`prior art identified as producing obviousness.”) (citation omitted). None of the
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`above references was before the patent office during the examination leading to
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`the ’264 patent. Petitioners further rely on the Declaration of Dr. John Bravman
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`10
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`(Ex. 1006) and other supporting evidence in Petitioners’ exhibit list.
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`IV. Overview of the ’264 patent
`The ’264 patent issued April 29, 2008 from a reissue application filed May
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`14, 2003. The sole inventor is Daniel L. Flamm. The patent discloses processing
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`(e.g., etching) a semiconductor wafer at two different temperatures in a single tool
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
`
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`chamber. (Ex. 1001, 2:10-12, 18:54-56.) Specifically, the patent describes
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`temperature control system 700, shown in Figure 7 below. (Id., 15:65-66.) That
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`system heats or cools wafer chuck 701 (purple), which holds a wafer during
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`processing. (Id., 16:3-5.) The control system measures wafer and chuck
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`5
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`temperatures, and a controller (not shown in Figure 7) increases or lowers
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`temperatures to match desired levels using a heater (red) and fluid (blue) from
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`reservoir 713. (Id., 14:62-63, 15:10-13, 16:3-19, 16:36-46, Fig. 6.) Temperature
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`control system 700 “us[es] conventional means” to change temperatures “to pre-
`
`determined temperatures within specific time intervals….” (Id., 16:60-67, 18:22-
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`10
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`26; Ex. 1006 ¶¶42-49.)
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
`
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`Figure 10 below plots changes in temperature against processing time. (Ex.
`
`1006 ¶¶50-51.)
`
`
`A. The claims recite two-temperature etch processes and add only
`conventional features
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`5
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`Independent method claim 37 recites placing a substrate (e.g., wafer) with a
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`film onto a substrate holder (e.g., chuck) and performing “film treatments” on the
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`substrate at two different selected temperatures in the same chamber. The claim
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`also recites temperature control systems for the substrate and substrate holder that
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`10
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`include a “temperature sensor” and a “control circuit” for adjusting temperature by
`
`heat transfer. The substrate temperature control circuit changes a “selected first
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`substrate temperature” to a “selected second substrate temperature.” That change
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
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`must occur within a “preselected time period.” Claim 37 also requires heating the
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`substrate holder to “above room temperature” during one of the film treatments.
`
`(Ex. 1006 ¶¶25-26.)
`
`Dependent claims 38-50 and 67 recite minor, conventional variations to the
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`5
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`general process outlined above:
`
`• using the same circuit to control substrate and substrate holder
`
`temperature (38, 39);
`
`• treating a film with “the substrate temperature being less than the
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`substrate holder temperature” (40);
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`10
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`• treating film portions with different “materials composition[s]” (41);
`
`• treating a film by transferring heat “from the substrate holder to the
`
`substrate” (42), including while maintaining substrate holder
`
`temperature “above room temperature” (44);
`
`• treating a film by transferring heat “from the substrate to the substrate
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`15
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`holder” (43);
`
`• treating a film by transferring heat to the substrate holder with the
`
`substrate holder control circuit, while the substrate holder control
`
`circuit maintains substrate holder temperature “above room
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`temperature” (45);
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`20
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`• treating a film using etching (46);
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
`
`
`• treating a film using “chemical vapor deposition” (47);
`
`• treating a film at 300ºC-500ºC (48);
`
`• transferring heat based on “pressure of a gas behind the substrate”
`
`(49);
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`5
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`• transferring heat based on “radiation” (50); and
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`• transferring heat “from the substrate holder with a heat transfer device”
`
`(67).
`
`The earliest priority date for the ’264 patent is September 1997
`
`B.
`For purposes of this Petition, September 11, 1997 is the earliest possible
`
`10
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`priority date for the challenged claims. Although the ’264 patent also recites a
`
`priority claim to U.S. Patent Application No. 08/567,224, filed on December 4,
`
`1995 (Ex. 1007), that date is unsupportable because the ’224 application did not
`
`disclose the claimed subject matter.2
`
`For example, claim 37 requires changing the temperature of a substrate from
`
`15
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`“the selected first substrate temperature to the selected second substrate
`
`
`
` 2
`
` In earlier IPRs, the Board found that September 11, 1997 is the earliest priority
`
`date to which the challenged claims are entitled. (Ex. 1014, 10-12.) Although
`
`unimportant to this Petition, Petitioners do not concede that the claims are entitled
`
`to priority as of September 11, 1997.
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
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`temperature within a preselected time period.” Yet, the ’224 application failed to
`
`disclose changing temperature “within a preselected time period,” much less using
`
`the same substrate holder. (Ex. 1006 ¶29.) Claim 37 also requires a “substrate
`
`temperature control system” that includes a substrate temperature sensor. While
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`5
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`the ’224 application disclosed a thermocouple to measure the temperature of the
`
`substrate holder, it did not describe any substrate temperature sensor. (Id. ¶¶30-31.)
`
`V. Overview of the prior art
`As Kadomura, Matsumura, Kikuchi, Muller, Moslehi ’824, and Oka
`
`illustrate, multi-temperature wafer processing in a chamber was well known in the
`
`10
`
`prior art. Those references disclosed the two-temperature etching processes recited
`
`in independent claim 37 and the minor variations in its dependents. (Id. ¶¶34-41.)
`
`In particular, the references disclosed controlling temperature changes (Ex.
`
`1002, Abstract; Ex. 1003, Abstract, 1:8-13; Ex. 1005, Title, Abstract; Ex. 1010
`
`4:58-5:1, 5:24-26, 7:3-16; Ex. 1011, 21:22-29) through heating (Ex. 1004, 7:25-34;
`
`15
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`Ex. 1005, 11:42-47; Ex. 1010, Abstract, 1:9-15, 5:24-26; Ex. 1011, 20:66-21:17)
`
`and cooling (Ex. 1002, 4:51-5:25; Ex. 1003, 6:20-32; Ex. 1005, 11:42-59; Ex. 1011,
`
`23:11-16), and rapid temperature changes to minimize potential processing delays
`
`(Ex. 1002, 5:17-25, 6:66-7:8; Ex. 1003, 7:50-53, Figs. 8-9; Ex. 1004, Abstract,
`
`7:62-8:14; Ex. 1005, 5:18-26; Ex. 1010, 4:58-5:1, 5:24-26; Ex. 1011, 23:11-16).
`
`20
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`The references disclosed etching or deposition tools with sensors and controllers to
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
`
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`measure temperature and regulate temperature changes. (Ex. 1003, 6:20-32; Ex.
`
`1005, 10:37-48; Ex. 1008, 321; Ex. 1010, 5:4-9, 7:3-16, 10:1-9.) The art also
`
`disclosed using processing recipes to pre-program control systems to process
`
`wafers at particular times or temperatures and to change temperatures within
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`5
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`preselected times. (Ex. 1003, 3:1-16, 5:58-6:2, 7:19-32, 8:25-35, 8:56-68, Figs. 8-
`
`9; Ex. 1010, 7:3-16; Ex. 1006 ¶¶70-72.)
`
`A. Kadomura (Ex. 1005)
`Kadomura was filed in February 1997. Like the ’264 patent, Kadomura
`
`disclosed a multi-temperature process for etching portions of a wafer. (Ex. 1006
`
`10
`
`¶¶57-67.) As shown in annotated Figure 4 below, Kadomura disclosed an etching
`
`tool with a heater (not explicitly shown but represented in red) in wafer holder
`
`stage 12 (purple), a chiller 17 (blue) for cooling stage 12, a thermometer 18
`
`(yellow) for measuring wafer temperature, and a control device 25 (orange) for
`
`controlling the temperature of wafer W (green) based on temperature
`
`15
`
`measurements from thermometer 18. (Ex. 1005, 11:36-59, 12:37-48.) Kadomura
`
`adjusted the wafer’s temperature by changing the temperature of stage 12. (Id.,
`
`3:23-49.)
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00281)
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`
`
`Kadomura also disclosed specific examples of multi-temperature etching
`
`processes, including etching at and above room temperature (20ºC, 50ºC) and
`
`changing etching temperature within about 30 or 50 seconds. (Id., 6:18-7:7, 7:58-
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`5
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`8:64, 9:33-10:27.)
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`B. Matsumura (Ex. 1003)
`Matsumura issued in September 1992. Like Kadomura, Matsumura
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`disclosed multi-temperature wafer processing in a chamber. In addition,
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`Matsumura disclosed the well-known practice of using recipes to preselect process
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`parameters such as processing temperatures and temperature change times. (Ex.
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`1006 ¶¶70, 77-78, 158-161.) Matsumura also disclosed the use of a substrate
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`holder temperature sensor with predetermined time-temperature processing recipes.
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`As in annotated Figure 5A, Matsumura taught a processing tool with
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`thermometer 24 and sensor 25 (yellow) for measuring the temperature of wafer
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`holding stage 12; control system 20 (orange) for managing temperature changes;
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`conductive thin film 14 (red) in stage 12 (purple) to heat wafer W (green); and
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`cooling system 23 (blue) for cooling the wafer. (Ex. 1003, 5:60-63, 5:68-6:2, 8:18-
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`35.)
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`Substrate holder temperature sensors, like Matsumura’s, were well known in
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`the prior art. (Ex. 1004, 2:1-3; Ex. 1006 ¶¶37, 75; Ex. 1008, 321; Ex. 1010, 4:40-
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`45, 10:1-9.) In addition, Wright, a paper published in 1992, disclosed a processing
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`tool that used two separate sensors to measure the temperature of the wafer and the
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`wafer holder. (Ex. 1008, 321 (“The system employs an optical fluorescence probe
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`on the chuck (a second probe monitors the wafer temperature as well)….”).)
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`Wright’s Figure 6 below shows sensor measurements for the wafer and the chuck
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`over time.
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`Likewise, using recipes to preselect temperature changes and other
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`processing conditions was well known in semiconductor manufacturing. (Ex. 1006
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`¶161.) Matsumura’s control system 20 followed “predetermined recipe[s]” that
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`specified temperatures, processing times, and temperature change times. (Ex. 1003,
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`3:1-7 (“storing, as a predetermined recipe, information showing a time-
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`temperature relationship and applicable for either heating the object to a
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`predetermined temperature for a predetermined period of time or cooling the object
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`from a predetermined temperature over a predetermined period of time, or for
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`both….”) (emphasis added), 3:14-16 (“controlling either the heating of the object
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`or the cooling thereof, or both, in accordance with the detected temperature and the
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`information”).) Matsumura’s Figure 9 (below) charts a sample recipe with
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`multiple preselected processing temperatures (y-axis) and temperature change
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`times (x-axis). Matsumura expressly taught that its recipe-based temperature
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`control techniques could be used in etching processes. (Id., 10:3-7.)
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`C. Kikuchi (Ex. 1004)
`Kikuchi (issued July 1993) also disclosed multi-temperature etching on a
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`substrate holder within a chamber. (Ex. 1006 ¶¶80-85.) Kikuchi described ashing3
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`a wafer’s photoresist film at two temperatures using either heat lamps or a hot plate
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`to raise temperature and measuring wafer and hot plate temperatures using
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`different thermometers. (Ex. 1004, 1:56-2:3, 7:20-34, 7:62-68, 8:8-14, 11:6-9,
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`Figs. 12-13.) Embodiments from Figures 1, 11, and 19 are shown below. The
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`annotations indicate lamps 5 (red) and hot plate 7 (purple) with heater (red), wafer
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`1 (green), and thermometers 10 and 66 (yellow).
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` Ashing is a type of etching that uses a plasma, typically at high temperatures, to
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`remove a photoresist film. (Ex. 1006 ¶81.) Flamm’s ’849 patent described “resist
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`stripp[ing]” as etching and dependent claims 7 and 16 recited “ashing” as a subset
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`of “etching.” (Ex. 1009, 1:7-9.)
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`Kikuchi ashed photoresist over a range of temperatures, with an initial step
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`at 70ºC-160ºC and a rapid increase to 200ºC in 5 seconds (lamps) or 10 seconds
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`(hot plate). Figures 12 and 13 below show exemplary ashing temperature changes
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`disclosed in Kikuchi.
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`D. Muller (Ex. 1002)
`Muller (issued February 1997) also disclosed etching a wafer at two
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`sequential temperatures in a chamber. (Ex. 1006 ¶¶98-102.) Muller disclosed
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`etching surface layers on a wafer and deep trenches into the wafer while varying
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`wafer temperature using an electrostatic chuck and coolant circulating through a
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`cathode. (Ex. 1005, 1:7-12, 1:44-55, 4:51-63.) Figure 4 below is annotated to
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`highlight wafer 104 (green), electrostatic chuck 105 (purple), and cathode 106
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`(blue).
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`Muller taught performing an initial etch at 125ºC or 145ºC. (Ex. 1002, 3:45-
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`52, 3:56-66.) Then, the gas pressure underneath the chuck was changed to increase
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`wafer temperature by 50ºC in “several seconds” during etching. (Id., 4:64-5:25,
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`5:41-48.) Due to the 50ºC increase, Muller’s second etching step was performed at
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`175ºC (e.g., 125ºC plus 50ºC) or 195ºC (e.g., 145ºC plus 50ºC). (Id., 5:17-25,
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`5:41-48; Ex. 1006 ¶101.) The two etching temperature examples corresponded to
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`different coolant temperatures––(a) with coolant at 10ºC, etch steps 1 and 2 were at
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`125ºC (step 1) and 175ºC (step 2), respectively; and (b) with coolant at 30ºC, etch
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`steps 1 and 2 were at 145ºC (step 1) and 195ºC (step 2), respectively. (Ex. 1006
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`¶101.) Figure 3 below shows the different step 1 etching temperatures achieved
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`for coolant at 10ºC versus 30ºC.
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`E. Moslehi ’824 (Ex. 1010)
`Moslehi ’824 described a tool for high temperature deposition processing,
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`which involves layers being deposited on a wafer instead of being etched away.
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`(Ex. 1010, 1:35-43, 3:28-31, 3:53-56; Ex. 1006 ¶¶114-121.) The tool rapidly
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`changed wafer temperature using a lamp-heated chuck. (Ex. 1010, 4:68-5:1, 5:24-
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`26.) The tool also used sensors to measure wafer and chuck temperature, and a
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`computer/controller system to adjust temperature to desired values. (Id., 4:40-45,
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`5:4-9, 7:3-16, 10:1-9.) Annotated Figure 3 below shows wafer 38 (green), chuck
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`assembly 82 (purple), heating lamp module 84 (red), and process control computer
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`104 and PID controller4 106 (orange). The lamp module included a chuck
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`temperature sensor (yellow).
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`Annotated Figures 6a and 6b below show thermocouple 116 (yellow), which
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`measures the temperature of wafer 38 (green).
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` A PID (proportional integral derivative) controller continuously calculates the
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`difference between a measured value and a desired set point to bring the process to
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`the desired set point. (Ex. 1006 ¶64.)
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`F. Oka (Ex. 1011)
`Oka taught a multi-temperature wafer processing recipe with two deposition
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`steps and a baking step. (Ex. 1006 ¶¶125-130.) Oka’s first step deposited a silicon
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`layer 602 on substrate 601 at 400ºC-800ºC. (Ex. 1011, 20:28-34.) The result of
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`this step is illustrated in Figure 6A below.
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`Oka’s second step deposited a second silicon layer 603 at 150ºC-300ºC,
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`yielding a layer with different properties from the first layer’s. (Id., 20:52-61.)
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`The result of this step is shown below in Figure 6B.
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`In the final step, the wafer was heated at 20ºC/minute or less (preferably
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`5ºC/minute) to 550ºC-650ºC and then baked for 1 to 10 hours to recrystallize the
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`silicon layers into a single film 604, as shown in Figure 6C below. (Id., 3:29-38,
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`20:66-21:10, 21:20-25.)
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`G. Level of ordinary skill in the art
`A person of ordinary skill in the art at the time of the alleged invention of
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`the ’264 patent (“skilled person”) would have had (i) a Bachelor’s degree in
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`chemical engineering, materials science engineering, electrical engineering,
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`physics, chemistry, or a similar field, and three or four years of work experience in
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`semiconductor manufacturing or related fields; or (ii) a Master’s degree in
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`chemical engineering, materials science engine