(12) United States Patent
`Oka et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,235,563 B1
`May 22, 2001
`
`US006235563B1
`
`(54) SEMICONDUCTOR DEVICE AND METHOD
`OF MANUFACTURING THE SAME
`
`0261666
`
`3/1988 (EP) .
`
`(75)
`
`Inventors: Hideaki Oka; Satoshi Takenaka;
`Masafumi Kunii, all of Suwa (JP)
`
`(73) Assignee: Seiko Epson Corporation, Tokyo (JP)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 07/790,107
`
`(22)
`
`Filed:
`
`Nov. 7, 1991
`
`Related U.S. Application Data
`
`(63) Continuation of application No. 07/479,396, filed on Feb.
`13, 1990, now abandoned.
`
`(30)
`
`Foreign Application Priority Data
`
`Feb. 14, 1989
`Mar. 27, 1989
`Mar. 27, 1989
`Jun. 5, 1989
`Oct. 4, 1989
`NOV. 21, 1989
`
`(JP) ................................................... .. 1—34140
`(JP)
`1—74229
`(JP)
`1—74230
`(JP)
`.. 1—142470
`(JP)
`.. 1—259393
`(JP) ................................................. .. 1—302862
`
`
`
`(51)
`
`Int. Cl.7 ................................................... .. H01L 21/32
`
`(52) U.S. Cl.
`
`......................... .. 438/166; 438/485; 438/486
`
`(58) Field of Search ................................... .. 437/173, 174,
`437/967, 973, 83, 103, 109, 980, 983, 968,
`913, 62, 485, 486, 166; 148/DIG. 1, DIG. 3,
`DIG. 90, DIG. 154, DIG. 122
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,883,372
`4,129,463
`
`5/1975 Lin ..................................... .. 148/187
`12/1978 Cleland et al.
`...................... .. 148/33
`
`(List continued on next page.)
`FOREIGN PATENT DOCUMENTS
`
`(List continued on next page.)
`OTHER PUBLICATIONS
`
`N. Sax and R. Lewis, Sr. Hawley’s Condensed Chemical
`Dictionary 11’h Ed. (1987) Van Nostrand Reinhold Co. pp.
`562, 563, 164.*
`P. Kwizera et al., “Solid Phase Epitaxial Recrystallization of
`Thin Polysilicon Films Amorphized by Silicon Ion Implan-
`tation”, Applied Physics Letters, vol. 41(4), pp. 379-381,
`Aug. 15, 1982 (Including vol./No. content page).
`
`Primary Examiner—Charles Bowers
`Assistant Examiner—Matthew Whipple
`
`(57)
`
`ABSTRACT
`
`An improved polycrystalline or polysilicon film having large
`grain size, such as 1 pm to 2 pm in diameter or greater, is
`obtained over the methods of the prior art by initially
`forming a silicon film, which may be comprised of amor-
`phous silicon or micro-crystalline silicon or contains micro-
`crystal regions in the amorphous phase, at a low temperature
`via a chemical vapor deposition (CVD) method, such as by
`plasma chemical vapor deposition (PCVD) with silane gas
`diluted with, for example, hydrogen, argon or helium at a
`temperature, for example, in the range of room temperature
`to 600° C. This is followed by solid phase recrystallization
`of the film to form a polycrystalline film which is conducted
`at a relatively low temperature in the range of about 550° C.
`to 650° C. in an inert atmosphere, e.g., N or Ar, for a period
`of about several hours to 40 or more hours wherein the
`
`temperature is gradually increased, e.g., at a temperature rise
`rate below 20° C./min, preferably about 5° C./min,
`to a
`prescribed recrystallization temperature within the range
`about 550° C. to 650° C. Further, between the step of film
`formation and the step of solid phase recrystallization, the
`film may be thermally treated at
`a relatively low
`temperature, e.g., over 300° C. and preferably between
`approximately 400° C. to 500° C. for a period of several
`minutes, such as 30 minutes, to remove hydrogen from the
`film prior to solid phase recrystallization.
`
`3241959
`
`5/1983 (DE) .
`
`41 Claims, 11 Drawing Sheets
`
`
`
`TEMPERATURE
`
`TIME
`
`Intel Corp. et al. Exhibit l0ll
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`US 6,235,563 B1
`Page 2
`
`4,814,292 *
`4,905,072
`
`................. .. 148/DIG. 1
`3/1989 Sasaki et al.
`2/1990 Komatsu et al.
`.................... .. 357/59
`
`FOREIGN PATENT DOCUMENTS
`
`12/1988
`0296747
`158431 * 12/1981 (JP) .................................... .. 437/247
`79718 *
`5/1983 (JP) .................................... .. 437/247
`10573 *
`1/1988 (JP).
`42112
`2/1988 (JP) .
`2—81421
`3/1990 (JP).
`
`* cited by examiner
`
`U.S. PATENT DOCUMENTS
`
`................... .. 136/258
`2/1981 Koliwad et al.
`2/1982 Yamamoto et al.
`. 437/247
`3/1983 Yamamoto ..
`. 437/239
`2/1984 Chye et al.
`.
`. 437/247
`5/1984 Akasaka ..
`. 156/603
`9/1984 Hu ...... ..
`29/571
`11/1985 Hoga ..... ..
`.. 148/1.5
`4/1986 Celler et al.
`437/62
`7/1986 Imaoka ............................... .. 437/247
`6/1988 Pennell et al.
`....................... .. 437/84
`9/1988 Ishihara et al.
`.................... .. 437/173
`
`
`
`4,249,957
`4,314,595 *
`4,377,605 *
`4,432,809 *
`4,448,632
`4,471,523
`4,552,595
`4,581,814 *
`4,597,804 *
`4,751,196 *
`4,772,486 *
`
`Intel Corp. et al. Exhibit 101 1
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`U.S. Patent
`
`May 22, 2001
`
`Sheet 1 of 11
`
`US 6,235,563 B1
`
`0
`
`103
`
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`
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`
`103
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`
`
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`
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`
`FIG.-1B
`
`FIG.-1C
`
`108
`
`4/”V 107
`
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`
`
`
` FIG.-1D
`
`
`
`
`106
`
`
`104
`
`10
`
`6
`
`hHe1Cknp.eta1 Exhflnt1011
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`U.S. Patent
`
`May 22, 2001
`
`Sheet 2 of 11
`
`US 6,235,563 B1
`
`u:
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`
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`
`FIG.-BB
`
`Intel Corp. et a1. Exhibit 1011
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`U.S. Patent
`
`May 22, 2001
`
`Sheet 3 of 11
`
`US 6,235,563 B1
`
`TEMPERATURE
`
`TEMPERATURE
`
`ME
`
`FIG.-EC
`
`TIME
`
`FIG.-ED
`
`hHe1Cknp.etaL Exhflnt1011
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`U.S. Patent
`
`May 22, 2001
`
`Sheet 4 of 11
`
`US 6,235,563 B1
`
`TEMPERATURE
`
`TIME
`
`FIG.-3A
`
`TEMPERATURE
`
`TIME
`
`FIG.-3B
`
`hHe1Cknp.etaL Exhflnt1011
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`U.S. Patent
`
`May 22, 2001
`
`Sheet 5 of 11
`
`US 6,235,563 B1
`
`TEMPERATURE
`
`FIG.-3C
`
`TEMPERATURE4Q4
`
`TEMPERATURE
`
`FIG.-3D
`
`FIG.-3E
`
`Intel Corp. et a1. Exhibit 1011
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`U.S. Patent
`
`May 22, 2001
`
`Sheet 6 of 11
`
`US 6,235,563 B1
`
`402
`
`7 IflT
`
`404
`
`404
`
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`
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`
`FIG.-4D
`
`Intel Corp. et a1. Exhibit 1011
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`U.S. Patent
`
`May 22, 2001
`
`Sheet 7 of 11
`
`US 6,235,563 B1
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`
`Intel Corp. et a1. Exhibit 1011
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`U.S. Patent
`
`May 22, 2001
`
`Sheet 8 of 11
`
`US 6,235,563 B1
`
`
`
`FIG.-SB
`
`505
`
`503
`
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`
`Intel Corp. et a1. Exhibit 1011
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`U.S. Patent
`
`May 22, 2001
`
`Sheet 9 of 11
`
`US 6,235,563 B1
`
`
`
` ’///////
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`
`Intel Corp. et a1. Exhibit 1011
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`U.S. Patent
`
`May 22, 2001
`
`Sheet 10 of 11
`
`US 6,235,563 B1
`
`608
`
`ZCIIIIIIIJVIIIIIIIIIIIII4
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`Intel Corp. et a1. Exhibit 1011
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`U.S. Patent
`
`May 22, 2001
`
`Sheet 11 of 11
`
`US 6,235,563 B1
`
`§ I
`
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`
`FIG.-7
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`Intel Corp. et a1. Exhibit 1011
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`
`

`
`US 6,235,563 B1
`
`1
`SEMICONDUCTOR DEVICE AND METHOD
`OF MANUFACTURING THE SAME
`
`“This is a continuation of application Ser. No. 07/479,
`396 filed Feb. 13, 1990 now abandoned”
`
`BACKGROUND OF THE INVENTION
`
`This invention relates generally to a semiconductor device
`and a method of manufacturing the same and, in particular,
`to a method of manufacturing semiconductor devices having
`a thin film formed on an insulating support, such as a
`substrate or support layer, and, further, to the formation of
`thin film transistors (TFTs) on insulating supports for large
`area image arrays, such as liquid crystal display panels.
`Studies and experiments have been performed to form a
`high quality semiconductor films, devices, and IC structures
`on insulating supports, such as, insulating substrates, for
`example, glass, quartz, or the like and on amorphous layers,
`for example, SiO2, Si3N4, and the like.
`In recent years, expectations and desires for improved
`high quality semiconductor silicon devices and IC structures
`formed on these insulating supports has continually
`increased. Examples of applications are large area, high
`resolution liquid crystal display panels and devices; high
`speed, high resolution contact type image sensors;
`three
`dimensional ICs, and other IC structures. Therefore,
`the
`development of a method that will consistently and reliably
`form high quality silicon thin films on an insulating support
`is under intensive research and development. Relative to
`semiconductor materials, a polycrystalline or polysilicon
`silicon TFT device has a higher field effect mobility than an
`amorphous silicon TFT device and the amount of ON
`current of a polysilicon TFT is much greater than that of an
`amorphous TFT. However, the mobility of present polysili-
`con TFTs is still lower than that of monocrystalline TFT
`devices because of many barriers around the boundaries of
`crystal gains in the polysilicon material. In the case of the
`above mentioned applications,
`it
`is highly desirable to
`increase the level of mobility of polysilicon TFT devices to
`approach that of monocrystalline silicon. In order to obtain
`such higher levels of mobility in polysilicon TFT devices,
`the grain size diameter of the polysilicon should be
`increased from around 500 A to several 1,000 A, which is in
`the range of reproducibility in the present state of the art, to
`about 1 pm or greater.
`Relative to the formation of thin film transistors (TFTs) on
`insulating structures, the following general methods have
`been studied and developed: (1) The formation of TFTs
`employing amorphous silicon as the semiconductor material
`fabricated by plasma CYD or low pressure chemical vapor
`deposition (LPCVD) or a similar process, (2) TFTs employ-
`ing polycrystalline silicon as the semiconductor material
`fabricated by chemical vapor deposition (CVD), LPCVD,
`plasma enhanced chemical vapor deposition (PECVD) or
`similar process, and (3) TFTs employing single crystal or
`monocrystallized silicon as the semiconductor material fab-
`ricated by melting recrystallization or such similar process.
`However, the realization of high quality TFTs has been very
`difficult because the field effect mobility of TFTs comprising
`amorphous silicon or polycrystalline silicon is substantially
`lower than that of TFTs comprising single crystal silicon.
`For example, relative the conventional methods of (1) and
`(2), the field effect mobility for amorphous silicon TFTs is
`typically below 1 cm2/V~sec and for conventional polycrys-
`talline silicon TFT is approximately or less than 10 cm2/
`V~sec. Thus, high speed operational characteristics have not
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`been realized by the employment of these methods. On the
`other hand,
`in the case of the method (3), melting
`recrystallization, wherein a laser beam is utilized to bring
`about recrystallization, higher mobilities have been
`achieved, such as in the hundreds of cm2/V~sec. However,
`there are problems associated with this technique due to the
`use of very high temperatures in processing and,
`furthermore, the technique has not been sufficiently devel-
`oped to lend itself to mass production of semiconductor
`devices, particularly, the mass production of hundreds to
`thousands of active elements on a large area insulating
`supports, such as glass substrates for large area image
`devices, e.g., liquid crystal display panels.
`Recently, the method of forming large grain polycrystal-
`line silicon layers or films by solid phase recrystallization
`has been pursued and research employing this method has
`been proceeding in recent years. One of the principal reasons
`for the interest in solid phase recrystallization is the advan-
`tage in using lower processing temperatures compared to
`melting recrystallization. Examples of studies relating to
`solid phase recrystallization processing are found in the
`articles of P. Kwizera et al., “Annealing Behavior of Thin
`Polycrystalline Silicon Films Damaged by Silicon Ion
`Implantation in the Critical Amorphous Range”, Thin Solid
`Films, Vol. 100(3), p. 227-233, (1983), and T. Noguchi et
`al., “Low Temperature Polysilicon Super-Thin-Film Tran-
`sistor (LSFT), Japanese Journal of Applied Physics, Vol.
`25(2), p. L121—L123, February, 1986 and in U.S. Pat. No.
`4,693,759.
`Generally, the conventional method of solid phase recrys-
`tallization relative to the formation of TFTs and other such
`
`active elements is that, first, a polycrystalline silicon film is
`formed by LPCVD or PECVD employing SiCI4, SiH4 or the
`like. Next, the polycrystalline silicon film is amorphized by
`a Si’' ion implantation. Then, the converted amorphous film
`is heat treated, for example, at approximately 600° C. in an
`nitrogen atmosphere in excess of 30 hours and, preferably
`nearly 100 hours to produce large gain polysilicon. Finally,
`the polysilicon film is patterned into a TFT device using
`conventional photolithography techniques. However,
`the
`practice of this method has the following disadvantages: (1)
`The process is complicated by the requirement
`that the
`formed polycrystalline silicon layer must be amorphized
`before further treatment, which naturally increases manu-
`facturing costs. (2) This amorphization is accomplished with
`expensive ion implantation system, which is necessary to
`perform the implantation operation. (3) The required heat
`treatment period is comparatively a very long period of time,
`in many cases as long as nearly 100 hours to achieve the
`largest grain size possible. (4) It is very difficult to handle
`large insulating substrates, such as, for example, 30 cm><30
`cm, and obtain uniform results across a deposited and heat
`treated thin film on such a substrate. (5) The crystallized
`volume fraction, i.e., the crystal to overall volume rates in
`the recrystallized film, is low after performing solid phase
`recrystallization. Therefore, it is very difficult to fabricate a
`high quality active elements on large area substrates
`employing conventional methods of solid phase recrystalli-
`zation.
`
`It is an object of this invention to provide a low tempera-
`ture method of forming polycrystalline thin films on an
`insulating support having high polycrystalline quality, larger
`crystal grains and good crystal grain orientation.
`It is another object of the present invention to provide
`semiconductor devices, such as TFTs, having high speed
`operational characteristics and higher field effect mobility
`compared with such devices made by conventional methods.
`
`Intel Corp. et al. Exhibit 101 l
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`US 6,235,563 B1
`
`3
`It another object of this invention to provide a semicon-
`ductor device which comprises a polycrystalline silicon thin
`film formed on an insulating support characterized by large
`grains, high crystallized volume fraction and reduction of
`the Si/SiO2 interface state density.
`It is another object of this invention to provide a method
`for the manufacture of a thin film polysilicon semiconductor
`that
`is simpler in implementation with resulting higher
`manufacturing reproducibility and yields compared to prior
`conventional methods.
`
`It is still a further object of this invention to provide a
`polysilicon thin film on an insulating medium having high
`field effect mobility suitable for large are IC applications,
`such as large area TFT arrays for LCD panels.
`
`SUMMARY OF THE INVENTION
`
`According to this invention, an improved polycrystalline
`or polysilicon film having large grain size, such as, 1 pm to
`2 pm in diameter or greater, is obtained over the methods of
`the prior art by initially forming a silicon film, which may
`be comprised of amorphous silicon, or micro-crystalline
`silicon, or contains micro-crystal regions in the amorphous
`phase (hereinafter also referred to as “noncrystalline”), at a
`low temperature via a chemical vapor deposition (CVD)
`method, such as by plasma chemical vapor deposition
`(PCVD) with silane gas diluted with,
`for example,
`hydrogen, argon or helium at a temperature, for example, in
`the temprature range room temperature to 600° C. This is
`followed by solid phase recrystallization of the film to form
`a polycrystalline film which is conducted at a relatively low
`temperature in the range of about 550° C. to 650° C. in an
`inert atmosphere, e.g., N or Ar, for a period of about several
`hours to 40 or more hours preferably wherein the tempera-
`ture is gradually increased, e.g., at a temperature rise rate
`below 20° C./min, preferably about 5° C./min, to a pre-
`scribed recrystallization temperature within the range about
`550° C. to 650° C.
`
`Further, between the step of forming the film and the step
`of solid phase recrystallization, the film may be thermally
`treated at a relatively low temperature, e.g., over 300° C. and
`preferably between approximately 400° C. to 500° C. for a
`period of several minutes, such as 30 minutes, to remove
`most of the hydrogen from the film prior to recrystallization,
`since hydrogen included in the silicon film disturbs and
`suppresses the formation of large crystal grain sizes during
`subsequent solid phase recrystallization treatment to form a
`polycrystalline film. Also, if the formation of the noncrys-
`talline film by CVD deposition is carried at a substrate
`temperature in the range of about 150° C. to 200° C. which
`is particularly desirable, during the process of solid phase
`recrystallization, larger crystal grains will be formed and the
`possibility of release of the film from the substrate is less
`likely to occur. The prepared polycrystalline film may then
`be utilized for TFT gate electrodes. After formation of the
`gate oxidation layer,
`the gate electrode may be formed,
`followed by formation of defined source and drain regions to
`complete the manufacture of a TFT device. The resultant
`field effect mobility of an n channel, polycrystalline silicon
`TFT formed in accordance with the method of this invention
`
`is 150 cm2/V~sec to 200 cm2/V~sec and greater.
`Further, the method of this invention comprises the ther-
`mal oxidation of a polysilicon film to form a gate oxidation
`layer or
`film on it surface wherein the temperature is
`increased gradually, e.g., below about 20° C./min, preferably
`at about 5° C./min, to the thermal oxidation temperature in
`the range of about 1,000° C. to 1,200° C.
`
`5
`
`10
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`15
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`20
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`25
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`30
`
`35
`
`40
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`50
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`55
`
`60
`
`65
`
`4
`Thus, polycrystalline silicon films with large grains and
`high crystallized volume fraction can be produced by
`employing a simpler manufacturing process. As a result, it is
`possible to form high quality semiconductor active elements
`on insulating materials, thereby making it possible to pro-
`duce large size, high resolution liquid crystal display panel;
`high speed, high resolution contact type image sensors; three
`dimensional ICs; and the like.
`Also, according to the method of this invention, there are
`following additional attributes. In the case of an undoped
`channel region in the past, it was necessary to dope the
`impurity, for example, boron, in the channel region via ion
`implantation, since the characteristics of the active region of
`an n channel polycrystalline silicon TFT tend to shift to the
`depletion side, and of a p channel polycrystalline silicon
`TFT to the enhancement side. On the other hand, according
`to this invention, since a doped polycrystalline silicon layer
`can be obtained by doping impurities, such as boron or the
`like, at the time of film growth and, then, thereafter solid
`phase recrystallization performed on the doped film,
`employment of expensive equipment, such as an ion implan-
`tation system,
`is not necessary and, further,
`there is no
`necessity to increase the number of processing steps, which
`is a cost effective advantage. For example, if an impurity in
`the concentration range of about 1015/cm3 to 109/cm3 are
`doped at the channel region prior to formation of the gate
`electrode of TFT device, this shift in Vth can be suppressed
`so that impurities in channel region can be employed to
`control threshold voltage, Vth and minimize cut off current.
`Alternatively, by doping impurities during the film growth
`prior to solid phase recrystallization in order to control Vth,
`an increased ON current for p channel TFT’s can be
`obtained beside minimized cut off current.
`
`Also, according to the method of this invention, reduction
`of gate interconnect resistance can be easily achieved with
`a simple treatment process. High gate interconnect resis-
`tance has been a problem in active TFT, large LCD panels
`and this resistance can be reduced by the practice of this
`invention more easily enabling the fabrication of liquid
`crystal display panels with applicability also to HDTV
`panels. Further, this invention is also effective as applied to
`a contact type image sensors wherein the scanning circuit
`and electro-optic transducer are integrated on a single sub-
`strate achieving higher read scan rates and higher resolution.
`It is possible to make a wider contact type image sensor
`because of the reduction of the gate interconnect resistance
`enabling larger size image sensors. For example, a high
`speed scanner with a contact type image sensor having an
`electrooptic transducer and scanning circuit integrated in a
`single chip manufactured according to this invention can
`have a scanning rate equal to or in excess of 1 ms/line, in the
`case of an A4 size scanned medium, and having a resolution
`of 400 DPI or greater. Also, this circuit can be operated at
`lower source voltage levels of about 5 V to 10 V, compared
`to previous levels of about 16 V. By the same token,
`application of this invention are also easily applicable to
`TFT driven liquid crystal shutter arrays, TFT driven thermal
`heads, three dimensional ICs or the like.
`Further, polycrystalline silicon films with large grains can
`be formed by employing shorter thermal treatment periods
`by a combination of films wherein one film crystalline seeds
`are easily generated by solid phase recrystallization and in
`another film crystalline seeds are difficult to generate by
`solid phase recrystallization. Further, by forming a film
`wherein crystalline seeds are easily generated by the
`employment of a relatively high temperature plasma CVD
`process, polycrystalline silicon with large grains with uni-
`
`Intel Corp. et al. Exhibit 101 l
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`US 6,235,563 B1
`
`5
`form direction of orientation, such as <110>, or silicon with
`small crystalline grains in the amorphous phase can be
`achieved with a thermal
`treatment of a relatively short
`duration. As a result, improvements in field effect mobility
`and reduction of Si/SiO2 interface state density are realized
`in the employment of this invention. In particular,
`two
`different silicon films are formed by plasma CVD method on
`the same support wherein one film is formed at a relatively
`higher temperature, e.g., in the range of about 400° C. to
`800° C. in order to possess a relatively high polycrystalline
`seed generation rate, and another film is formed at a rela-
`tively lower temperature, e.g., in the range of about 150° C.
`to 300° C.
`, in order to possess a relatively low polycrys-
`talline seed generation rate. Thus, the polycrystalline seed
`generation ratio of the latter film is lower than that of the
`former film. This enables a polycrystalline film to be formed
`by solid phase recrystallization in a relatively short thermal
`treatment period that has large crystal grain sizes. The role
`of the crystalline seeds is to lower activation energy of
`transforming amorphous to crystalline silicon thereby ren-
`dering a shorter annealing time and to control crystal ori-
`entation of the formed polycrystalline silicon film. The field
`effect mobility of a high temperature processed n channel
`TFT manufactured according to the method of this invention
`is greater than about 200 cm2/V~sec, thereby providing for a
`high quality TFT.
`Other objects and attainments together with a fuller
`understanding of the invention will become apparent and
`appreciated by referring to the following description and
`claims taken in conjunction with the accompanying draw-
`1ngs.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1A—1D illustrate a series of manufacturing steps in
`the manufacture of a semiconductor device in carrying out
`one embodiment of the method comprising this invention.
`FIGS. 2A—2D are graphic illustrations of the temperature
`rise over time relative to one embodiment of this invention.
`
`FIGS. 3A—3E are graphic illustrations of the temperature
`rise over time relative to another embodiment of this inven-
`tion.
`
`FIGS. 4A—4H illustrate a series of manufacturing steps in
`the manufacture of a semiconductor device in carrying out
`another embodiment of the method comprising this inven-
`tion.
`
`FIGS. 5A—5F illustrate a series of manufacturing steps in
`the manufacture of a semiconductor device in carrying out
`still another embodiment of the method comprising this
`invention.
`
`FIGS. 6A—6D illustrate a series of manufacturing steps in
`the manufacture of a semiconductor device in carrying out
`a further embodiment of the method comprising this inven-
`tion.
`
`FIG. 7 is graphical illustration of the characteristics of the
`gate voltage versus the drain current of a n channel TFT
`comprising this invention.
`FIG. 8 is graphical illustration of the characteristics of the
`gate voltage versus the drain current of a p channel TFT
`comprising this invention.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Various specific embodiments will now be described
`relative to the method of this invention relative to active
`semiconductor devices in the form of TFTs as shown in
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`FIGS. 1, 4, 5 and 6. However, the method of this invention
`is equally applicable to other active semiconductor
`elements, such as bipolar transistors, static induction type
`transistors, electro-optic transducers, e.g., solar cells and
`optical sensor devices and arrays.
`Reference is now made to FIGS. 1A—1D which illustrate
`
`one example of the manufacturing process of a semicon-
`ductor device employed in a first embodiment of this inven-
`tion comprising the formation of a thin film transistor (TFT)
`shown in FIG. 1.
`
`As shown in FIG. 1A, a silicon layer or film 102 is formed
`on insulating support 101, such as an insulating substrate,
`for example, glass, quartz or the like or an amorphous layer,
`for example, SiO2, Si3N4 or the like. Also, other insulating
`crystalline supports may be employed, such as a sapphire
`substrate (A1203) or substrates of MgO~Al2O3, CaF2 or the
`like. Film 102, for the most part, is amorphous silicon or
`micro-crystalline silicon or contains micro-crystal regions in
`the amorphous phase, which is generally referred to in the
`disclosure as a noncrystalline film.
`One example of the growth of noncrystalline film 102 is
`by plasma CVD (PCVD) discharge. Substrate 101 is placed
`in the reactor of the CVD system and the temperature of
`substrate 101 is maintained in the range from about room
`temperature to 600° C. Silane gas, e.g., SiH4, is diluted with,
`for example, hydrogen, argon or helium, is introduced into
`the reactive chamber and rf power is applied to dissociate the
`gas and a silicon layer is formed on substrate 101 having a
`thickness in the range of about 100 A to 2,000
`An amorphous silicon film formed by plasma CVD con-
`tains less contaminants, e.g., oxygen, nitrogen or carbon,
`compared to the amorphous silicon film formed by electron
`beam evaporation or LPCVD. Thus, a polycrystalline film
`with high purity has been obtained by performing solid
`phase recrystallization on an amorphous silicon film formed
`by plasma CVD.
`Also,
`less contaminants in an amorphous silicon film
`makes it easy to promote solid phase recrystallization, which
`results in obtaining a polycrystalline silicon film with a large
`grain size. In particular, the amorphous silicon deposited in
`the temperature range of about 150° C. to 350° C. contains
`the lowest amount of contaminants, which are derived from
`an insulating support and the PCVD reaction chamber. On
`the other hand,
`the amorphous silicon deposited in the
`temperature range of about room temperature to 150° C.
`easily releases hydrogen via thermal treatment so that the
`thermal treatment time may be short.
`The amount of carbon and oxygen in an amorphous
`silicon film formed by PCVD may be reduced to the order
`of 1017/cm‘3 to 1018 cm‘3. In particular,
`the amount of
`carbon and oxygen may be reduced to less than 101° cm‘3
`by improving the purity of the gas source and suppressing
`the generation of contaminants from the inner walls of the
`PCVD reaction chamber.
`
`It should be noted that other methods may be employed
`for forming film 102. In any case, the optimum parameters
`of the thermal treatment applied after film formation for
`solid phase recrystallization may be dictated by what
`method of film formation is employed.
`Next, thermal treatment is performed on noncrystalline
`silicon film 102 to convert the film to a polycrystalline
`silicon film 103 by means of solid phase resrystallization,
`illustrated in connection with FIG. 3. As previously
`indicated, the best conditions for thermal treatment differ
`depending upon the method of forming and the nature of
`silicon film 102. For example, depending upon the substrate
`
`Intel Corp. et al. Exhibit 1 01 l
`
`Intel Corp. et al. Exhibit 1011
`
`

`
`US 6,235,563 B1
`
`7
`temperature when film 102 is grown by plasma CVD, there
`are the following differences:
`(1) A noncrystalline silicon film 102 formed while the
`substrate temperature is in the range between room tem-
`perature and 150° C., which is a relatively low temperature
`range, is deposited as amorphous silicon containing a large
`amounts of hydrogen. However, hydrogen in film 102 can be
`removed by a subsequent thermal treatment at a temperature
`below that necessary for removal in the case of a film formed
`while the substrate temperature in the range between
`approximately 200° C. to 300° C. One example of such a
`thermal treatment is the annealing of the amorphous silicon
`film before vacuum is broken in the film forming system.
`Since an amorphous film formed at these low temperatures
`is porous in nature, oxygen and other contaminants will
`enter into the film upon removal of the structure from the
`reactor system resulting in a low quality film. However, if
`the film is given proper thermal treatment before it is taken
`out of the reactor, then the film will become dense in nature
`preventing oxygen and other contaminants from entering
`into the film. The desirable thermal treatment temperature
`for this purpose is over 300° C. and, if the temperature is
`increased between approximately 400° C. to 500° C., sub-
`stantially effective results can be achieved. However,
`it
`should be noted that, even when the thermal
`treatment
`temperature is below 300° C., film densification can still be
`achieved, although not as effectively.
`In the case wherein subsequent annealing for the purposes
`of solid phase recrystallization is performed in the same film
`forming apparatus without breaking vacuum, the annealing
`step for purpose of film densification can be omitted.
`Next, the step of solid phase recrystallization is performed
`on amorphous silicon film 102 with a relatively low tem-
`perature thermal treatment in the range of about 550° C. to
`650° C. for a period of about several hours to 20 hours. Both
`hydrogen removal and crystal growth concurrently occur
`during the treatment and polycrystalline silicon is formed
`comprising large grain sizes of about 1 to 2 yim in diameter
`or greater. It is preferred that the temperature of annealing
`for achieving both enhanced density and solid phase recrys-
`tallization is not increased or elevated rapidly to the pre-
`scribed temperature for solid phase recrystallization. This is
`because hydrogen dissipation from the film begins to occur
`as the temperature rises, especially when the temperature
`exceeds 300° C.
`If the rate of temperature rise to the
`prescribed temperature for solid phase recrystallization is
`performed too rapidly, the formation of defects in the film
`will more easily occur. In some cases pin holes may appear
`and other cases film separations will appear. We have
`determined that if the temperature is gradually increased by
`a rate below 20° C./min., preferably, an increasing tempera-
`ture rise rate below 5° C./min., particularly where the
`treatment temperature exceeds 300° C., the formation of
`defects in the film will be less. A more detailed explanation
`of the method of gradient increase of the treatment tempera-
`ture to the