UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`AND MICRON TECHNOLOGY, INC.,
`Petitioners,
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`v.
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`DANIEL L. FLAMM,
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`Patent Owner.
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`PTAB Case No. IPR2017-00281
`Patent No. RE40,264 E
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`DECLARATION OF DR. JOHN BRAVMAN IN SUPPORT OF PETITION
`FOR INTER PARTES REVIEW OF U.S. PATENT NO. RE40,264
`(Claims 37-50 and 67)
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`Intel Corp. et al. Exhibit 1006
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`

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`TABLE OF CONTENTS
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`Page
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`I.
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`II.
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`INTRODUCTION AND SUMMARY OF TESTIMONY ............................ 1
`A. Qualifications ....................................................................................... 1
`1.
`Education ................................................................................... 1
`2.
`Career ......................................................................................... 2
`3.
`Publications ................................................................................ 4
`4.
`Curriculum Vitae ........................................................................ 5
`Compensation ....................................................................................... 5
`B.
`C. Materials Reviewed .............................................................................. 5
`D.
`Level of Ordinary Skill in the Art ........................................................ 8
`OVERVIEW REGARDING TECHNOLOGY .............................................. 9
`A.
`Priority Date ......................................................................................... 9
`1.
`The Challenged Independent Claims ....................................... 10
`2.
`The Disclosure of Application No. 08/567,224, Filed on
`December 4, 1995 .................................................................... 12
`State of the Art from the Perspective of a Person of Ordinary
`Skill in the Art at the Time of the Alleged Invention ........................ 15
`Background and General Description of the ’264 patent ................... 20
`C.
`Claim Construction ............................................................................ 24
`D.
`III. OVERVIEW OF THE PRIOR ART ............................................................ 25
`A.
`Standard for Invalidity........................................................................ 25
`B.
`Background on Kadomura ................................................................. 27
`1.
`General overview of Kadomura ............................................... 27
`2.
`Summary of Kadomura ............................................................ 34
`Background on Matsumura ................................................................ 35
`1.
`General overview of Matsumura ............................................. 35
`2.
`Summary of Matsumura .......................................................... 38
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`B.
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`C.
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`-i-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`D.
`E.
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`F.
`G.
`H.
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`Reasons to combine Kadomura with Matsumura .............................. 38
`Background on Kikuchi ..................................................................... 42
`1.
`General overview of Kikuchi ................................................... 42
`2.
`Summary of Kikuchi ................................................................ 47
`Reasons to combine Kikuchi with Kadomura and Matsumura ......... 47
`Reasons to combine Matsumura with Kikuchi .................................. 51
`Background on Muller ....................................................................... 57
`1.
`General overview of Muller ..................................................... 57
`2.
`Summary of Muller .................................................................. 60
`Reasons to combine Muller with Kadomura and Matsumura ........... 61
`Reasons to combine Muller with Kikuchi and Matsumura................ 64
`Background on Moslehi ’824 ............................................................. 69
`1.
`General overview of Moslehi ’824 .......................................... 69
`2.
`Summary of Moslehi ’824 ....................................................... 73
`Reasons to combine Matsumura with Moslehi ’824 .......................... 74
`L.
`M. Background on Oka ............................................................................ 76
`1.
`General overview of Oka ......................................................... 76
`2.
`Summary of Oka ...................................................................... 77
`Reasons to combine Oka with Moslehi ’824 ..................................... 77
`N.
`IV. KADOMURA, MATSUMURA, MULLER, AND KIKUCHI
`RENDERED CLAIMS 37-46, 49-50, AND 67 OBVIOUS ........................ 79
`A. Kadomura and Matsumura rendered claim 37 obvious ..................... 79
`1.
`Kadomura disclosed what is recited in the preamble of
`claim 37 .................................................................................... 79
`Kadomura disclosed claim 37, limitation [a] ........................... 80
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`I.
`J.
`K.
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`2.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`3.
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`4.
`5.
`6.
`7.
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`Kadomura and Matsumura disclosed claim 37, limitation
`[b] ............................................................................................. 81
`Kadomura disclosed claim 37, limitation [c] ........................... 91
`Kadomura disclosed claim 37, limitation [d]........................... 92
`Kadomura disclosed claim 37, limitation [e] ........................... 94
`Kadomura and Matsumura rendered claim 37, limitation
`[f] obvious ................................................................................ 96
`Kadomura and Matsumura rendered claim 38 obvious ................... 106
`B.
`Kadomura and Matsumura rendered claim 39 obvious ................... 107
`C.
`D. Kadomura and Matsumura alone or in view of Muller rendered
`claim 40 obvious .............................................................................. 108
`Kadomura and Matsumura rendered claim 41 obvious ................... 119
`Kadomura and Matsumura alone or in view of Muller rendered
`claim 42 obvious .............................................................................. 119
`G. Kadomura and Matsumura rendered claim 43 obvious ................... 121
`H. Kadomura and Matsumura rendered claim 44 obvious ................... 122
`I.
`Kadomura and Matsumura alone or in view of Muller rendered
`claim 45 obvious .............................................................................. 126
`Kadomura and Matsumura rendered claim 46 obvious ................... 129
`J.
`K. Kadomura and Matsumura in view of Muller rendered claim 49
`obvious ............................................................................................. 129
`Kadomura and Matsumura in view of Kikuchi rendered claim
`50 obvious ........................................................................................ 134
`M. Kadomura and Matsumura in view of Muller rendered claim 67
`obvious ............................................................................................. 138
`V. KIKUCHI, MATSUMURA AND MULLER RENDERED CLAIMS
`37-46, 49-50, AND 67 OBVIOUS. ............................................................ 138
`A. Kikuchi and Matsumura rendered claim 37 obvious ....................... 139
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`E.
`F.
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`L.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`1.
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`2.
`3.
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`4.
`5.
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`6.
`7.
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`Kikuchi disclosed what is recited in the preamble of
`claim 37 .................................................................................. 139
`Kikuchi disclosed claim 37, limitation [a] ............................. 139
`Kikuchi and Matsumura disclosed claim 37, limitation
`[b] ........................................................................................... 140
`Kikuchi disclosed claim 37, limitation [c] ............................. 153
`Kikuchi and Matsumura disclosed claim 37, limitation
`[d] ........................................................................................... 153
`Kikuchi disclosed claim 37, limitation [e] ............................. 154
`Kikuchi and Matsumura rendered claim 37, limitation [f]
`obvious ................................................................................... 154
`Kikuchi and Matsumura rendered claim 38 obvious ....................... 156
`B.
`Kikuchi and Matsumura rendered claim 39 obvious ....................... 156
`C.
`D. Kikuchi and Matsumura rendered claim 40 obvious ....................... 157
`E.
`Kikuchi and Matsumura alone or in view of Muller rendered
`claim 41 obvious .............................................................................. 161
`Kikuchi and Matsumura rendered claim 42 obvious ....................... 168
`F.
`G. Kikuchi and Matsumura rendered claim 43 obvious ....................... 169
`H. Kikuchi and Matsumura rendered claim 44 obvious ....................... 172
`I.
`Kikuchi and Matsumura rendered claim 45 obvious ....................... 173
`J.
`Kikuchi and Matsumura rendered claim 46 obvious ....................... 174
`K. Kikuchi and Matsumura in view of Muller rendered claim 49
`obvious ............................................................................................. 175
`Kikuchi and Matsumura rendered claim 50 obvious ....................... 178
`L.
`M. Kikuchi and Matsumura rendered claim 67 obvious ....................... 181
`VI. MOSLEHI ’824, MATSUMURA AND OKA RENDERED AT
`LEAST CLAIMS 37 AND 47-48 OBVIOUS ............................................ 181
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`TABLE OF CONTENTS
`(continued)
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`Page
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`A. Moslehi ’824, Matsumura and Oka rendered claim 37 obvious ...... 182
`1. Moslehi ’824 disclosed what is recited in the preamble of
`claim 37 .................................................................................. 182
`2. Moslehi ’824 disclosed claim 37, limitation [a] .................... 182
`3. Moslehi ’824 and Oka disclosed claim 37, limitation [b] ..... 185
`4. Moslehi ’824 and Oka disclosed claim 37, limitation [c] ...... 191
`5. Moslehi ’824 and Oka disclosed claim 37, limitation [d] ..... 192
`6. Moslehi ’824 and Oka disclosed claim 37, limitation [e] ...... 193
`7. Moslehi ’824 and Oka in view of Matsumura disclosed
`claim 37, limitation [f] ........................................................... 193
`B. Moslehi ’824, Matsumura and Oka rendered claim 47 obvious ...... 200
`C. Moslehi ’824, Matsumura and Oka rendered claim 48 obvious ...... 201
`VII. CONCLUSION ........................................................................................... 201
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`-v-
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`Intel Corp. et al. Exhibit 1006
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`I. Introduction and summary of testimony
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` My name is John Bravman. I have been retained in the above-1.
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`referenced inter partes review proceeding by Intel Corporation, Micron Technolo-
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`gy, Inc., and GlobalFoundries U.S., Inc. (collectively, “Petitioners”) to evaluate
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`United States Patent No. RE40,264 (the “’264 patent”) against certain prior art ref-
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`erences, specifically U.S. Patent Nos. 6,063,710, 5,151,871, 5,226,056, 5,605,600,
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`5,446,824, and 6,235,563, as well as the knowledge of a person of skill in the art at
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`the time of the purported invention, including as demonstrated by various state of
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`the art references. The ’264 patent is attached as Exhibit 1001 to Petitioners’ peti-
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`tion for Inter Partes Review of U.S. Patent No. RE40,264 (“Petition”). I under-
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`stand that Petitioners seek review of claims 37-50 and 67 in their Petition. As de-
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`tailed in this declaration, it is my opinion that each of the challenged claims is ren-
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`dered obvious by prior art references that predate the priority date of the ’264 pa-
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`tent. If requested by the Patent Trial and Appeal Board (“PTAB” or “Board”), I
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`am prepared to testify about my opinions expressed in this declaration.
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`A. Qualifications
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`Education
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`1.
`I received my Bachelors of Science degree in Materials Science and
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`2.
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`Engineering at Stanford University in 1979. I later received a Master’s of Science
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`in Materials Science and Engineering from Stanford University in 1981, and I was
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`Intel Corp. et al. Exhibit 1006
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`awarded a Ph.D. in Materials Science and Engineering from Stanford University in
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`1984, specializing in semiconductor processing and materials analysis. My thesis
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`was entitled “Morphological Aspects of Silicon - Silicon Dioxide VLSI Interfac-
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`es,” and concerned structural analyses of silicon-silicon dioxide interfaces, as
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`found in integrated circuit devices—specifically very-large-scale integration devic-
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`es.
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`Career
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`2.
`I will discuss my current position first, followed by a synopsis of my
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`3.
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`career and work from when I received my Ph.D. to the present.
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`4.
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`I am currently employed as the President and as a Professor of Elec-
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`trical Engineering at Bucknell University in Lewisburg, Pennsylvania. As the
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`President of Bucknell, I am the chief administrator at the university and am re-
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`sponsible for helping to set university policy and priorities, alumni relations, and
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`university advancement.
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`5.
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`From 1979 to 1984, while a graduate student at Stanford, I was em-
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`ployed part-time by Fairchild Semiconductor in their Palo Alto Advanced Re-
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`search Laboratory. I worked in the Materials Characterization group. In 1985, upon
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`completion of my doctorate, I joined the faculty at Stanford as Assistant Professor
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`of Materials Science and Engineering. I was promoted to Associate Professor with
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`tenure in 1991, and achieved the rank of Professor in 1995. In 1997 I was named
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`Intel Corp. et al. Exhibit 1006
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`to the Bing Professorship.
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`6.
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`I served as Chairman of Stanford University’s Department of Materi-
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`als Science and Engineering from 1996-1999, and the Director of Stanford’s Cen-
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`ter for Materials Research from 1998-1999. I served as Senior Associate Dean of
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`the School of Engineering from 1992 to 2001 and the Vice Provost for Undergrad-
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`uate Education from 1999 to 2010.
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`7.
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`On July 1, 2010, I retired from Stanford University and began service
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`as the President of Bucknell University, where I also became a Professor of Elec-
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`trical Engineering.
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`8.
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`I have worked for more than 25 years in the areas of thin film materi-
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`als processing and analysis. Much of my work has involved materials for use in
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`microelectronic interconnects and packaging, and in superconducting structures
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`and systems. I have also led multiple development efforts of specialized equip-
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`ment and methods for determining the microstructural and mechanical properties
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`of materials and structures.
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`9.
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`I have taught a wide variety of courses at the undergraduate and grad-
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`uate level in materials science and engineering, emphasizing both basic science
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`and applied technology, including coursework in the areas of integrated circuit ma-
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`terials and processing. More than two thousand students have taken my classes,
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`Intel Corp. et al. Exhibit 1006
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`and I have trained 24 doctoral students, most of whom now work in the microelec-
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`tronics and semiconductor processing industries.
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`10.
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`In the course of my research, my research group made extensive use
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`of plasma semiconductor processing equipment for depositing and etching films of
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`both simple (e.g., elemental) and complex (e.g., multi-element compound) materi-
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`als, including semiconductor processing that monitored and controlled temperature
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`during processing.
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`11.
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`I am or have been a member of many professional societies, including
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`the Materials Research Society, the Institute of Electrical and Electronic Engineers,
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`Electron Microscopy Society of America, the American Society of Metals, the
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`Metallurgical Society of AIME, the American Chemical Society, and the American
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`Physical Society. I served as President of the Materials Research Society in 1994.
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`Publications
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`3.
`I am a named inventor on two United States patents relating to the de-
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`12.
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`livery of medicinal compounds using particular material compositions. The patent
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`numbers and titles as well as my co-inventors are listed on my curriculum vitae at-
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`tached to this declaration as Appendix A.
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`13.
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`I am author or co-author of over 160 peer-reviewed articles and con-
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`ference proceedings, nearly all of which relate to semiconductor processing and/or
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`integrated circuits. The titles, publication information and my co-authors are listed
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`Intel Corp. et al. Exhibit 1006
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`on my curriculum vitae attached to this declaration as Appendix A.
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`14.
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`I am also the author, co-author, or editor of 8 edited works related to
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`semiconductor processing or materials.
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`4.
`Curriculum Vitae
` Additional details of my education and employment history, recent
`15.
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`professional service, patents, publications, and other testimony are set forth in my
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`current curriculum vitae, attached to this declaration as Appendix A.
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`B. Compensation
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`16.
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`In connection with my work as an expert, I am being compensated at a
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`rate of $450.00 per hour for consulting services including time spent testifying at
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`any hearing that may be held. I am also being reimbursed for reasonable and cus-
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`tomary expenses associated with my work in this case. I receive no other forms of
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`compensation related to this case. No portion of my compensation is dependent or
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`otherwise contingent upon the results of this proceeding or the specifics of my tes-
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`timony.
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`C. Materials Reviewed
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`In formulating my opinions in this matter, I have reviewed the ’264 patent (Ex.
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`Intel Corp. et al. Exhibit 1006
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`10011) and its prosecution history. I have also reviewed the following materials:
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`Ex. 1001 U.S. Patent No. RE40,264 (“’264 patent”)
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`Ex. 1002 U.S. Patent 5,605,600 (“Muller”)
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`Ex. 1003 U.S. Patent 5,151,871 (“Matsumura”)
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`Ex. 1004 U.S. Patent 5,226,056 (“Kikuchi”)
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`Ex. 1005 U.S. Patent 6,063,710 (“Kadomura”)
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`Ex. 1007 U.S. Patent Application No. 08/567,224 (“’224 application”)
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`Ex. 1008 Wright, D.R. et al., A Closed Loop Temperature Control System for
`a Low-Temperature Etch Chuck, Advanced Techniques for Integrat-
`ed Processing II, Vol. 1803 (1992), pp. 321–329 (“Wright”)
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`Ex. 1009 U.S. Patent No. 5,711,849 (“’849 patent”)
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`Ex. 1010 U.S. Patent No. 5,446,824 (“Moslehi ’824”)
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`Ex. 1011 U.S. Patent No. 6,235,563 (“Oka”)
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`Ex. 1012 U.S. Patent No. 5,628,871 (“Shinagawa”)
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`Ex. 1013 U.S. Patent No. 5,393,374 (“Sato”)
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`Ex. 1014
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`PTAB Decision Denying Institution of Inter Partes Review, Lam
`Research Corp. v. Daniel L. Flamm, IPR2016-00470, Paper 6 (July
`1, 2016).
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` 1
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`The citations in this declaration to an “Exhibit” or “Ex.” refer to the Exhibits
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`to the Petition.
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`Intel Corp. et al. Exhibit 1006
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`PTAB Institution of Inter Partes Review, Lam Research Corp. v.
`Daniel L. Flamm, IPR2015-01768, Paper 7 (February 24, 2016).
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`PTAB Institution of Inter Partes Review, Lam Research Corp. v.
`Daniel L. Flamm, IPR2015-01764, Paper 7 (February 24, 2016).
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`
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`Ex. 1015
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`Ex. 1016
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`Ex. 1017 U.S. Patent No. 5,242,536 (“Schoenborn”)
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`Ex. 1018
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`Petition for Inter Partes Review of U.S. Patent No. RE40,264 E
`Fourth Petition, Lam Research Corp. v. Daniel L. Flamm, IPR2015-
`01768, Paper 1 (August 18, 2015).
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`Ex. 1019 U.S. Patent No. 5,174,856 (“Hwang”)
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`Ex. 1020 U.S. Patent No. 4,331,485 (“Gat”)
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`Ex. 1021 Declaration of Rachel J. Watters regarding Exhibit 1008
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`I also refer to my curriculum vitae, which is attached as Appendix A to this decla-
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`ration.
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`17.
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`In connection with live testimony in this proceeding, should I be
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`asked to provide it, I may use as exhibits various documents that refer to or relate
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`to the matters contained within this declaration, or which are derived from the re-
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`sults and analyses discussed in this declaration. Additionally, I may create or su-
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`pervise the creation of certain demonstrative exhibits to assist me in testifying.
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`18.
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`I am prepared to use any or all of the above-referenced documents,
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`and supplemental charts, models, and other representations based on those docu-
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`ments, to support my live testimony in this proceeding regarding my opinions cov-
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`ering the ’264 patent. If called upon to do so, I will offer live testimony regarding
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`Intel Corp. et al. Exhibit 1006
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`the opinions in this declaration.
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`D. Level of Ordinary Skill in the Art
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`19.
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`It is my understanding that the claims and specification of a patent
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`must be read and construed through the eyes of a person of ordinary skill in the art
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`as of the priority date of the claims at issue. Counsel has also advised me that to
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`determine the appropriate level of one of ordinary skill in the art, the following fac-
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`tors may be considered: (a) the types of problems encountered by those working in
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`the field and prior art solutions to those problems; (b) the sophistication of the
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`technology in question, and the rapidity with which innovations occur in the field;
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`(c) the educational level of active workers in the field; and (d) the educational level
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`of the inventor.
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` The relevant technology fields for the ’264 patent are semiconductor
`20.
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`processing and semiconductor processing equipment. In my opinion, for the pur-
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`poses of the ’264 patent, a person of ordinary skill in the art, as of the priority date
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`for the ’264 patent, would have generally have had either (i) a Bachelor’s degree in
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`engineering, physics, chemistry, materials science, or a similar field, and three or
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`four years of work experience in semiconductor manufacturing or related fields,
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`(ii) a Master’s degree in chemical engineering, electrical engineering, materials
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`science engineering, physics, chemistry, or a similar field and two or three years of
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`work experience in semiconductor manufacturing or related fields, or (iii) a Ph.D.
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`or equivalent doctoral degree in engineering, physics, chemistry, materials science
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`or a similar field, who had performed research related to semiconductor manufac-
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`turing or related fields.
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` Based on this understanding of a person of ordinary skill in the art at
`21.
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`the time of the alleged invention for the ’264 patent, I believe that I am at least a
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`person having ordinary skill in the art for purposes of the ’264 patent, and that I
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`was one prior to September 11, 1997. For example, my qualifications and experi-
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`ences discussed above, and in my curriculum vitae (Appendix A), demonstrate my
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`familiarity with and knowledge of the art of the ’264 patent. I therefore believe
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`that I am qualified to offer this declaration as to how such a person would have in-
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`terpreted the ’264 patent and the prior art on or about September 11, 1997. Unless
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`otherwise stated, my statements below refer to the knowledge, beliefs and abilities
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`of a person having ordinary skill in the art of the ’264 patent at the time of the pur-
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`ported invention of the ’264 patent.
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`II. Overview Regarding Technology
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`A. Priority Date
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`22.
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`I have been informed that a claim of a patent is not entitled to the pri-
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`ority date of an earlier application if that application does not disclose all limita-
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`tions of the claim in question.
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` The ’264 patent is a reissue of U.S. Patent No. 6,231,776 (the “’776
`23.
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`Intel Corp. et al. Exhibit 1006
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`patent”). The ’264 patent issued on April 29, 2008 from a reissue application filed
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`on May 14, 2003. The ’776 patent issued from Application No. 09/151,163, filed
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`on September 10, 1998. The ’776 patent claims priority to Provisional Application
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`No. 60/058,650, filed on September 11, 1997, and further claims priority as a con-
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`tinuation-in-part of Application No. 08/567,224, filed on December 4, 1995 (the
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`“’224 application.”)
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`24.
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`It is my opinion that claims 37-50 and 67 of the ’264 patent (“chal-
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`lenged claims”) are not entitled to a priority date earlier than September 11, 1997.
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`I express no opinion regarding the correctness of the September 11, 1997 or Sep-
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`tember 10, 1998 priority date, but I will use September 11, 1997 for purposes of
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`this declaration. In my opinion, however, December 4, 1995 is not the correct pri-
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`ority date for the challenged claims because application No. 08/567,224 does not
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`disclose or adequately support the subject matter claimed in the challenged claims.
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`1. The Challenged Independent Claims
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` Among other limitations, claim 37 recites: “performing a first film
`25.
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`treatment of a first portion of the film at a selected first substrate temperature,”
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`“with the substrate temperature control circuit, changing from the selected first
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`substrate temperature to a selected second substrate temperature, the selected sec-
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`ond substrate temperature being different from the selected first substrate tempera-
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`ture,” and “ wherein … and the substrate temperature control circuit is operable to
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`change the substrate temperature from the selected first substrate temperature to
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`the selected second substrate temperature within a preselected time period to pro-
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`cess the film.” (’264 patent at 23:6-20 (Ex. 1001)) Claim 37 further requires
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`“placing a substrate having a film thereon on a substrate holder2 within a chamber
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`of a plasma discharge apparatus … comprising: a substrate temperature control
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`system comprising a substrate temperature sensor … and a substrate holder tem-
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`perature control system comprising a substrate holder temperature sensor…” (’264
`
`patent at 22:59-23:5 (Ex. 1001))
`
` Accordingly, independent claim 37 recites processing a film on a sub-
`26.
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`strate at two different substrate etching temperatures and changing from the first
`
`substrate temperature for processing to the second substrate temperature for pro-
`
`cessing “within a preselected time period to process the film.” Claim 37 also re-
`
`cites elements that require both a substrate holder temperature sensor and a sub-
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`strate temperature control circuit that changes the substrate temperature from a first
`
`processing temperature to a second processing temperature.
`
`
`
` 2
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`
`
`Unless otherwise indicated, the terms “substrate holder,” “chuck,” “wafer
`
`stage,” and “stage” are used interchangeably for purposes of this declaration.
`
`
`
`- 11 -
`
`Intel Corp. et al. Exhibit 1006
`
`

`
`
`
`2. The Disclosure of Application No. 08/567,224, Filed on Decem-
`ber 4, 1995
`
`
`27.
`
`In my opinion, the ’224 application, filed on December 4, 1995, does
`
`not include written description sufficient to support any of claims 37-50 and 67 of
`
`the ’264 patent. Thus, the challenged claims are entitled to a priority date of no
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`earlier than September 11, 1997, the date of Provisional Application No.
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`60/058,650.
`
` Specifically, claim 37 recites the concepts of processing (e.g., etching)
`28.
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`a film at a selected first temperature and further processing at a selected second
`
`temperature and changing from the first temperature to the second temperature
`
`within a specific preselected time period.
`
`
`29.
`
`I was unable to find any discussion in the ’224 application of chang-
`
`ing the temperature of the substrate from a first temperature to a second tempera-
`
`ture within a preselected time period to process the film. Furthermore, the only
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`disclosure of two-temperature processing in the ’224 application is a disclosure of
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`a technique well known at the time, changing the temperature by transferring a wa-
`
`fer between substrate holders held at different temperatures (either in the same
`
`processing chamber or in different chambers). Specifically, the ’224 application
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`discloses changing the temperature during plasma ashing by transferring the wafer
`
`from a first resist stripping chamber with a half-wave helical resonator, in which a
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`wafer is processed at a low temperature, to a second chamber with a resonator op-
`
`
`
`- 12 -
`
`Intel Corp. et al. Exhibit 1006
`
`

`
`
`
`erating at a full-wave multiple, in which a wafer is processed at a higher tempera-
`
`ture:
`
`An implant resist stripping process was performed to re-
`move the top implant hardened resist. This occurred by
`stripping using an “un-balanced” phase and anti-phase
`coupling relationship in a half-wave helical resonator.
`The half-wave helical resonator was configured in one of
`the process chambers. In this chamber, the pedestal had a
`temperature of about 40ºC to maintain a low wafer tem-
`perature. This low wafer temperature was maintained. to
`reduce the possibility of “popping.” Popping occurs
`when vapor in the underlying photoresist explodes
`through the implant hardened resist.
`
`After the top hardened layer was removed. The wafer
`was transferred into a chamber operating at a full-wave
`multiple. This chamber operated at a frequency of about
`27.12 MHz at a full-wave multiple. The pedestal of this
`chamber was at 150 to 200ºC. The full-wave structure
`provided for balanced phase and anti-phase coupled cur-
`rents, thereby reducing the amount of capacitively cou-
`pled plasma, which can be detrimental to the underlying
`substrate. In this step, overashing was performed to sub-
`stantially remove all photoresist material from the wafer.
`No damage occurred to the underlying substrate during
`the overashing step.
`
`
`
`- 13 -
`
`Intel Corp. et al. Exhibit 1006
`
`

`
`Once the photoresist has been stripped, the wafer is
`cooled. In particular, the wafer is removed from the, full-
`wave multiple process chamber, and placed on the cool-
`ing station. This cooling station reduces the temperature
`of the wafer (which was heated). This wafer is then re-
`loaded back into its wafer cassette.
`
`
`
`(’224 application at 33:16-34:6 (Ex. 1007)) This passage does not disclose chang-
`
`ing the temperature within a particular time period. I cannot find any other part of
`
`the ’224 application that contains those teachings. Furthermore, based on my re-
`
`view of the ’224 application, it does not discuss changing the processing tempera-
`
`ture of the same substrate holder.
`
` Claim 37 further requires measuring the temperature of the substrate,
`30.
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`which is used to control the change from a first processing temperature to a second
`
`processing temperature, “a substrate temperature control system comprising a sub-
`
`strate temperature sensor and a substrate temperature control circuit operable to ad-
`
`just the substrate temperature to a predetermined substrate temperature value with
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`a first heat transfer process” and “with the substrate temperature control circuit,
`
`changing from the selected first substrate temperature to a selected second sub-
`
`strate temperature….” (’264 patent at 22:62-66, 23:7-10 (Ex. 1001))
`
` The ’224 application does not disclose using a measured substrate
`31.
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`temperature or using a control circuit to change the temperature of the substrate.
`
`
`
`- 14 -
`
`Intel Corp. et al. Exhibit 1006
`
`

`
`
`
`The ’224 application discloses, again in the context of plasma ashing, a substrate
`
`support that is heated resistively and has a thermocouple to sense the temperature
`
`of the substrate support:
`
`The wafer 618 is a 6-inch (250mm) <100> type wafer
`with approximately 1.25 microns of spin-coated
`Mitsubishi Kasei positive photoresist MPR-4000. This
`wafer was ashed on the grounded 10 inch diameter wafer
`support 616. This support was resistivity heated and, the
`temperature of the substrate support was sensed with a
`thermocouple.
`
`(’224 application at 30:24-28 (Ex. 1007)) This is different from measuring the
`
`substrate temperature. Indeed, claim 37 also discloses a substrate holder control
`
`circuit and a substrate holder temperature sensor to measure and adjust the sub-
`
`strate holder temperature value.
`
` The ’224 application does not support the material recited in inde-
`32.
`
`pendent claim 37, and thus does not provide sufficient disclosure to support any of
`
`the challenged claims.
`
`B.
`
`State of the Art from the Perspective of a Person of Ordinary Skill
`in the Art at the Time of the Alleged Invention
`
` The ’264 patent generally relates to methods for performing semicon-
`33.
`
`ductor processing with in situ temperature changes (meaning the substrate being
`
`processed stays on the same substrate holder during the first processing step