`571-272-7822
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` Paper 31
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` Entered: January 31, 2019
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`MICRON TECHNOLOGY, INC. and
`SAMSUNG ELECTRONICS COMPANY, LTD.1,
`Petitioner,
`
`v.
`
`DANIEL L. FLAMM,
`Patent Owner.
`____________
`
`Case IPR2017-00281
`Patent RE40,264 E
`____________
`
`
`Before CHRISTOPHER L. CRUMBLEY, JO-ANNE M. KOKOSKI, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
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`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
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`
`
`
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`1 Samsung Electronics Company, Ltd. was joined as a party to this
`proceeding via a Motion for Joinder in IPR2017-01750.
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`
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`IPR2017-00281
`Patent RE40,264 E
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`
`I. INTRODUCTION
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`In this inter partes review, instituted pursuant to 35 U.S.C. § 314,
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`Intel Corporation, GLOBALFOUNDRIES U.S., Inc., Micron Technology,
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`Inc. and Samsung Electronics Company, Ltd., (collectively “Petitioner”)
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`challenge the patentability of claims 37–50 and 67 of U.S. Patent No.
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`RE40,264 (Ex. 1001, “the ’264 patent”), owned by Daniel L. Flamm.
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`(“Patent Owner”).
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`We have jurisdiction under 35 U.S.C. § 6. This Final Written
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`Decision, issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73,
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`addresses issues and arguments raised during trial. For the reasons discussed
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`below, we determine that Petitioner has shown by a preponderance of the
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`evidence that claims 37–50 and 67 of the ’264 patent are unpatentable.
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`A. Procedural History
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`On December 2, 2016, Intel Corporation, GLOBALFOUNDRIES
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`U.S., Inc., and Micron Technology, Inc. (collectively, “Initial Petitioners”)
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`filed a Petition requesting an inter partes review of claims 37–50 and 67 of
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`the ’264 patent. Paper 2 (“Pet.”). Patent Owner filed a Preliminary
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`Response. Paper 8. On June 13, 2017, we instituted an inter partes review of
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`the challenged claims. Paper 10 (“Decision on Institution” or “Dec. on
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`Inst.”) Subsequent to institution, Samsung Electronics Company, Ltd.
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`(“Samsung”) filed a petition and motion for joinder with the instant
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`proceeding. Samsung Electronics Company, Ltd. v. Daniel L. Flamm, Case
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`IPR2017-01751, Papers 1, 3. On September 15, 2017, we granted
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`Samsung’s petition and motion for joinder, joining Samsung as a petitioner
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`in this inter partes review. Paper 14, 7.
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`2
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`IPR2017-00281
`Patent RE40,264 E
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`Thereafter, Patent Owner filed a Patent Owner Response (Paper 13,
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`“PO Resp.”) and Petitioner filed a Reply (Paper 15, “Reply”). The Petition is
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`supported by the Declaration of Dr. John Bravman (Ex. 1006, “the Bravman
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`Declaration”) and the Reply is supported by the Reply Declaration of
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`Dr. John Bravman (Ex. 1024, “the Bravman Reply Declaration”). Patent
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`Owner’s Response is supported by the Declaration of Dr. Daniel L. Flamm2
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`(Ex. 2001, “the Flamm Declaration”).
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`Oral hearing was requested by both parties. Papers 16, 17. A
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`consolidated oral hearing for this proceeding and Cases IPR2017-00279,
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`IPR2017-00280, and IPR2017-000282, involving the same parties and
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`the ’264 patent, and Cases IPR2017-00391, IPR2017-00392, and IPR2017-
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`00406, involving the same parties and unrelated patents, was held on
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`March 7, 2018. A transcript of the consolidated hearing has been entered
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`into the record. Paper 29 (“Tr.”).
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`B. Related Proceedings
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`Petitioner reports that the Patent Owner has asserted the ’264 patent in
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`five proceedings in the Northern District of California (Case Nos. 5:16-cv-
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`01578-BLF, 5:16-cv-1579-BLF, 5:16-cv-1580-BLF, 5:16-cv-1581-BLF, and
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`5:16-cv-02252-BLF) and that Lam Research Corporation has filed a
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`declaratory judgment action against Patent Owner on the ’264 patent, also in
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`the Northern District of California (Case No. 5:15-cv-01277-BLF). Pet. 2.
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`
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`2 Daniel L. Flamm is both the Patent Owner and Patent Owner’s declarant in
`this proceeding.
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`3
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`IPR2017-00281
`Patent RE40,264 E
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`Petitioner also challenges certain claims of the ’264 patent in
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`IPR2017-00279, IPR2017-00280, and IPR2017-00282, which were filed
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`concurrently with the Petition in this proceeding. The parties also identified
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`nine other IPR petitions for review of the ’264 patent, filed by Lam Research
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`Corporation or Samsung, none of which are currently pending. See Pet. 2;
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`Prelim. Resp. 1 (identifying IPR2015-01759 (institution denied); IPR2015-
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`01764 (terminated-settled); IPR2015-01766 (institution denied); IPR2015-
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`01768 (terminated-settled); IPR2016-00468 (institution denied); IPR2016-
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`00469 (institution denied); and IPR2016-00470 (institution denied);
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`IPR2016-01510 (institution denied) and; IPR2016-01512 (Final Written
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`Decision – challenged claims unpatentable)).
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`C. The ’264 Patent
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`The ’264 patent, titled “Multi-Temperature Processing,” relates
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`generally to methods and systems for controlling the heating and cooling
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`time of a substrate (e.g., wafer) during plasma processing in a single
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`processing chamber. See, e.g., Ex. 1001, 1:18–21. A “plasma etching
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`apparatus according to the present invention” is shown in Figure 1 of
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`the ’264 patent, reproduced below. Id. at 2:66–67.
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`4
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`IPR2017-00281
`Patent RE40,264 E
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`Figure 1 above illustrates a plasma etching apparatus having chamber
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`12 and a substrate holder (product support chuck or pedestal 18) for holding
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`a substrate (product 28, such as a wafer to be etched). Id. at 3:24–25, 3:32–
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`33, 3:40–42. The substrate holder, which is thermally coupled to the
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`substrate, “can rapidly change its temperature.” Id. at 3:51–55.
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`One embodiment of a temperature control system according to the
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`invention is shown in Figure 7 below. Id. at 3:11–13, 15:65–67.
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`5
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`IPR2017-00281
`Patent RE40,264 E
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`Figure 7, shown above, depicts a temperature control system having
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`substrate holder (also called “wafer chuck” or “wafer holder”) 701, heater
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`705, heat transfer fluid reservoir 713, and heat exchanger 723. Id. at 15:65–
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`16:8. Fluid is “pumped from the reservoir through the heating unit, which
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`selectively sets the temperature of the fluid.” Id. at 16:9–11. The fluid
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`“transfers energy in the form of heat to the wafer holder to a desirable
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`temperature.” Id. at 16:14–16. In another embodiment, the fluid can also be
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`cooled using heat exchanger 723. Id. at 16:20–21. In a specific embodiment,
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`“system 700 operates in a manner to program a process temperature of the
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`substrate holder.” Id. at 16:28–30. An electrical heater heats the fluid to a
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`desired temperature, which is “determined by comparing the desired wafer
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`or wafer chuck set point temperature to a measured wafer or wafer chuck
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`temperature.” Id. at 16:36–41.
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`A microprocessor-based system can be used to control the
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`temperature of the substrate holder by selectively turning elements of the
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`system (e.g., heater, fluid reservoir) on or off. Id. at 17:1–9. For example, if
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`the measured temperature of the wafer or chuck is below the desired
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`temperature “a suitable control algorithm such as a proportional controller or
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`a proportional-integral-derivative (i.e., ‘PID’) controller algorithm increases
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`the temperature by supplying more power to the heater.” Id. at 16:41–46.
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`“The heat exchanger, fluid flow rate, coolant-side fluid temperature, heater
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`power, chuck, etc., should be designed using conventional means to permit
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`the heater to bring the fluid to a setpoint temperature and bring the
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`temperature of the chuck and wafer to predetermined temperatures within
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`6
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`IPR2017-00281
`Patent RE40,264 E
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`specified time intervals and within specified uniformity limits.” Id. at 16:60–
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`67.
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`The ’264 patent states that conventional processing of resist layers,
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`which is performed at low temperatures in order to help prevent rupturing of
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`cross-linked layers and contaminative particulate matter, requires excessive
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`time and lower throughput. Id. at 2:17–26. The ’264 patent states that the
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`present invention overcomes these disadvantages by removing the ion
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`implanted layer at a lower temperature followed by rapidly removing a
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`majority of resist at a higher temperature. See id. at 2:26–30. For example, a
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`“sequence of temperature changes” may be employed to avoid “various
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`types of processing damage to the device and material layers.” Id. at 2:34–
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`37. Figure 10, shown below, illustrates a simplified process according to the
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`invention. Id. at 18:58–59.
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`7
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`The process shown in Figure 10, above, plots changes in temperature
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`against processing time. See id., Fig. 10; see also id. at 18:58–19:64
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`(providing details of the process shown in Figure 10). For example, during
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`the isotropic breakthrough step (time A through BB), an SF6 plasma is used
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`to remove native oxide at a low temperature, such as room temperature. Id.
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`at 18:63–66, Fig. 10. At the end of this step, at time BB, the control program
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`increases within several seconds to a higher steady state value at time B. Id.
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`at 19:8–10. The tungsten silicide layer is then etched at a constant
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`temperature until the layer is breached. Id. at 19:10–15. At point D, the
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`8
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`IPR2017-00281
`Patent RE40,264 E
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`wafer temperature is gradually reduced in order to achieve a slower and
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`more anisotropic polysilicon etching step. Id. at 19:36–28.
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`D. Illustrative Claims
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`Of the claims challenged by Petitioner, only claim 37 is independent.
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`Claim 37, with bracketed material and formatting added for clarity, is
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`reproduced below:
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`37. A method of processing a substrate during
`manufacture of a device, the method comprising:
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`the
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`[a] placing a substrate having a film thereon on a substrate
`holder within a chamber of a plasma discharge
`apparatus,
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`[b] the plasma discharge apparatus comprising:
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`a substrate temperature control system comprising a
`substrate
`temperature sensor and a
`substrate
`temperature control circuit operable to adjust the
`substrate temperature to a predetermined substrate
`temperature value with a first heat transfer process; and
`a substrate holder
`temperature control system
`comprising a substrate holder temperature sensor and a
`substrate holder temperature control circuit operable to
`adjust
`the substrate holder
`temperature
`to a
`predetermined substrate holder temperature value with
`a second heat transfer process;
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`[c] performing a first film treatment of a first portion of the
`film at a selected first substrate temperature;
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`[d] with the substrate temperature control circuit, changing
`from the selected first substrate temperature to a
`selected second substrate temperature, the selected
`second substrate temperature being different from the
`selected first substrate temperature; and
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`[e] performing a second film treatment of a second portion of
`the film at the selected second substrate temperature;
`9
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`IPR2017-00281
`Patent RE40,264 E
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`[f] wherein the substrate holder is heated above room
`temperature during at least one of the first or the second
`film treatments, and the substrate temperature control
`circuit is operable to change the substrate temperature
`from the selected first substrate temperature to the
`selected second substrate temperature within a
`preselected time period to process the film.
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`
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`E. Instituted Grounds
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`We instituted an inter partes review of claims 37–50 and 67 on the
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`following grounds of unpatentability:
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`(1) Whether claims 37–46 are unpatentable under § 103(a) over the
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`combination of Kadomura3 and Matsumura;4
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`(2) Whether claims 40, 42, 45, 49, and 67 are unpatentable under
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`§ 103(a) over the combination of Kadomura, Matsumura, and Muller;5
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`(3) Whether claim 50 is unpatentable under § 103(a) over the
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`combination of Kadomura, Matsumura, and Kikuchi;6
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`(4) Whether claims 37–46, 50, and 67 are unpatentable are
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`unpatentable under § 103(a) over the combination of Kikuchi and
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`Matsumura;
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`
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`3 U.S. Patent No. 6,063,710, filed Feb. 21, 1997, issued May 16, 2000
`(Ex. 1005, “Kadomura”).
`4 U.S. Patent No. 5,151,871, filed Jun. 15, 1990, issued Sept. 29, 1992
`(Ex. 1003, “Matsumura”).
`5 U.S. Patent No. 5,605,600, filed Mar. 13, 1995, issued Feb. 25, 1997 (Ex.
`1002, “Muller”).
`6 U.S. Patent No. 5,226,056, filed Jan. 9, 1990, issued July 6, 1993 (Ex.
`1004, “Kikuchi”).
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`10
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`IPR2017-00281
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`(5) Whether claims 41 and 49 are unpatentable under § 103(a) over
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`the combination of Kikuchi, Matsumura, and Muller, and
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`(6) Whether claims 37, 47, and 48 are unpatentable under § 103(a) as
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`having been obvious over the combination of Moslehi ’824,7 Oka,8 and
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`Matsumura. Dec. on Inst. 40.
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`II. DISCUSSION
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`A. Principles of Law
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`To prevail on its challenges, Petitioner must demonstrate by a
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`preponderance of the evidence that the claims are unpatentable. 35 U.S.C.
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`§ 316(e); 37 C.F.R. § 42.1(d). A claim is unpatentable under 35 U.S.C.
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`§ 103(a) if the differences between the claimed subject matter and the prior
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`art are such that the subject matter, as a whole, would have been obvious at
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`the time of the invention to a person having ordinary skill in the art. KSR
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`Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 406 (2007). The question of
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`obviousness is resolved on the basis of underlying factual determinations
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`including: (1) the scope and content of the prior art; (2) any differences
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`between the claimed subject matter and the prior art; (3) the level of ordinary
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`skill in the art; and (4) objective evidence of nonobviousness, i.e., secondary
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`considerations.9 See Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
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`
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`7 U.S. Patent No. 5,466,824, filed May 17, 1993, issued Aug. 29, 1995
`(Ex. 1010, “Moslehi”)
`8 U.S. Patent No. 6,235,563 B1, filed Nov. 7, 1991, issued May 22, 2001
`(Ex. 1011, “Oka”).
`9 The record does not contain evidence or argument of objective evidence of
`non-obviousness.
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`11
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`IPR2017-00281
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`The level of ordinary skill in the art may be reflected by the prior art of
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`record. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001).
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`B. Level of Ordinary Skill in the Art
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`Citing its declarant, Petitioner contends that a person of ordinary skill
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`in the art at the relevant time (“POSITA”) would have had (i) a Bachelor’s
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`degree in chemical engineering, materials science engineering, electrical
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`engineering, physics, chemistry, or a similar field, and three or four years of
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`work experience in semiconductor manufacturing or related fields; or (ii) a
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`Master’s degree in chemical engineering, materials science engineering,
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`electrical engineering, physics, chemistry, or a similar field, and two or three
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`years of work experience in semiconductor manufacturing or related fields;
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`or (iii) a Ph.D. in chemical engineering, materials science engineering,
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`electrical engineering, physics, chemistry, or a similar field.
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`Pet. 24 (citing Ex. 1006 ¶¶ 19–21).
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`Patent Owner does not contest Petitioner’s description of the level of
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`ordinary skill in its Response. Based on our review of the ’264 patent, the
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`cited prior art, and the testimony of the parties’ declarants, we agree with
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`Petitioner’s assessment of the level of ordinary skill in the art, and apply it
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`for purposes of this Decision. See Okajima, 261 F.3d at 1355 (explaining
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`that specific findings regarding ordinary skill level are not required “where
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`the prior art itself reflects an appropriate level and a need for testimony is
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`not shown”).
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`12
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`C. Claim Construction
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`The ’264 patent is expired.10 For claims of an expired patent, the
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`Board’s claim interpretation is similar to that of a district court. See In re
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`Rambus, Inc., 694 F.3d 42, 46 (Fed. Cir. 2012). Claim terms are given their
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`ordinary and customary meaning as would be understood by a person of
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`ordinary skill in the art at the time of the invention, and in the context of the
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`entire patent disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257
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`(Fed. Cir. 2007). Only those terms in controversy need to be construed, and
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`only to the extent necessary to resolve the controversy. See Vivid Techs., Inc.
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`v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
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`For purposes of our Decision on Institution, we determined that none
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`of the claims terms requires an explicit construction. Dec. on Inst. 10.
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`During the instituted trial, neither party disagreed with this assessment, and
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`we again see no need to provide an express construction for any of the terms
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`in the challenged claims.
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`
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`10 Neither party disputes that the ’264 patent has expired. The earliest patent
`application referenced for the benefit of priority under 35 U.S.C. § 120 for
`the ’264 patent was filed on December 4, 1995, and the patent has no term
`extensions. The term of the ’264 patent, therefore, expired no later than
`December 4, 2015. See 35 U.S.C. § 154(a)(2) (2012 & Supp. III 2015)
`(stating that the term of a patent grant ends twenty (20) years from the date
`on which the application for the patent was filed in the United States, “or, if
`the application contains a specific reference to an earlier filed application or
`applications under section 120, 121, 365(c), or 386(c), from the date on
`which the earliest such application was filed”).
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`D. Priority Date for the Challenged Claims of the ’264 Patent
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`The ’264 patent is a reissue of U.S. Patent No. 6,231,776 B1 (“the
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`’776 patent”), which issued from U.S. Patent Application No. 09/151,163
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`(“the ’163 application”) filed September 10, 1998. Ex. 1001, [64]. The ’163
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`application claims priority to both (1) U.S. Provisional Application No.
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`60/058,650 (“the ’650 provisional application”), filed on September 11,
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`1997, and (2) U.S. Patent Application No. 08/567,224 (“the ’224
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`application”), filed on December 4, 1995. Id. at [64], [60], [63], 1:11–15.
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`Petitioner contends that the challenged claims of the ’264 patent are
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`not entitled to claim priority to a filing date any earlier than the
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`September 11, 1997, filing date of the ’650 provisional application, and,
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`therefore, each of the asserted references qualifies as prior art to the
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`challenged claims. See Pet. 9–12, 16, 18. Specifically, Petitioner contends
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`that the ’264 patent is not entitled to claim priority to the earlier filed ’224
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`application because the ’224 application fails to disclose, inter alia,
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`changing the temperature of a substrate from “the selected first substrate
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`temperature to the selected second substrate temperature within a preselected
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`time period” as required by independent claim 37. Id. at 9–10 (citing
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`Ex. 1006 ¶¶ 30–31).
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`Patent Owner has not introduced any evidence or argument that
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`the ’224 application provides written description support for the independent
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`claim. See generally PO Resp. Nor does Patent Owner contend that any of
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`the asserted references are not prior art to the ’264 patent. Evaluating
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`Petitioner’s unchallenged arguments, we determine that the challenged
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`claims of the ’264 patent are not entitled to claim priority to the December 4,
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`1995, filing date of the ’224 application. As a consequence, we find that
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`Kadomura, which was filed on February 21, 1997, Oka, which was filed on
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`November 7, 1991, and the remaining asserted references, each of which
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`issued before the September 11, 1997, filing date of the ’650 provisional
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`application, qualify as prior art to the challenged claims of the ’264 patent.
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`See Tech. Licensing Corp. v. Videotek, Inc., 545 F.3d 1316, 1327 (Fed. Cir.
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`2008) (stating that the patent owner has the burden of production to make a
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`claim of priority that the challenged claims are entitled to a filing date prior
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`to the date of the alleged prior art).
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`E. Asserted Art
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`1. Kadomura
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`Kadomura, titled “Method and Apparatus for Dry Etching with
`
`Temperature Control,” discloses, inter alia, a multi-temperature process for
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`etching portions of a semiconductor wafer. Ex. 1005 at [54], [57]. The
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`etching tool of Kadomura shown in Figure 4 has a wafer stage for holding
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`the wafer/substrate during processing, thermometer for measuring wafer
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`temperature, and a control device, having a PID controller, for controlling
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`the temperature of wafer based on temperature measurements from the
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`thermometer. See id. at 11:36–59, 12:37–48, Fig. 4. Kadomura adjusts the
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`wafer temperature by adjusting the temperature of wafer stage 12, using a
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`heater or chiller 17. See id. at 10:7–10 (stating the change in temperature of
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`specimen W is controlled by “the cooling means and the heater disposed to
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`the stage 12”); see also id. at 12:37–38 (the “cooling degree for the
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`specimen [] is controlled by the flow rate of the coolant supplied from the
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`chiller”). The temperature sensed by thermometer 18 is detected by a
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`15
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`feedback control device (feedback control means) 25 comprising a PID
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`controller. Id. at 12:39–43. Kadomura explains that feedback control device
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`25 controls the cryogenic valve “to obtain a gas coolant flow rate previously
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`determined by experiment or calculation based on the difference between the
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`detected temperature and the predetermined temperature for the specimen.”
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`Id. at 12:43–49.
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`Kadomura discloses several examples of multi-temperature etch
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`processes. For example, one process includes a first step of etching silicide
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`and polysilicon at room temperature (20°C) and a second step of etching
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`polysilicon at a lower temperature (-30°C). Id. at 6:18–7:7; Figs. 1A–1C. In
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`between these etching steps, gases remaining in the diffusion chamber are
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`exhausted and the etching gas used in the second step is introduced; the gas
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`is stabilized and the inside of the diffusion chamber is controlled to a
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`constant pressure. Id. at 6:36–44. During “a series of such operations, that is
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`directly after the completion of the etching of the first step,” gas coolant at
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`-140°C from the chiller is supplied to the wafer stage to rapidly cool the
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`wafer. Id. at 6:44–51. The temperature of the wafer reaches -30ºC “within a
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`short period of time of about 30 sec by such rapid cooling.” Id. at 6:52–55.
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`After completing these two steps, a heater within substrate holder
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`stage 12 returns the wafer specimen temperature back up to 20ºC. Id. at
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`7:31–47. The tool then repeats the same two-temperature etch process. Id. at
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`6:63–7:7, 7:31–47.
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`In another embodiment, the first etching step occurs at a low
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`temperature (i.e., -30ºC) and the second etching step is applied at a much
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`higher temperature (i.e., 50ºC). Id. at 9:54–10:27. A control mechanism for
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`16
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`IPR2017-00281
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`the cooling means and the heater disposed to the wafer stage are controlled
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`to rapidly heat the specimen W between the etching steps. See id. at 10:7–
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`10. The temperature of the wafer reaches 50ºC “within a short period of time
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`of about fifty (50) seconds.” Id. at 10:11–27.
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`2. Matsumura
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`Matsumura generally relates to heat-processing semiconductor wafers
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`and, in particular, to controlling the temperature of a semiconductor wafer
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`during processing. See Ex. 1003, 1:8–13; see also id. at 2:60–65 (stating one
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`objective is to provide a “simpler method of heat-processing semiconductor
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`devices whereby temperatures of the semiconductor devices can be
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`controlled at devices-heating and -cooling times so as to accurately control
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`their thermal history curve”).
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`Matsumura’s temperature control system uses a central processing
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`unit (“CPU”) having a PID controller that stores “as a predetermined recipe,
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`information showing a time-temperature relationship and applicable for
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`either heating [a wafer] to a predetermined temperature for a predetermined
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`period of time or cooling the [wafer] from a predetermined temperature over
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`a predetermined period of time.” See id. at 3:1–7, 5:64–6:6, 8:56–62; see
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`also id. at [57] (stating a “control system controls either the heating of the
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`wafer or the cooling thereof, or both, in accordance with the detected
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`temperature signal and the [stored] information”).
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`An example of a predetermined recipe is shown in Figure 9 below.
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`See id. at 8:56–57.
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`Figure 9, shown above, is a diagram showing a “recipe relating to a thermal
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`history curve of a wafer-stage,” showing temperature as a function of time.
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`See id. at 4:42–43; see also id. at 8:56–68 (stating “Points P10 to P19 shown
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`in figure 9 are set in the recipe to surely reproduce the thermal history curve
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`of the wafer”). The information “relating to temperatures and times at these
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`points P10 to P19 is inputted as a command temperature table to the CPU.”
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`Id. at 8:59–62.
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`Figure 5A, reproduced below, is a schematic diagram of an adhesion
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`unit included in a resist processing system of Matsumura that includes wafer
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`stage 12 for heating and cooling wafer W in accordance with recipes
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`inputted into a CPU. See id. at 4:28–29, 5:13–17, 6:6–9.
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`Figure 5A, reproduced above, depicts adhesion unit 42 having wafer-stage
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`12 that can heat and cool the semiconductor wafers (e.g., wafer W). Id. at
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`5:14–16. Recipes, including heating and other conditions, are inputted to the
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`CPU by keyboard 20a. Id. at 6:6–9. Thermometer 24, which has thermal
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`sensor attached to thin film 14, is attached to a control system 20. See id. at
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`5:57–6:4. Based on the recipe and temperature detecting signal, control
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`system 20 controls the amount of coolant supplied from the cooling system
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`to cooling jacket 22 under stage 12 and the current applied to conductive
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`thin film 14 to raise the temperature of the wafer. Id. at 5:64–6:61.
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`Matsumura states that, although “the present invention has been
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`applied to the adhesion and baking processes for semiconductor wafers in
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`the above-described embodiments . . . , it can also be applied to any of the
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`ion implantation, [chemical vapor deposition (“CVD”)], etching and ashing
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`processes.” Id. at 10:3–7.
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`3. Muller
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`Muller is directed to methods of shaping etch profiles by controlling
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`wafer temperature using an electrostatic chuck and coolant circulating
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`through a cathode and by changing the pressure of the gas filled in the gaps
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`between the wafer and the cathode. Ex. 1002 at [54], Abstract, 1:7–12, 1:44–
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`64, 4:51–5:25. Figure 4 of Muller, which depicts an example of an apparatus
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`used to accomplish the multi-temperature etching methods, is reproduced
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`below.
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`Figure 4 depicts wafer 104, electrostatic chuck 105, cathode 106, and gas
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`filled gap 110 between cathode 106 and wafer 104. Id. at 4:33–54.
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`Muller teaches that the change in taper angle of etched trenches correlates
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`with increasing wafer temperature during the etching processes. Ex. 1002,
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`3:33–66, Figs. 1, 2. Muller explains that changing pressure of the gas filled
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`in the gaps between the wafer and cathode, which can be accomplished in a
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`very short period of time, results in an immediate effect on wafer
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`temperature. Id. For example, wafer temperature can be increased by
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`approximately 50ºC over a time of “several seconds” during etching. Id.at
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`4:64–5:25, 5:41–48.
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`In one example, Muller teaches performing an initial etch at either
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`125ºC or 145ºC. Id. at 3:45–52, 3:56–66. The two etching temperature
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`examples correspond to two different coolant temperatures. For example,
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`use of a cathode coolant at 10ºC results in a wafer temperature of
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`approximately 125°C, while use of a cathode coolant at 30ºC results in a
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`wafer temperature of approximately 145ºC. Id. at 3:45–52. Figure 3 below
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`shows the wafer temperature at the two cathode coolant temperatures as a
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`function of time.
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`Figure 3 depicts a graph illustrating the change in wafer temperature for
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`various coolant temperatures as a function of etch time.
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`In another example of an etching process, the gas-filled gap is pressurized
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`for a first time period and then the pressure in the gap is rapidly changed to a
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`second pressure for a second period of time. Id. at 4:64–5:3. Then, the gas
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`pressure underneath the chuck is changed to increase wafer temperature by
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`50ºC in “several seconds” during etching. Id. at 4:64-5:25, 5:41–48. In this
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`example, using a 30°C coolant, the initial pressure is maintained for 70
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`seconds, after which the gap pressure is decreased for the remaining 6
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`minutes of etch time. Id. at 5:26–33.
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`4. Kikuchi
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`Kikuchi is directed to methods for plasma ashing a resist film by
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`initially controlling the temperature of the substrate below that at which
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`explosion of the resist film occurs until after a surface portion of a resist film
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`has been removed. Ex. 1004, Abstract. Kikuchi describes ashing a wafer’s
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`photoresist film at two sequential temperatures using either infrared heat
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`lamp 5 or hot plate 7 to raise the temperature, and thermometers 10, 66 to
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`measure the wafer and hot plate temperatures. See, e.g., id. at 1:56–2:3,7:20–
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`34, 7:62–68, 8:8–14, 11:6–9, Figs. 12, 13. Figure 1 of Kikuchi is reproduced
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`below.
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`Figure 1 depicts a “conventional ashing method” in which a substrate is
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`placed on rack 8 and is heated by infrared lamps 5 to a predetermined
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`temperature in about 5 seconds (as shown by curve A in Figure 3). Id. at
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`1:56–60. The temperature of the substrate is controlled by infrared
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`thermometer 9. Id. at 1:56–65, 4:62–63. Kikuchi explains that in this
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`embodiment, it is difficult to coat the resist film 11 on only the front surface
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`of substrate 1 as film will also be deposited on the rear surface of substrate
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`1. Id. at 2:47–61. Kikuchi states that if the substrate 1 is heated in contact
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`with hot plate 7 to remove the resist film by ashing, hot plate 7
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`prevents the reactive radicals from working on that resist film and the resist
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`film may remain on the rear surface of substrate 1. Id. at 2:61–67; Figs. 8, 9.
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`Figure 11, shown below, depicts a sectional side view of an embodiment of
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`the invention of Kikuchi.
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`Figure 11 depicts a semiconductor substrate (wafer) 1, thermometer
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`10, pins 16, and heating means 51 having hot plate 7, inside of vacuum
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`treatment chamber 4. Id. at 7:19–33. Kikuchi describes using the pins to
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`suspend the substrate being ashed above the hot plate to remove a surface
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`layer of photoresist, lowering pins 16 to place the substrate on the hot plate,
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`and then raising the temperature to ash the remaining portion of the
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`photoresist at a high temperature. Id. at 8:1–14; see also Ex. 1006 ¶ 86.
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`Kikuchi describes etching a photoresist over a range of temperatures,
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`with an initial step of 70°C–160°C and a rapid increase to 200°C over a time
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`period of 5 to 10 seconds. See, e.g., Ex. 1004, 2:37–46, 3:33–44, 5:46–54,
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`Figs. 12, 13.
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`5. Moslehi ’824
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`Moslehi ’824 is directed to a lamp-heated chuck for uniform
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`semiconductor wafer processing in lamp-heated and radio-frequency plasma
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`device processing applications, over a wide range of temperatures that may
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`reach as high as 1100°C. See Ex. 1010, [54], 1:9–15, 1:60–65, 5:16–21.
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`Moslehi ’824 states that its chuck can be used to uniformly heat a
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`semiconductor wafer from its back side and avoid the edge non-uniformity
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`or cooling problems typical of known single wafer rapid thermal processing
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`(RTP) based semiconductor device fabrication equipment. See id. at 4:16–
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`21. Moslehi ’824 also states that its chuck “may serve as a source of RF
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`frequency for local RF plasma generation from activated species for plasma-
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`enhanced deposition and etching or cleaning processes.” Id. at 10:34–39.
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`Figure 3 of Moslehi ’824, reproduced below, illustrates a single-wafer
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`semiconductor fabrication reactor. Id. at 6:10–13.
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`Figure 3 depicts single-wafer semiconductor fabrication reactor 50 having
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`process chamber 72, semiconductor wafer 38, chuck assembly 82, he