UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`AND MICRON TECHNOLOGY, INC.,
`Petitioners,
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`v.
`
`DANIEL L. FLAMM,
`
`Patent Owner.
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`PTAB Case No. IPR2017-00280
`Patent No. RE40,264 E
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`
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`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. RE40,264 E
`
`Claims 27-36, 51-55, 66 & 68-69
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`

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`TABLE OF CONTENTS
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`Page
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`
`I.
`Introduction ..................................................................................................... 1
`II. Mandatory notices .......................................................................................... 1
`A.
`Real party in interest............................................................................. 1
`B.
`Related matters ..................................................................................... 2
`C.
`Notice of counsel and service information ........................................... 2
`III. Requirements for inter partes review ............................................................. 4
`A. Ground for standing ............................................................................. 4
`B.
`Identification of challenge .................................................................... 4
`IV. Overview of the ’264 patent ........................................................................... 5
`A.
`The specification describes multi-temperature etch processes ............ 5
`B.
`The claims recite two-temperature etch processes and add only
`conventional features ............................................................................ 7
`The earliest priority date for the ’264 patent is September 1997 ......... 9
`C.
`V. Overview of the prior art .............................................................................. 10
`A. Kadomura (Ex. 1005) ......................................................................... 11
`B. Matsumura (Ex. 1003) ........................................................................ 12
`C.
`Kikuchi (Ex. 1004) ............................................................................. 16
`D. Muller (Ex. 1002) ............................................................................... 18
`E.
`Level of ordinary skill in the art ......................................................... 20
`VI. Claims 27-36, 51-55, 66, and 68-69 of the ’264 patent are
`unpatentable .................................................................................................. 21
`A. Ground 1: Claims 27, 29, 32, 34, 36, and 66 are obvious over
`Kadomura and Matsumura ................................................................. 21
`1.
`Claim 27 ................................................................................... 21
`2.
`Claim 29 ................................................................................... 36
`3.
`Claim 32 ................................................................................... 36
`4.
`Claim 34 ................................................................................... 37
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`-i-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`C.
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`B.
`
`5.
`Claim 36 ................................................................................... 38
`Claim 66 ................................................................................... 38
`6.
`Ground 2: Claims 31 and 35 are obvious over Kadomura,
`Matusmura, and Kikuchi .................................................................... 39
`1.
`Claim 27 ................................................................................... 39
`2.
`Claim 31 ................................................................................... 39
`3.
`Claim 35 ................................................................................... 42
`Ground 3 ............................................................................................. 42
`1.
`Claim 27 ................................................................................... 42
`2.
`Claim 28 ................................................................................... 42
`3.
`Claim 30 ................................................................................... 44
`4.
`Claim 33 ................................................................................... 47
`5.
`Claim 51 ................................................................................... 47
`6.
`Claim 52 ................................................................................... 53
`7.
`Claim 53 ................................................................................... 54
`8.
`Claim 54 ................................................................................... 55
`9.
`Claim 55 ................................................................................... 55
`10. Claim 68 ................................................................................... 58
`11. Claim 69 ................................................................................... 58
`D. Ground 4 ............................................................................................. 59
`1.
`Claim 27 ................................................................................... 59
`2.
`Claim 28 ................................................................................... 71
`3.
`Claim 31 ................................................................................... 72
`4.
`Claim 32 ................................................................................... 74
`5.
`Claim 33 ................................................................................... 74
`6.
`Claim 34 ................................................................................... 75
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`TABLE OF CONTENTS
`(continued)
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`Page
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`7.
`Claim 35 ................................................................................... 76
`Claim 36 ................................................................................... 76
`8.
`Claim 51 ................................................................................... 76
`9.
`10. Claim 52 ................................................................................... 80
`11. Claim 53 ................................................................................... 81
`12. Claim 54 ................................................................................... 82
`13. Claim 66 ................................................................................... 82
`14. Claim 68 ................................................................................... 83
`15. Claim 69 ................................................................................... 83
`Ground 5: Claims 29-30, 34, 55, and 68 are obvious over
`Kikuchi, Matsumura, and Muller ....................................................... 83
`1.
`Claim 27 ................................................................................... 83
`2.
`Claim 29 ................................................................................... 83
`3.
`Claim 30 ................................................................................... 85
`4.
`Claim 34 ................................................................................... 87
`5.
`Claim 51 ................................................................................... 89
`6.
`Claim 55 ................................................................................... 89
`7.
`Claim 68 ................................................................................... 91
`VII. Conclusion .................................................................................................... 91
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`E.
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`-iii-
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
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`EXHIBIT LIST AND TABLE OF ABBREVIATIONS AND CONVENTIONS
`
`Petitioner’s Exhibits
`
`Exhibit
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`Description
`
`Ex. 1001 U.S. Patent No. RE40,264 (“’264 patent”)
`
`Ex. 1002 U.S. Patent No. 5,605,600 (“Muller”)
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`Ex. 1003 U.S. Patent No. 5,151,871 (“Matsumura”)
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`Ex. 1004 U.S. Patent No. 5,226,056 (“Kikuchi”)
`
`Ex. 1005 U.S. Patent No. 6,063,710 (“Kadomura”)
`
`Ex. 1006 Declaration of Dr. John Bravman in Support of Petition for Inter
`Partes Review of U.S. Patent No. RE40,264
`
`Ex. 1007 U.S. Patent Application No. 08/567,224 (“’224 application”)
`
`Ex. 1008 Wright, D.R. et al., A Closed Loop Temperature Control System for
`a Low-Temperature Etch Chuck, Advanced Techniques for
`Integrated Processing II, Vol. 1803 (1992), pp. 321–329 (“Wright”)
`
`Ex. 1009 U.S. Patent No. 5,711,849 (“’849 patent”)
`
`Ex. 1010 U.S. Patent No. 4,331,485 (“Gat”)
`
`Ex. 1011 U.S. Patent No. 5,393,374 (“Sato”)
`
`Ex. 1012
`
`PTAB Decision Denying Institution of Inter Partes Review, Lam
`Research Corp. v. Daniel L. Flamm, IPR2016-00470, Paper 6 (July
`1, 2016)
`
`Ex. 1013
`
`PTAB Institution of Inter Partes Review, Lam Research Corp. v.
`Daniel L. Flamm, IPR2015-01768, Paper 7 (February 24, 2016)
`
`
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`-iii-
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
`
`EXHIBIT LIST AND TABLE OF ABBREVIATIONS AND CONVENTIONS
`(continued)
`
`Petition for Inter Partes Review of U.S. Patent No. RE40,264 E
`Fourth Petition, Lam Research Corp. v. Daniel L. Flamm, IPR2015-
`01768, Paper 1 (August 18, 2015)
`
`Ex. 1014
`
`Ex. 1015
`
`PTAB Decision Denying Institution of Inter Partes Review, Lam
`Research Corp. v. Daniel L. Flamm, IPR2016-00469, Paper 6 (July
`1, 2016)
`
`Ex. 1016
`
`PTAB Institution of Inter Partes Review, Lam Research Corp. v.
`Daniel L. Flamm, IPR2015-01764, Paper 7 (February 24, 2016)
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`Ex. 1017 U.S. Patent No. 5,446,824 (“Moslehi ’824”)
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`Ex. 1018 U.S. Patent No. 5,628,871 (“Shinagawa”)
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`Ex. 1019 U.S. Patent No. 5,174,856 (“Hwang”)
`
`Ex. 1020 Declaration of Rachel J. Watters regarding Exhibit 1008
`
`Other Abbreviations and Conventions
`Petitioners
`Intel Corporation, GLOBALFOUNDRIES U.S., Inc., and Micron
`Technology, Inc.
`Daniel Flamm
`
`Patent
`Owner
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`-iv-
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`
`
`I.
`
`Introduction
`
`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
`
`Dr. Daniel Flamm sued Petitioners Intel Corporation,
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`GLOBALFOUNDRIES U.S., Inc., and Micron Technology, Inc. for allegedly
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`infringing U.S. Patent No. RE40,264 E. Petitioners request the Board to institute
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`5
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`an IPR trial on claims 27-36, 51-55, 66, and 68-69 of the ’264 patent because prior
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`art that was not before the examiner during prosecution renders those claims
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`unpatentable.
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`The ’264 patent is titled “Multi-Temperature Processing.” The challenged
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`claims all require etching a substrate (such as a semiconductor wafer) at multiple
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`10
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`temperatures and with preselected processing times. Several references that were
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`not previously before the patent office show that multi-temperature etching and
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`predetermined process times were known long before the critical date. The various
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`claims also tack on conventional semiconductor tool components (temperature
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`sensors and control circuits), ordinary semiconductor temperature ranges (above
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`15
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`room temperature), but there was nothing unexpected or inventive about those
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`elements either. Each of the challenged claims is a combination of well-known
`
`elements arranged in a conventional way to produce predictable results. The
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`challenged claims are obvious.
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`20
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`II. Mandatory notices
`A. Real party in interest
`The real parties in interest are Intel Corporation, GLOBALFOUNDRIES,
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
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`Inc., GLOBALFOUNDRIES U.S., Inc., and Micron Technology, Inc.
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`B. Related matters
`Patent Owner has asserted the ’264 patent against Petitioners and others in
`
`lawsuits (now stayed) in the Northern District of California: Case Nos. 5:16-cv-
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`5
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`01578-BLF, 5:16-cv-1579-BLF, 5:16-cv-1580-BLF, 5:16-cv-1581-BLF, and 5:16-
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`cv-02252-BLF. In addition, Lam Research Corporation has filed a declaratory
`
`judgment action against Patent Owner on the ’264 patent (N.D. Cal. Case No.
`
`5:15-cv-01277-BLF) and IPR petitions on the ’264 patent (IPR2015-01759;
`
`IPR2015-01764; IPR2015-01766; IPR2015-01768; IPR2016-00468; IPR2016-
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`10
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`00469; and IPR2016-00470). Finally, Samsung Electronics, Co., Ltd. has filed
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`IPR petitions on the ’264 patent (IPR2016-01510 and IPR2016-01512).
`
`C. Notice of counsel and service information
`Petitioners’ respective counsel are:
`
`Lead Counsel
`
`Jonathan McFarland
`Reg. No. 61,109
`PERKINS COIE LLP
`1201 Third Avenue, Suite 4900
`Seattle, WA 98101
`206-359-8000 (phone)
`206-359-9000 (fax)
`Attorney for Intel Corporation
`
`
`Back-Up Counsel
`Chad Campbell
`Pro hac vice to be submitted
`Tyler Bowen
`Reg. No. 60,461
`PERKINS COIE LLP
`2901 N. Central Ave, Suite 2000
`Phoenix, AZ 85012
`602-351-8000 (phone)
`602-648-7000 (fax)
`Attorneys for Intel Corporation
`
`Daniel Keese
`Reg. No. 69,315
`
`
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`-2-
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
`
`PERKINS COIE LLP
`1120 NW Couch St., 10th Floor
`Portland, OR 97209
`503-727-2000 (phone)
`503-727-2222 (fax)
`Attorney for Intel Corporation
`
`Jeremy Jason Lang
`Registration No. 73,604
`WEIL, GOTSHAL & MANGES LLP
`201 Redwood Shores Parkway
`Redwood Shores, CA 94065
`650-802-3237 (phone)
`650-802-3100 (fax)
`Attorney for Micron Technology, Inc.
`
`Jared Bobrow
`Pro hac vice to be submitted
`WEIL, GOTSHAL & MANGES LLP
`201 Redwood Shores Parkway
`Redwood Shores, CA 94065
`650-802-3034 (phone)
`650-802-3100 (fax)
`Attorney for Micron Technology, Inc.
`
`David M. Tennant
`Registration No. 48,362
`WHITE & CASE LLP
`701 Thirteenth Street, NW
`Washington, DC 20005-3807
`202-626-3600 (phone)
`202-639-9355 (fax)
`Attorney for GLOBALFOUNDRIES
`U.S., Inc.
`
`Nathan Zhang
`Registration No. 71,401
`WHITE & CASE LLP
`3000 El Camino Real
`5 Palo Alto Square, 9th Floor
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`
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`-3-
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
`
`Palo Alto, CA 94306
`650-213-0300 (phone)
`650-213-8158 (fax)
`Attorney for GLOBALFOUNDRIES
`U.S., Inc.
`
`
`Petitioners consent to electronic service. All services and communications
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`to the above attorneys can be sent to: Intel-Flamm-Service-IPR@perkinscoie.com;
`
`micron.flamm.service@weil.com; and WCGlobalFoundries-
`
`FlammTeam@whitecase.com. A Power of Attorney for Petitioners will be filed
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`5
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`concurrently with this Petition.
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`III. Requirements for inter partes review
`A. Ground for standing
`The ’264 patent qualifies for IPR, and Petitioners are not barred.1
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`Identification of challenge
`
`B.
`Claims 27-36, 51-55, 66, and 68-69 should be cancelled as obvious based on:
`
`10
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`
`
` 1
`
` Patent Owner did not name Petitioners in an infringement complaint until January
`
`15, 2016, and the court did not issue summonses for purposes of service until
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`January 21, 2016. N.D. Cal. Case No. 5:15-cv-01277-BLF, Dkts. 50, 58, 60 & 61.
`
`Patent Owner did not serve any Petitioner with the complaint before January 21,
`
`2016.
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`
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
`
`Challenged Claims
`Claims 27, 29, 32, 34, 36,
`66
`Claims 31, 35
`
`Kikuchi, Matsumura, & Muller (Exs.
`1002-1004)
`
`Ground References
`1
`Kadomura & Matsumura (Exs. 1003 &
`1005)
`Kadomura, Matsumura, & Kikuchi (Exs.
`1003-1005)
`Claim 28, 30, 33, 51-55, 68,
`Kadomura, Matsumura, & Muller (Exs.
`69
`1002-1003 & 1005)
`Kikuchi & Matsumura (Exs. 1003-1004) Claims 27-28, 31-36, 51-54,
`66, 68-69
`Claims 29-30, 34, 55, 68
`
`2
`
`3
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`4
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`5
`
`Wright, Sato, Shinagawa, and other references illustrate the state of the art at
`
`the time of the alleged invention. Ariosa Diagnostics v. Verinata Health, Inc., 805
`
`F. 3d 1359, 1365 (Fed. Cir. 2015) (“Art can legitimately serve to document the
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`knowledge that skilled artisans would bring to bear in reading the prior art
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`5
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`identified as producing obviousness.”) (citation omitted). None of the above
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`references was before the patent office during the examination leading to the ’264
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`patent. Petitioners further rely on the Declaration of Dr. John Bravman (Ex. 1006)
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`and other supporting evidence in Petitioners’ exhibit list.
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`10
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`IV. Overview of the ’264 patent
`A. The specification describes multi-temperature etch processes
`The ’264 patent issued April 29, 2008 from a reissue application filed May
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`14, 2003. The sole inventor is Daniel L. Flamm. The patent discloses processing
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`(e.g., etching) a semiconductor wafer at two different temperatures in a single tool
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`chamber. (Ex. 1001, 2:10-12, 18:54-56.) Specifically, the patent describes
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
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`temperature control system 700, shown in Figure 7 below. (Id., 15:65-67.) That
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`system heats or cools wafer chuck 701 (purple), which holds a wafer during
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`processing. (Id., 16:3-5.) The control system measures wafer and chuck
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`temperatures, and a controller (not shown in Figure 7) increases or lowers set
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`5
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`temperatures to match desired levels using a heater (red) and fluid (blue) from
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`reservoir 713. (Id., 14:62-63,15:10-13, 16:3-19, 16:36-46, Fig. 6.) Temperature
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`control system 700 “us[es] conventional means” to change temperatures “to pre-
`
`determined temperatures within specific time intervals….” (Id., 16:60-67, 18:22-
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`26; Ex. 1006 ¶¶43-50.)
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`10
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`
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`Figure 10 below plots changes in temperature against processing time. (Ex.
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`1006 ¶¶51-52.)
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
`
`B.
`
`The claims recite two-temperature etch processes and add only
`conventional features
`
`Independent method claims 27 and 51 both recite placing a substrate (e.g.,
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`5
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`wafer) onto a substrate holder (e.g., chuck) and etching the substrate at two
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`different sequentially-selected temperatures in the same chamber. They also recite
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`sensors for measuring temperature and require controlling temperature changes
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`based on the measurements. Claim 27 specifically requires a “substrate holder
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`having at least one temperature sensing unit” and changing temperature based on
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`10
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`“a measured substrate temperature.” Claim 51 similarly requires temperature
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`control via a “substrate control circuit,” a “substrate holder temperature sensor,”
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`and a “substrate holder control circuit.” Both claims require changing temperature
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
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`within a “preselected” time. The claims differ in that claim 27 requires at least one
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`etching temperature to be “above room temperature,” while claim 51 requires at
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`least one etching step to occur “while heat is being transferred to the substrate
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`holder with the substrate holder control circuit.” (Ex. 1006 ¶¶26-28.)
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`5
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`The claims that depend from claim 27 (28-36, 66) and from claim 51 (52-55,
`
`68-69) recite, at-most, minor, conventional variations to the general process
`
`outlined above:
`
`• a “continuous etching process” (28);
`
`• heat transfer using an electrostatic chuck (29);
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`10
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`• heat transfer based on “a pressure of gas behind [the] substrate” (30);
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`• etching or temperature change based on “radiation” (31, 35);
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`• heat transfer “from a substrate temperature control system to the
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`substrate holder” (32);
`
`• “in-situ” temperature change (33);
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`15
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`• etching film portions with different “material composition[s]” (34, 68);
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`• etching based on “ion bombardment” (36),
`
`• etching at a first temperature “above room temperature” (66);
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`• etching with “heat flow from the substrate holder into the substrate”
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`(52) or “from the substrate into the substrate holder” (53);
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`20
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`• etching at 50ºC-100ºC (54);
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
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`• etching where the temperature change time “subtends less than about
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`5 percent of a total etching process time” (55); and
`
`• reaching a second temperature “at approximately a selected time” (69).
`
`C. The earliest priority date for the ’264 patent is September 1997
`For purposes of this Petition, September 11, 1997 is the earliest possible
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`5
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`priority date for the challenged claims. Although the ’264 patent also recites a
`
`priority claim to U.S. Patent Application No. 08/567,224, filed on December 4,
`
`1995 (Ex. 1007), that date is unsupportable because the ’224 application did not
`
`disclose the claimed subject matter.2
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`10
`
`For example, claim 27 requires changing the temperature of a substrate on a
`
`substrate holder from a “first” to a “second substrate temperature, using a
`
`measured substrate temperature, within a preselected time interval.” Yet, the ’224
`
`application failed to disclose changing temperature “within a preselected time
`
`interval,” much less using the same substrate holder. (Ex. 1006 ¶¶30-31.) Claim
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`15
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`27 also requires “using a measured substrate temperature” to change temperatures.
`
`
`
` 2
`
` In earlier IPRs, the Board found that September 11, 1997 is the earliest priority
`
`date to which the challenged claims are entitled. (Ex. 1012, 10-12; Ex. 1015, 10-
`
`12.) Although unimportant to this Petition, Petitioners do not concede that the
`
`claims are entitled to priority as of September 11, 1997.
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
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`The ’224 application disclosed a thermocouple to measure the temperature of the
`
`substrate holder, not the substrate. (Id. ¶¶32-33.)
`
`Similarly, claim 51 requires that a “substrate temperature control circuit
`
`effectuates the change from the first substrate temperature to the second substrate
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`5
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`temperature within a preselected time period.” Yet, the ’224 application did not
`
`disclose changing substrate temperature “within a preselected time period” or
`
`using a control circuit to effect the change. (Id. ¶¶30-33.)
`
`V. Overview of the prior art
`As Kadomura, Matsumura, Kikuchi, and Muller illustrate, multi-temperature
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`10
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`wafer processing in a chamber was well known in the prior art. Alone or in
`
`combination, those references disclosed the two-temperature etching processes
`
`recited in independent claims 27 and 51 and the minor variations in their
`
`dependents. (Id. ¶¶35-42.)
`
`In particular, the references disclosed controlling temperature changes (Ex.
`
`15
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`1002, Abstract; Ex. 1003, Abstract, 1:8-13; Ex. 1005, Title, Abstract) through
`
`heating (Ex. 1004, 7:24-33; Ex. 1005, 11:42-47) and cooling (Ex. 1002, 4:51-5:25;
`
`Ex. 1003, 6:19-31; Ex. 1005, 11:42-59), and rapid temperature changes to
`
`minimize potential processing delays (Ex. 1002, 5:17-25, 6:66-7:8; Ex. 1003, 7:50-
`
`53, Figs. 8-9; Ex. 1004, Abstract, 7:62-8:14; Ex. 1005, 5:18-26). The references
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`20
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`disclosed etching tools with sensors and controllers to measure temperatures and
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
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`regulate temperature changes. (Ex. 1003, 6:19-31; Ex. 1005, 12:37-48; Ex. 1008,
`
`321.) The references also disclosed using processing recipes to pre-program
`
`control systems to process wafers at particular times or temperatures and to change
`
`temperatures within preselected times. (Ex. 1003, 3:1-16, 5:58-6:2, 7:19-32, 8:25-
`
`5
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`35, 8:56-68, Figs. 8-9; Ex. 1006 ¶¶71-73.)
`
`A. Kadomura (Ex. 1005)
`Kadomura was filed in February 1997. Like the ’264 patent, Kadomura
`
`disclosed a multi-temperature process for etching portions of a semiconductor
`
`wafer. (Ex. 1006 ¶¶58-67.) As in annotated Figure 4 below, Kadomura disclosed
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`10
`
`an etching tool with a heater (not explicitly shown but represented in red) in wafer
`
`holder stage 12 (purple), a chiller 17 (blue) for cooling stage 12, a thermometer 18
`
`(yellow) for measuring wafer temperature, and a control device 25 (orange) for
`
`controlling the temperature of wafer W (green) based on temperature
`
`measurements from thermometer 18. (Ex. 1005, 11:36-59, 12:37-48.) Kadomura
`
`15
`
`adjusted the wafer’s temperature by changing the temperature of stage 12. (Id.,
`
`3:23-49.)
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`Petition for Inter Partes Review of '264 Patent (IPR2017-00280)
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`
`
`Kadomura also disclosed several specific examples of multi-temperature
`
`etch processes, including etching wafers at and above room temperature (20ºC,
`
`50ºC) and changing etching temperature within about 30 or 50 seconds. (Id., 6:18-
`
`5
`
`7:7, 7:58-8:64, 9:33-10:27.)
`
`B. Matsumura (Ex. 1003)
`Matsumura issued in September 1992. Like Kadomura, Matsumura
`
`disclosed multi-temperature wafer processing in a chamber. In addition,
`
`Matsumura disclosed the well-known practice of using recipes to preselect process
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`10
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`parameters such as processing temperatures and temperature change times.
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`Matsumura also disclosed the use of a substrate holder temperature sensor with
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`processing recipes. (Ex. 1006 ¶¶69-74.)
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`As in annotated Figure 5A, Matsumura taught a processing tool with a
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`thermometer 24 and sensor 25 (yellow) for measuring the temperature of wafer
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`holding stage 12; control system 20 (orange) for managing temperature changes;
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`conductive thin film 14 (red) in the wafer holder stage 12 (purple) to heat wafer W
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`(green); and cooling system 23 (blue) for cooling the wafer. (Ex. 1003, 5:60-63,
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`5:68-6:2, 8:18-35.)
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`Substrate temperature sensors, like Matsumura’s, were well known in the
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`prior art. Wright, a paper published in 1992, disclosed a processing tool that used
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`two separate sensors to measure the temperature of the wafer and the wafer holder.
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`(Ex. 1008, 321 (“The system employs an optical fluorescence probe on the chuck
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`(a second probe monitors the wafer temperature as well)….”); see also Ex. 1004,
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`2:1-3.) Wright’s Figure 6 below shows sensor measurements for the wafer and the
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`chuck over time.
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`Likewise, using recipes to preselect temperature changes and other
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`processing conditions was well known in semiconductor manufacturing. (Ex. 1006
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`¶71.) Matsumura’s control system 20 followed “predetermined recipe[s]” that
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`specified temperatures, processing times, and temperature change times. (Ex. 1003,
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`3:1-7 (“storing, as a predetermined recipe, information showing a time-
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`temperature relationship and applicable for either heating the object to a
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`predetermined temperature for a predetermined period of time or cooling the object
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`from a predetermined temperature over a predetermined period of time, or for
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`both….) (emphasis added), 3:14-16 (“controlling either the heating of the object or
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`the cooling thereof, or both, in accordance with the detected temperature and the
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`information”).) Matsumura’s Figure 9 below charts a sample recipe with multiple
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`preselected processing temperatures (y-axis) and temperature change times (x-axis).
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`Matsumura expressly taught that its recipe-based temperature control techniques
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`could be used in etching processes. (Id., 10:3-7.)
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`C. Kikuchi (Ex. 1004)
`Kikuchi (issued July 1993) also disclosed multi-temperature etching within
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`the same chamber. (Ex. 1006 ¶¶82-87.) Kikuchi described ashing3 a wafer’s
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`photoresist film at two sequential temperatures using either heat lamps or a hot
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`plate to raise temperature, in addition to measuring wafer and hot plate
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`temperatures, respectively, using different thermometers. (Ex. 1004, 1:56-2:3,
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`7:20-34, 7:62-68, 8:8-14, 11:6-9, Figs. 12-13.) Embodiments from Figures 1, 11,
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`and 19 are shown below. The annotations indicate lamps 5 (red), hot plate 7
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`(purple) with heater 6 (red), wafer 1 (green), and thermometers 10 and 66 (yellow).
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` Ashing is a type of etching that uses a plasma, typically at high temperatures, to
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`remove a photoresist film. (Ex. 1006 ¶83.) Flamm’s ’849 patent described “resist
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`stripp[ing]” as etching and dependent claims 7 and 16 recited “ashing” as a subset
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`of “etching.” (Ex. 1009, 1:7-9.)
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`Kikuchi etched photoresist over a range of temperatures, with an initial step
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`at 70ºC-160ºC and a rapid increase to 200ºC from 5seconds (lamps) or 10 seconds
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`(hot plate). Figures 12 and 13 below show exemplary etching temperature changes
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`disclosed in Kikuchi.
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`D. Muller (Ex. 1002)
`Likewise, Muller (issued February 1997) disclosed etching a wafer at two
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`sequential temperatures in a chamber. (Ex. 1006 ¶¶100-104.) Muller disclosed
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`etching surface layers on a wafer and deep trenches into the wafer itself while
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`varying wafer temperature using an electrostatic chuck and coolant circulating
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`through a cathode. (Ex. 1002, 1:7-12, 1:44-55, 4:51-63.) Figure 4 below is
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`annotated to highlight the wafer 104 (green), electrostatic chuck 105 (purple), and
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`cathode 106 (blue).
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`Muller taught performing an initial etch at 125ºC or 145ºC. (Id., 3:45-52,
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`3:56-66.) Then, the gas pressure underneath the chuck was changed to increase
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`wafer temperature by 50ºC in “several seconds” during etching. (Id., 4:64-5:25,
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`5:41-48.) Due to the 50ºC increase, Muller’s second etching step was performed at
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`175ºC (e.g., 125ºC plus 50ºC) or 195ºC (e.g., 145ºC plus 50ºC). (Id., 5:17-25,
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`5:41-48; Ex. 1006 ¶103.) The two etching temperature examples corresponded to
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`two different coolant temperatures––(a) with coolant at 10ºC, etch steps 1 and 2
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`were at 125ºC (step 1) and 175ºC (step 2), respectively; and (b) with coolant at
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`30ºC, etch steps 1 and 2 were at 145ºC (step 1) and 195ºC (step 2), respectively.
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`(Id.) Figure 3 below shows the different step 1 etching temperatures achieved for
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`coolant at 10ºC versus 30ºC.
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`Level of ordinary skill in the art
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`E.
`A person of ordinary skill in the art at the time of the alleged invention of
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`the ’264 patent (“skilled person”) would have had (i) a Bachelor’s degree in
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`chemical engineering, materials science engineering, electrical engineering,
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`physics, chemistry, or a similar field, and three or four years of work experience in
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`semiconductor manufacturing or related fields; or (ii) a Master’s degree in
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`chemical engineering, materials science engineering, electrical engineering,
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`physics, chemistry, or a similar field, and two or three years of work experience in
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`semiconductor manufacturing or related fields; or (iii) a Ph.D. in chemical
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`engineering, materials science engineering, electrical engineering, physics,
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`chemistry, or a similar field. (Ex. 1006 ¶¶20-22.)
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`VI. Claims 27-36, 51-55, 66, and 68-69 of the ’264 patent are unpatentable
`This Petition uses primary references (1) Kadomura, (2) Matsumura, and
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`(3) Kikuchi, along with secondary reference (4) Muller, to form distinct
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`unpatentability grounds for claims 27-36, 51-55, 66, and 68-69.
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`A. Ground 1: Claims 27, 29, 32, 34, 36, and 66 are obvious over
`Kadomura and Matsumura
`1.
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`Claim 27
`a.
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`Preamble: “A method of etching a substrate in the
`manufacture of a device, the method comprising”
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`Kadomura described etching a substrate (wafer) to make semiconductor
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`devices. (Ex. 1005, 1:6-11, 11:36-42.)
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`b.
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`27[a]: “heating a substrate holder to a first substrate
`holder temperature with a heat transfer device, the
`substrate holder having at least one temperature
`sensing unit”
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`Kadomura taught raising a wafer’s temperature by heating the substrate
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`holder (stage 12) to a desired temperature. (Id., 3:19-65.) In one example, a
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`20
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`wafer’s silicide layer and part of a polysilicon layer were etched at 20ºC. (Id.,
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`6:18-29.) Then the remaining part of the polysilicon layer was etched at -30ºC.
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`(Id., 6:63-7:7.) After completing those two steps, a heater within substrate holder
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`stage 12 brought the holder back up to 20ºC before the tool repeated the same two-
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`temperature etch process. (Id., 6:63-7:7, 7:31-47.)
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`Kadomura included