US005446824A
`
`[11]
`
`[45]
`
`Patent Number:
`
`5,446,824
`
`Date of Patent:
`
`Aug. 29, 1995
`
`63-58926
`3/1988
`63-160222
`7/1988
`64-5014
`1/1989
`3-20464
`1/1991
`3- 159224
`7/1991
`3-256323 11/1991
`4—I7667
`1/1992
`
`Japan .
`Japan .
`Japan ................................... 392/418
`Japan
`
`Japan .
`Japan .
`Japan .
`
`Primary Examiner—John A. Jeffery
`Attorney, Agent, or Firm—Gary Honeycutt; Renie’
`Grossman; Richard Donaldson
`
`[57]
`
`ABSTRACI‘
`
`A chuck (82) for lamp-heated thermal and plasma semi-
`conductor wafer (38) processing comprises an absorb-
`ing surface (171) for absorbing optical energy from an
`illuminator module (84) that transforms the electrical
`energy into radiant optical energy. Chuck (82) includes
`an absorbing surface (171) that absorbs optical energy
`and distributes the resultant thermal energy. From the
`absorbing surface, a contact surface (168) conducts the
`heat energy to semiconductor wafer (38) and uniformly
`heats the semiconductor wafer (38) with the distributed
`thermal energy. Chuck (82) not only provides signifi-
`cantly improved process temperature uniformity, but
`also allows for the generation of RF plasma for plasma-
`enhanced fabrication processes as well as for in-situ
`chamber cleaning and etching. Additionally, chuck (82)
`provides at least two methods of determining semicon-
`ductor wafer temperature; a direct reading thermo-
`couple (112) and association with the pyrometry sensor
`of illuminator module (84). Other features of chuck (82)
`are that it is thermally decoupled from the thermal mass
`of fabrication reactor (50) and establishes an environ-
`ment for [purging optical quartz window (80) surface
`and semiconductor wafer (38) backside in order to pre-
`vent deposition on wafer backside and the quartz win-
`dow.
`
`5 Claims, 8 Drawing Sheets
`
`United States Patent
`
`[19]
`
`Moslehi
`
`[54] LAMP-HEATED CHUCK FOR UNIFORM
`WAFER PROCESSING
`
`[75]
`
`Inventor: Mehrdad M. Moslehi, Dallas, Tex.
`
`[73] Assignee: Texas Instruments, Dallas, Tex.
`
`[21] Appl. No.: 63,110
`
`[22] Filed:
`
`May 17, 1993
`
`Related U.S. Application Data
`
`[63]
`
`Continuation of Ser. No. 774,677, Oct. 11, 1991, aban-
`doned.
`
`[51]
`
`Int. Cl.6 '................... .. H05B 3/00; H01L 21/027;
`F27D 11/00
`[52] U.S. Cl. .................................. .. 392/416; 118/724;
`118/50.1
`[58] Field of Search .............................. .. 392/416-418;
`219/405, 411, 390; 118/724, 725, 728, 730, 50.1;
`250/492.1; 427/55, 50, 51, 585, 586, 592, 557,
`569
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`9/1974 Anderson ............................ 219/405
`3,836,751
`4,499,354 2/1985 Hill et al.
`........ .. .
`.. ... 118/725
`4,599,069 7/1986 Murakami et al.
`.
`118/725
`4,640,224 2/1987 Bunch et al
`...... .. ...
`..... 118/725
`4,682,566 7/1987 Aitken .....
`... .. 118/724
`4,709,655 12/1987 Van Mastrig
`118/725
`4,796,562
`1/1989 Brors et al
`. ....
`. .... 118/725
`4,891,335
`1/1990 McNei1ly
`219/530
`5,073,698 12/1991 Stultz ... .. .
`.. ... 219/405
`5,119,761
`6/1992 Nakata .... .. ..
`..... 118/725
`5,156,461 10/1992 Moslehi et al
`374/121
`5,255,286 10/1993 Moslehi et al
`374/121
`5,293,216 3/1994 Moslehi ... .. . .
`. .. .. 356/371
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`60-189924 9/1985 Japan ................................... 118/724
`60-189927 9/1985 Japan ................................. .. 118/730
`
` ..
`
`
`
`
`
`
`
`/55’_ /
`...._,\\\\\\\\\\‘
`45%.:
`
`"%j‘3\\T\\\‘\‘
`
`Intel Corp. et al.
`
`Exhibit 1 017
`
`Intel Corp. et al. Exhibit 1017
`
`

`
`U.S. Patent
`
`Aug. 29, 1995
`
`Sheet 1 of 8
`
`5,446,824
`
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`
`Intel Corp. et al. Exhibit 1017
`
`Intel Corp. et al. Exhibit 1017
`
`

`
`U.S. Patent
`
`Aug. 29, 1995
`
`Sheet 2 of 8
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`5,446,824
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`Intel Corp. et al. Exhibit 1017
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`Intel Corp. et al. Exhibit 1017
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`
`

`
`U.S. Patent
`
`Aug. 29, 1995
`
`Sheet 3 of 8
`
`5,446,824
`
`Intel Corp. et al. Exhibit 1017
`
`Intel Corp. et al. Exhibit 1017
`
`

`
`U.S. Patent
`
`Aug. 29, 1995
`
`Sheet 4 of 8
`
`5,446,824
`
`\\\.
`
`FIG. 5
`
`Intel Corp. et al. Exhibit 1017
`
`Intel Corp. et al. Exhibit 1017
`
`
`

`
`U.S. Patent
`
`Aug. 29, 1995
`
`Sheet 5 of 3
`
`5,446,824
`
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`

`
`U.S. Patent
`
`Aug. 29, 1995
`
`Sheet 6 of 8
`
`5,446,824
`
`171
`
`FIG. 9
`
`Intel Corp. et al. Exhibit 1017
`
`Intel Corp. et al. Exhibit 1017
`
`

`
`U.S. Patent
`
`Aug. 29, 1995
`
`Sheet 7 of 8
`
`5,446,824
`
`Intel Corp. et al. Exhibit 1017
`
`Intel Corp. et al. Exhibit 1017
`
`

`
`U.S. Patent
`
`Aug. 29, 1995
`
`Sheet 8 of 8
`
`5,446,824
`
`FIG. 10
`
`Intel Corp. et al. Exhibit 1017
`
`Intel Corp. et al. Exhibit 1017
`
`

`
`1
`
`5,446,824
`
`LAMP-HEATED CHUCK FOR UNIFORM WAFER
`PROCESSING
`
`This application is a continuation of application Ser.
`No. 07/774,677, filed Oct. 11, 1991, now abandoned.
`
`TECHNICAL FIELD OF THE INVENTION
`
`The present invention relates to microelectronic de-
`vice processing and more particularly to a lamp-heated
`chuck with the ability to provide radio—frequency (RF)
`plasma enhancement for uniform semiconductor wafer
`processing that is useful in a wide range of single-wafer
`lamp-heated and RF plasma device processing applica-
`tions.
`
`5
`
`10
`
`15
`
`BACKGROUND OF THE INVENTION
`
`20
`
`25
`
`30
`
`35
`
`Single-wafer rapid thermal processing (RTP) is a
`versatile technique for fabrication of very-large-scale
`integrated (VLSI) and ultra-large-scale integrated
`(ULSI) circuits. Single-wafer RTP combines low ther-
`mal mass, photon-assisted, rapid wafer heating with
`reactive ambient semiconductor device processing.
`Both the wafer temperature and the process environ-
`ment can be quickly controlled and, as a result, it is
`possible to optimize each fabrication step to improve
`the overall electrical performance of the circuits.
`RTP is one form of single-wafer semiconductor
`wafer processing that can provide improved wafer-to-
`wafer process
`repeatability in single-wafer,
`lamp-
`heated, thermal processing reactors. Numerous semi-
`conductor fabrication technologies may use RTP tech-
`niques, including thermal oxidation, nitridation, implant
`activation, dopant diffusion, and different types of ther-
`mal anneals. Chemical-vapor deposition (CVD) is an-
`other type of device fabrication process that can benefit
`from RTP in single-wafer reactors. For example, CVD
`processes using advanced RTP techniques to form di-
`electrics (e.g., oxides and nitrides), semiconductors
`(e.g., amorphous silicon and polysilicon), and conduc-
`tors (e.g., aluminum, copper,
`tungsten, and titanium
`nitride) have significant potentials in VLSI and ULSI
`device fabrication.
`FIG. 1 illustrates a known RTP system 20 for semi-
`conductor wafer processing. The system 20 of FIG. 1
`uses two banks 22 and 24 of lamps 26 which are ar-
`ranged in orthagonal or cross directions. The lamps are
`placed outside the reactor chamber’s quartz windows
`30. Reflectors 32 and 34 are placed behind lamp banks
`22 and 24, respectively. Quartz susceptor 36 holds semi-
`conductor wafer 38, and semiconductor wafer 38 front
`and back surfaces face lamp banks 22 and 24. Relative
`power to each lamp 26 may be set and overall power
`may be controlled to maintain desired temperature by
`computer lamp controller 40. Computer lamp control-
`ler 40 receives temperature signal input from pyrometer
`42. Rotary pump 44 vacuum manifold and gas manifold
`46 maintain process chamber environment 28 for vari-
`ous processes.
`The conventional type of RTP system such as that of 60
`FIG. 1, may provide generally uniform wafer heating
`during some steady-state conditions. However,
`the
`known RTP systems cannot provide uniform wafer
`heating over a wide range of temperatures and during
`both the transient and steady-state conditions. The re-
`sultant wafer temperature nonuniformities can result in
`process nonuniformities and possibly slip dislocations.
`In fact, the most critical problems with commercial
`
`40
`
`45
`
`50
`
`55
`
`65
`
`2
`RTP systems are process nonuniformities caused by the
`steady-state and transient temperature nonuniformities.
`Some existing tungsten—halogen lamp-heated RTP
`systems such as that of the FIG. 1, employ two crossed
`banks of linear tungsten-halogen lamps. While this con-
`figuration may provide a limited capability for steady-
`state temperature uniformity control, it does not pro-
`vide complete uniformity adjustment and does not pro-
`vide cylindrical symmetry consistent with the circular
`shape of semiconductor wafer 38. Moreover, the design
`of FIG. 1 provides no reliable and accurate measure of
`wafer 38 temperature. In addition, this type of RTP
`system does not provide any RF plasma capability for
`in-situ plasma processing applications.
`The RTP temperature control and process nonuni-
`formity problems are particularly manifested in the
`form of localized wafer edge cooling due to excessive
`heat losses by radiation and gas cooling. FIG. 2 shows
`a qualitative plot of wafer temperature versus radial
`position that demonstrates the edge problem. In FIG. 2,
`the vertical axis represents wafer temperature and the
`horizontal axis has an origin at the center C and range in
`equal directions between —R and +R at the edge
`points of semiconductor wafer 38. According to FIG. 2,
`at the center C, semiconductor wafer 38 may achieve a
`temperature Tc. Throughout a significant portion of the
`radial distance from C to the edge of semiconductor
`wafer 38, the temperature can be made approximately
`equal to Tc. Close to the edge, however, the tempera-
`ture usually drops. The are labeled “edge cooling”
`indicates that at the —R and +R edge points on semi-
`conductor wafer 38, semiconductor wafer 38 tempera-
`ture falls to the edge cooled level of Te. The amount of
`center-to-edge temperature variation may be a few de-
`grees up to 10’s of degrees C.
`The extent of the temperature nonuniformity prob-
`lem depends on the target wafer temperature and the
`RTP system design as well as process parameters such
`as chamber pressure. For a given RTP lamp, the wafer
`temperature nonuniformity may also depend on the
`details of the thermal cycle. The transient thermal nonu-
`niformity is, in general, different from the steady-state
`temperature nonuniformity. If the lamp module for
`heating semiconductor wafer employs a single high-
`power arc lamp, there is basically no flexibility for real-
`time control or optimization of wafer temperature uni-
`formity by changing or adjusting the optical flux distri-
`bution on the wafer. In commercial RTP systems with
`tungsten—halogen lamps such as that in FIG. 1, there is
`no practical way to adjustably control the transient and
`steady-state temperature uniformity profiles over the
`entire wafer area. High-temperature RTP techniques
`particularly exacerbate this problem. For example, in
`some applications fabrication temperatures may reach
`as high as 1100“ C. and good wafer temperature unifor-
`mity is required in order to avoid slip dislocations and
`process nonuniformities.
`Another semiconductor device fabrication technique
`that has many applications is known as “plasma-
`enhanced processing.” In plasma-enhanced processing,
`a substantially ionized gas, usually produced by a radio-
`frequency (RF) or microwave electromagnetic gas dis-
`charge, generates a mixture of ions, electrons, and ex-
`cited neutral species, which may react to deposit or etch
`various material layers on semiconductor substrates in a
`wafer processing reactor. Plasma-enhanced chemical-
`vapor deposition (PECVD) is an example of a widely-
`used plasma-enhanced semiconductor device fabrica-
`
`Intel Corp. et al. Exhibit 1 017
`
`Intel Corp. et al. Exhibit 1017
`
`

`
`3
`tion process. PECVD uses the activated neutrals and
`ions in the plasma to deposit material layers at high rates
`and lower temperatures on a semiconductor substrate.
`Various PECVD applications for plasma-enhanced
`processing and semiconductor device manufacturing
`include deposition of amorphous silicon, polysilicon,
`tungsten, aluminum, and dielectric layers. Plasma-
`enhanced metal-organic chemical-vapor deposition pro-
`cesses (PEMOCVD) also are useful for high-rate depo-
`sition of material layers such as aluminum and copper
`films for device interconnection applications. Plasma-
`enhanced deposition techniques can also be used for
`planarized interlevel dielectric formation. Additional
`applications of PECVD techniques include low-tem-
`perature epitaxial silicon growth as well as diamond
`thin films.
`
`If it were possible to concurrently and/or sequen-
`tially perform plasma—enhanced processing together
`with lamp-heated processing (RTP) in the same cham-
`ber without having to reconfigure the fabrication reac-
`tor, numerous semiconductor device fabrication pro-
`cesses could be materially enhanced. For example, such
`a system would provide for rapid thermal chemical-
`vapor deposition (RTCVD) of various material layers
`with in-situ process chamber cleaning. There is no
`known RTP system that accomplishes these objectives
`in a flexible manner.
`As a result of the above, there is a need for a method
`and apparatus to provide both steady-state and transient
`semiconductor device fabrication process uniformity
`for rapid thermal processing (RTP) applications.
`There is a need for a device that permits accurate
`real-time measurement of temperature across the entire
`semiconductor wafer.
`
`There is a need for a method and apparatus that al-
`lows semiconductor device fabrication process control
`flexibility based on the particular application as well as
`real-time temperature readings of the semiconductor
`wafer temperature and its uniformity.
`Moreover, there is a need for a semiconductor device
`fabrication apparatus that permits flexible and uniform
`wafer processing for various thermal processing appli-
`cations.
`
`There is yet the need for an apparatus for plasma
`generation within the semiconductor wafer processing
`chamber that is both reliable and controllable.
`There is the further need for a method and apparatus
`to support coordinated plasma generation for plasmaen-
`hanced semiconductor device fabrication processes and
`lamp-heated rapid thermal processes.
`SUMMARY OF THE INVENTION
`
`Accordingly, the present invention provides a lamp-
`heated radio-frequency (RF) plasma chuck for uniform
`semiconductor device processing which overcomes the
`problems and satisfies the needs previously considered.
`According to one aspect of the present invention,
`there is provided a chuck for lamp-heated and (RF)
`plasma—enhanced semiconductor wafer processing that
`comprises an absorbing surface for absorbing optical
`energy from a heating lamp via an optically transparent
`window and transforming the optical energy into radi-
`ant heat energy. The main body of the radio-frequency
`chuck associates with the absorbing surface and distrib-
`utes the radiant heat energy and conducts the thermal
`energy toward the semiconductor wafer. A contact
`surface of the chuck associates with the main body of
`the chuck and transfers the distributed radiant heat
`
`5
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`20
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`30
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`35
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`40
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`45
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`50
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`55
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`65
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`5,446,824
`
`4
`energy across the entire semiconductor wafer surface.
`In the preferred embodiment, the new chuck design
`provides a circular thin silicon carbide or a silicon-car-
`bide-coated graphite (other materials such as silicon
`may also be used) disk for absorbing the optical energy
`from a multi-zone heat lamp via an optically transparent
`window made of quartz, sapphire, or another material.
`The silicon carbide or graphite disk transforms the opti-
`cal energy from the multi-zone heating lamp into radi-
`ant heat energy and conducts the radiant heat energy to
`a circular and somewhat thicker (higher thermal mass)
`metallic disk or main chuck body that significantly
`distributes the radiant heat energy within its volume.
`The base or main body of the chuck has a surface which
`contacts the semiconductor wafer and distributes the
`radiant heat energy to the semiconductor wafer. As a
`result,
`the chuck of the present invention uniformly
`heats the semiconductor wafer from its backside and
`avoids the edge nonuniforrnity or cooling problem typi-
`cal of known RTP-based semiconductor device fabrica-
`tion equipment.
`A technical advantage of the present invention is that
`it is designed to be compatible with the high-perfor-
`mance multi-zone heat lamp for semiconductor wafer
`processing of U.S. patent
`application, Ser. No.
`07/690,426 (filed on Apr. 24, 1991) by Moslehi, et. al.
`and assigned to Texas Instruments Incorporated now
`abandoned. The device of that invention provides much
`improved steady-state and transient semiconductor de-
`vice fabrication uniformity and facilitates the use of
`advanced multi-point pyrometry techniques for semi-
`conductor wafer temperature measurement. Moreover,
`the high-performance multi-zone heating lamp provides
`significantly increased semiconductor fabrication pro-
`cess uniformity control
`flexibility. For lamp-heated
`semiconductor device processing, the chuck of the pres-
`ent invention combines with the multi-zone heat lamp
`to further enhance both steady-state and transient tem-
`perature and process uniformity.
`Another technical advantage of the present invention
`is that it provides a way to perform more accurate and
`convenient pyrometry-based semiconductor wafer tem-
`perature measurements by measuring the temperature
`of the surface that absorbs the optical energy from the
`lamp. As a result, the temperature of the absorbing
`surface (with a known constant emissivity) may be mea-
`sured and controlled during a semiconductor device
`fabrication process. A direct relationship exists between
`the temperature of the semiconductor wafer and the
`temperature of the absorbing surface during wafer pro-
`cessing. With a known absorbing surface emissivity for
`a particular temperature range and a known tempera-
`ture offset relationship between the optical energy ab-
`sorbing surface (e.g., the silicon carbide or graphite disk
`in the preferred embodiment) and the wafer, it is possi-
`ble to accurately measure and control the temperature
`of the semiconductor wafer.
`
`Another technical advantage of the present invention
`is that it provides increased process control flexibility
`over known systems. For example, not only is the chuck
`of the present invention fully compatible with the multi-
`zone illuminator of U.S. patent application Ser. No.
`07/690,426, now abandoned but also the present inven-
`tion has further flexibility features. The chuck of the
`present invention is designed to be thermally decoupled
`from the thermal mass of the semiconductor device
`fabrication reactor including the optical/vacuum quartz
`window. This permits more rapid and more uniform
`
`Intel Corp. et al. Exhibit 1 017
`
`Intel Corp. et al. Exhibit 1017
`
`

`
`5,446,824
`
`6
`FIG. 10 is a schematic cross-sectional view of an
`alternative embodiment of the base of the chuck.
`
`5
`temperature response for various RTP techniques.
`Moreover, thermal isolation of the chuck from the op-
`tical/vacuum quartz window eliminates possible degra-
`dation of the vacuum O-ring seals. Additionally, the
`present invention has an embedded thermocouple for
`direct wafer temperature measurement that may be
`used to calibrate the pyrometry measurement devices or
`to separately sense the temperature of the semiconduc-
`tor wafer for real-time temperature and process control.
`Furthermore, the chuck of the present invention may be
`designed for fabrication reactors that process either 150
`millimeter or 200 millimeter and even larger semicon-
`ductor wafers. The radial symmetry of the chuck of the
`present invention facilitates scaling in size with uniform
`temperature distribution.
`Another technical advantage of the present invention
`is that it may be manufactured of high-temperature
`refractory metals or their alloys which may be used at
`increased processing temperatures. For example, in the
`preferred embodiment, applications may be as high as
`1l00° C. Moreover, the preferred embodiment includes
`a melted (liquid metal) tin chamber that further pro-
`motes a uniform distribution of the wafer temperature.
`In high-temperature processing applications, the chuck
`of the present invention has the ability to rapidly distrib-
`ute the radiant heat energy for uniform wafer heating.
`This feature of the chuck also ensures uniform process-
`ing at lower temperatures.
`Yet another important technical advantage of the
`present invention is that it permits the combination of 30
`lamp-heated semiconductor wafer processing with RF
`plasma generation. The chuck of the present invention
`includes an RF source contact which translates radio-
`frequency excitation signals from an external electrical
`source to the processing environment of the semicon-
`ductor wafer. No known device provides the combina-
`tion of RF generation for plasma enhancement and
`improved thermal uniformity as provided in the present
`invention via multi-zone lamp heating.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The preferred embodiment of the present invention is
`best understood by referring to the FIGURES wherein
`like numbers are used for like and corresponding parts
`of the various documents.
`FIG. 3 is a schematic representation and FIG. 4 is an
`isometric partially cut-away view of a single-wafer
`semiconductor fabrication reactor 50 that establishes
`the environment of the present invention. Referring to
`FIG. 3, within a single-wafer rapid thermal processing
`(RTP) reactor 50 such as the Texas Instruments Auto-
`mated Vacuum Processor (AVP), may reside semicon-
`ductor wafer 38. Beginning at the bottom right hand
`comer of FIG. 3, gas distribution network 52 may com-
`prise two gas manifolds: a non-plasma process gas mani-
`fold and a plasma manifold. The non-plasma gas mani-
`fold feeds through gas line 54 into reactor casing 56 and
`process chamber wall 58 to ground electrode 60 and
`into gas injector 62. The plasma manifold connects
`through plasma line 64 through connection 66 and into
`microwave discharge cavity 68. Plasma from micro-
`wave discharge cavity 68 feeds through plasma tube 70
`which also penetrates reactor casing 56 and process
`chamber wall 58. Within the process chamber 72 plasma
`tube 70 passes through ground electrode 60 and through
`gas injector 62 to plasma output 74. Above quartz
`jacket assembly 76 and supported by low thermal mass
`pins 78 appears semiconductor wafer 38. Low thermal
`mass pins 78 are clamped against chuck assembly 82 by
`ground electrode 60 (or a liner, not shown) within pro-
`cess chamber 72.
`-
`
`Process chamber 72 includes optical quartz window
`80 through which penetrates the chuck assembly 82 of
`the present invention. Chuck assembly 82 holds firmly
`semiconductor wafer 38 for direct thermal contact and
`heat distribution across semiconductor wafer 38. RF
`chuck assembly 82 connects to tungsten-halogen heat-
`ing lamp module 84 and receives direct optical energy
`from module 84 through quartz window 80. In associa-
`tion with tungsten-halogen heating lamp module 84
`may be a multi-point temperature sensor (not shown) as
`described in U.S. patent application Ser. No. 702,646 by
`Moslehi, et al. filed on May 17, 1991 and assigned to
`Texas Instruments Incorporated now issued as U.S. Pat.
`Nos. 5,156,461 and U.S. 5,255,286. Vacuum pump con-
`nection 86 removes flowing process gas and plasma
`from process chamber 72 and directs them into pump-
`ing package 88. Additionally, isolation gate 90 permits
`passage of semiconductor wafer 38 from vacuum load-
`lock chamber 92 into process chamber 72. To permit
`movement of semiconductor wafer 38 into process
`chamber 72, a vertically moveable bellows 94 supports
`process chamber wall 58.
`Within vacuum load—lock chamber 92 appears cas-
`sette 96 of semiconductor wafers 38 from which wafer
`handling robot 98 removes a single semiconductor
`wafer 38 for processing. To maintain load-lock chamber
`92 under vacuum, load-lock chamber 92 also includes
`vacuum pump connection 100 to pumping package 88.
`Additionally, scatter module 102 may be included in
`load-lock chamber 92 for determining the surface
`roughness and reflectance of semiconductor wafer 38
`for wafer processing measurements according to U.S.
`
`Intel Corp. et al. Exhibit 1 017
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`The invention and its modes of use and advantages
`are best understood by reference to the following de-
`scription of illustrative embodiments when read in con-
`junction with the accompanying drawings, wherein:
`FIG. 1 is a side schematic view of a tungsten-halogen
`lamp RTP system typical of the prior art;
`FIG. 2 illustrates the wafer temperature nonuniform-
`ity problem that the present invention solves;
`FIG. 3 is a schematic cut-away side view of a typical
`environment of the preferred embodiment;
`FIG. 4 is a partially cut-away isometric view of a
`single-wafer rapid thermal processing reactor for estab-
`lishing the environment of the preferred embodiment;
`FIG. 5 is a perspective view of a multi-zone illumina-
`tor module incorporating the preferred embodiment;
`FIGS. 6a and 6b are cut-away side schematic views
`of the illuminator module of FIG. 5 along with the
`lamp-heated chuck of the preferred embodiment;
`FIG. 7 is a cross-sectional view of the modified
`quartz window for a fabrication reactor used in con-
`junction with the preferred embodiment of the present
`invention;
`FIG. 8 is a cross-sectional schematic view of the
`preferred embodiment of the base of the chuck;
`FIG. 9 is an isometric view of a silicon carbide or
`graphite or silicon disk used for light absorption in
`conjunction with the preferred embodiment; and
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`Intel Corp. et al. Exhibit 1017
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`

`
`7
`patent application Ser. No. 07/638472, now U.S. Pat.
`No. 5,239,216 .
`Process control computer 104 checks the status of
`multi—zone illuminator 84 for diagnosis/prognosis pur-
`poses and provides multiple temperature control signals
`to PID controller 106 in response to temperature read-
`ings of multi-point sensors. The multi—zone controller
`(or PID controller) receives measured multi-point tem-
`perature sensor outputs as well as the desired wafer
`temperature set point (from process control computer
`104) and delivers suitable power set points to the lamp
`power supply module 108. Signal lines 110 between
`process control computer 104 and multi—zone illumina-
`tor 84 include signals from multi-point temperature
`sensors for real-time semiconductor wafer 38 tempera-
`ture measurements and lamp power readings.
`FIG. 4 shows a perspective view of the multi-proc-
`essing reactor 50 described in FIG. 3. Reactor casing 56
`surrounds process chamber wall 58 within which pro-
`cess chamber 72 (not shown) establishes the semicon-
`ductor wafer 36 fabrication environment. The reactor
`casing 56 rigidly supports multi-zone lamp module 84
`which includes chuck 82 of the preferred embodiment.
`Adjacent to reactor chamber 56 is vacuum load-lock
`chamber 92 within which appears cassette 96 for hold-
`ing semiconductor wafers 38. Adjacent to vacuum load-
`lock chamber 92 is process control computer 104 which
`controls the operation of the various elements associ-
`ated with processing reactor 50.
`FIG. 5 illustrates a partially cut-away prospective
`view of a three-zone version of a multi—zone illuminator
`module 84 which supports and heats chuck 82 of the
`present invention. Moreover, FIGS. 6a and 6b show a
`side schematic view of chuck 82 associated with illumi-
`nator module 84 and quartz window 80 associated with
`reactor casing 56. U.S. patent application Ser. No.
`07/690,426 describes illuminator module 84 in detail.
`That description is expressly incorporated by reference
`to the same extent as if herein written. Appropriate
`modifications of illuminator module 84 may, however,
`be necessary to properly house and support chuck 82.
`These modifications are well within the scope of the
`present invention.
`Referring in particular to chuck 82 of FIG. 6a, ther-
`mocouple adaptor 112 connects to thermocouple feed-
`throughs 114 which connect to spring-loaded thermo-
`couple 116. Thermocouple adaptor 112 attaches at
`mount 118 to insulating thermocouple adaptor 120
`(made of teflon or another material). Thermocouple
`adapter 120 mounts to insulating adaptor 122 which
`receives thermocouple/helium tube 124 and tin melt
`tube 126. Within adaptor 122 are helium inlet 128 to
`heat thermocouple/helium tube 124 and tin powder
`connection 130 to tin melt tube 126.
`
`In the preferred embodiment, thermocouple/helium
`tube 124 has an outside diameter of approximately 3/16
`inch for helium flow and contains spring‘-loaded ther-
`mocouple 116. Additionally, RF connection pin 132
`connects to tin melt tube 126. Adaptor 122 mounts to
`insulating adaptor 134 which receives teflon tube 136,
`tin melt tube 126, and thermocouple/helium tube 124.
`Surrounding teflon tube 136 and tin melt tube 126 ap-
`pears stainless steel or aluminum tube 138 for receiving
`and circulating cooling water from cooling water inlet
`140 through cooling channel 145 back to cooling water
`outlet (not shown) respectively. Cooling water from
`cooling water channel 145 provides sufficient cooling
`for the vacuum O-ring seal 147 between quartz tube 154
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`8
`and the wafer-cooled stainless steel tube 138. Connect-
`ing insulating adaptors 120, 122, and 134 are tie bolts
`147. Between the inner surface of illuminator module 84
`and the outer surface of water-cooled stainless steel tube
`138 appears air gap 148 which permits a cooling air flow
`into space 150 between lamps 152 and quartz window
`80. The air flow is provided via connection tube 144.
`The air flow cools quartz window 80 and lamps 152.
`For the preferred embodiment, quartz window 80 has
`been modified to include quartz tube 154 which sup-
`ports teflon tube 136 and receives tin melt tube 126 and
`thermocouple/helium tube 124. (FIG. 7 shows the
`quartz window 80 modification for the preferred em-
`bodiment.) In FIG. 6a, quartz tube 154 is fused to quartz
`window base 155 and permits passage of tin melt tube
`126 and thermocouple/helium tube 124 through aper-
`ture 156. Sleeve 154 joins teflon tube 136 at vacuum
`sealed interface 139. Quartz window 80 also includes
`inert gas flow channel 158 which receives inert gas
`through channel 160 of reactor casing 56. Channel 158
`in quartz window 80 allows an inert gas (e.g., Ar, He or
`a process diluent such as H2 or N2) between quartz
`window 80 and the top portion of chuck 82 which may
`be silicon carbide disk 171 or simply a black anodized
`surface on chuck top surface. The inert gas purge main-
`tains a clean quartz window surface in the gap 175
`region. Thermocouple/helium tube 124 and tin melt
`tube 126 join to chuck base 162 which includes tin
`chamber 164 surrounded by cladding 166. Adjoining
`cladding 166 some small distance from quartz window
`80 is silicon carbide or silicon or sand-blasted quartz
`disk 171. Within tin melt chamber 164 appears a tin
`medium 170 which, when heated to process tempera-
`tures of fabrication reactor 50 forms a liquid to promote
`conductive heat flow from the surface of silicon carbide
`disk 168 as well as radially between the center and edge
`regions. Clamped to the bottom surface of cladding 166
`is semiconductor wafer 38.
`
`Referring to FIGS. 6a and 6b, thermocouple tip 171 is
`spring-loaded by spring-loaded thermocouple mecha-
`nism 118 within an adaptor 120 to sense the temperature
`of cladding 166. FIG. 6b shows that thermocouple tip
`171 may either be designed to contact semiconductor
`wafer 38 backside or simply make thermally conductive
`contact with cladding 166 for determining semiconduc-
`tor wafer 38 temperature.
`FIG. 8 shows an isometric view of the preferred
`embodiment of chuck 82. Base 64 includes radially ori-
`ented channels 176 from center hole 174 through which
`helium flows to purge the back of semiconductor wafer
`38. In the preferred embodiment, a central hole 174
`approximately inch in diameter is used for both the
`thermocouple connection and for helium (or argon)
`purge gas flow to the back of semiconductor wafer 38.
`The bottom cladding 166 of chuck 82 of the preferred
`embodiment comprises a 316 L stainless steel which is
`nickel plated or aluminum which is § of an inch thick.
`Other metallic