(19) United States
`(12) Reissued Patent
`Flamm
`
`US RE40,264 E
`(10) Patent Number:
`(45) Date of Reissued Patent:
`Apr. 29, 2008
`
`USO0RE40264E
`
`(54) MULTI-TEMPERATURE PROCESSING
`
`5,700,734 A
`5,705,433 A *
`
`...................... .. 438/592
`12/1997 Ooishi
`1/1998 Olson et al.
`438/695
`
`(76)
`
`Inventor: Daniel L. Flamm, 476 Green View Dr.,
`Walnut Creek, CA (US) 94596
`
`(21) APP1, N01 10/439,245
`.
`.
`Ffled"
`
`May 14’ 2003
`
`(22)
`
`Related U-S- Patent D°°“m°“tS
`
`Reissue 0ft
`(64) Patent No.:
`Issued:
`App1.N0.;
`Filed,
`
`6,231,776
`May 15, 2001
`09/151,163
`sep_ 10, 1993
`
`(63) Continuation-in-part of application No. 08/567,224, filed on
`Dec. 4, 1995, now abandoned.
`Provisional application No. 60/058,650, filed on Sep. 11,
`1997.
`
`(60)
`
`(51)
`
`Int‘ Cl‘
`H05H 1/00
`H01L 21/302
`
`(2006.01)
`(2006.01)
`
`(52) U.s. Cl.
`
`........................... .. 216/59; 216/67; 216/68;
`216/74; 438/714; 438/715; 204/192.32;
`15634552; 156/34553
`(58) Field of Classification Search ............... .. 438/715,
`438/719, 721, 725, 737, 738; 216/41, 49,
`216/63—67, 75, 79; 156/345.27, 345.52, 345.53
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U~S~ PATENT DOCUMENTS
`5,179,264 A
`1/1993 Cuomo et al.
`....... N 219/121.43
`5,294,778 A
`3/1994 Carman et al.
`........... N 219/385
`5,320,982 A *
`6/1994 Tsubone et al.
`428/714
`5,556,204 A *
`9/1996 Tamum et al.
`374/161
`5,571,366 A
`11/1996 Ishii
`. . . . . . . . . . . .
`. . . .. 156/345
`5,609,720 A *
`3/ 1997 LeI1Z et 31,
`--
`433/715
`5,645,683 A
`7/1997 Miyamoto .... ..
`.. 156/643.1
`5,667,631 A
`9/1997 Holland et al.
`.
`..... .. 216/13
`5,695,564 A
`12/1997 Imahashi
`.................. .. 118/719
`
`
`
`..
`
`
`
`438/719
`--------- --
`5/1998 1i_Z111<a
`5,756,401 A
`. . . .. 216/68
`6/1998 Rice et al.
`. . . . .
`5,770,099 A
`156/345
`1/1999 Wicker et al.
`.
`5,863,376 A
`. . . . .. 156/345
`7/1999 Rice et al.
`. . . . .
`5,925,212 A
`.. 315/111.21
`8/1999 Fong etal.
`5,939,831 A
`.................. .. 216/67
`9/1999 Grosshart
`5,948,283 A
`5,965,034 A * 10/1999 Vinogradov et al.
`........ .. 216/68
`6,008,139 A
`12/1999 Pan et al.
`........... ..
`438/730
`6 033 478 A
`3/2000 Kholodenko
`118/500
`6,042,901 A
`3/2000 Denison et al.
`427/579
`6,048,798 A
`4/2000 Gadgil etal.
`............. .. 438/714
`6,068,784 A
`5/2000 Collins et al.
`.............. .. 216/68
`6,077,357 A
`6/2000 Rossman et al.
`.
`118/728
`6,087,264 A
`7/2000 Sh1n et al.
`...... ..
`438/706
`6,090,303 A
`7/2000 Collins et al.
`216/68
`211221211:
`12/5233 6:14 444444444444~ 112/222
`’
`’
`0 ms e a ' """""" "
`6,167,834 B1
`1/2001 Wang et al.
`.............. .. 418/723
`xarlgs e: 3%’
`,
`,
`3.1‘ S 6 a.
`6/2001 Marks et al.
`2001/0003676 A1
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`JP
`
`1236226 A2
`59076876 A *
`
`7/2001
`5/1984
`
`7/2001
`
`W0'°1/4“89 42
`W0
`* cited by examiner
`Primary Examiner—Anita Alanko
`(74) Attorney, Agent, or Firm—Daniel L. Flamm
`(57)
`ABSTRACT
`
`including a
`The present invention provides a technique,
`method and apparatus, for etching a substrate in the manu-
`facture of a device. The apparatus includes a chamber and a
`substrate holder disposed in the chamber. The substrate
`holder has a selected thermal mass to facilitate changing the
`temperature of ‘the substrate to be etched during etching
`processes. That 1s, the selected thermal mass ofthe substrate
`helder a110WS for a Change from 21 firet Ielnperature 10 8
`second temperature within a character1st1c t1me per1od to
`process a film. The present technique can, for example,
`provide different processing temperatures during an etching
`process or the like.
`
`59 Claims, 15 Drawing Sheets
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 1 of 15
`
`US RE40,264 E
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 2 of 15
`
`US RE40,264 E
`
`FIE. 2/1
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 3 of 15
`
`US RE40,264 E
`
`55
`
`FIG. 26‘
`
`57
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 4 of 15
`
`US RE40,264 E
`
`52
`
`vw
`
`%%%%%%%%%%~
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 5 of 15
`
`US RE40,264 E
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 6 of 15
`
`US RE40,264 E
`
`151
`
`(132
`
`O O
`
`3 O
`
`1530
`O
`
`/\/
`
`134
`
`°j’x‘2"
`
`114
`
`13?
`
`
`
`K 1
`
`22
`
`124
`
`122
`
`124
`
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`
`
`14° 127
`M
`
`‘(((((((11.
`
`12
`
`128
`
`126
`
`133
`
`I.
`
`112
`
`Fig. 3
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 7 of 15
`
`US RE40,264 E
`
`119
`
`112
`
`l‘§‘CCCiC€.
`
`=
`
`"—
`
`116
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 8 of 15
`
`US RE40,264 E
`
`
`
`FIG.
`
`.54
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 9 of 15
`
`US RE40,264 E
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 10 of 15
`
`US RE40,264 E
`
`2m
`
`2m
`
`2:
`5%.
`
`00000000 0
`
`Sm
`
`mE
`
`mum
`
`/lyum
`
`05
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 11 of 15
`
`US RE40,264 E
`
`(TOP VIEW)
`
`613
`
`605
`
`
`
`SIDE
`VIEW
`KB]!
`
`605
`
`snbsvusw
`“CH
`
`CHUCR
`
`\
`
`615
`
`FIG. 6
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 12 of 15
`
`US RE40,264 E
`
`.2m>>Fmflagozwwmm
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`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 13 of 15
`
`US RE40,264 E
`
`Fluid at
`temperature T1
`
`809
`
`
`
`Fluid at
`temperature T2
`
`803
`
`t_
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`U.S. Patent
`
`Apr. 29,2008
`
`Sheet 14 of 15
`
`US RE40,264 E
`
`/P/ 900
`
`Photoresist
`
`
`
`Tungsten Silicide
`
`Polysificon
`
`Siticon dioxide
`
`Silicon Wafer
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`Patent
`
`AP1‘- 29, 2008
`
`Sheet 15 of 15
`
`US RE40 264 E
`
`Temp reduced at
`
`U
`
`t
`
`520 nm
`
`B
`
`Resist ashed in 02
`(different wavelength)
`
`Constant Temperature
`
`Time
`
`Intensityat520nm
`
`0
`
`40
`
`80
`
`Time
`
`120
`
`160
`
`A. St’-'6 native oxide "breakthrough"
`B. C12 piasma is ignited
`0. WSi, begins to c't'ea‘r'(endpoint)
`D. Polysilicon is exposed
`E. Polysilicon cleared to oxide
`
`H. Plasma extinguished and O2 teed
`gas flow is started
`I. Oé plasma is started
`J 02 plasma is extinguished.
`
`Fig. 10
`
`Intel Corp. et al. Exhibit 1001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`US RE40,264 E
`
`1
`MULTI-TEMPERATURE PROCESSING
`
`Matter enclosed in heavy brackets [ ] appears in the
`original patent but forms no part of this reissue specifi-
`cation; matter printed in italics indicates the additions
`made by reissue.
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This present application is a continuation-in-part of U.S.
`application Ser. No. 60/058,650 filed Sep. 11, 1997, and a
`continuation-in-part of U.S. application Ser. No. 08/567,224
`filed Dec. 4, 1995, now abandoned which are hereby incor-
`porated by reference for all purposes.
`
`BACKGROUND OF THE INVENTION
`
`This invention relates generally to plasma processing.
`More particularly, one aspect of the invention is for greatly
`improved plasma processing of devices using an in-situ
`temperature application technique. Another aspect of the
`invention is illustrated in an example with regard to plasma
`etching or resist stripping used in the manufacture of semi-
`conductor devices. The invention is also of benefit in plasma
`assisted chemical vapor deposition (CVD) for the manufac-
`ture of semiconductor devices. But it will be recognized that
`the invention has a wider range of applicability. Merely by
`way of example, the invention also can be applied in other
`plasma etching applications, and deposition of materials
`such as silicon, silicon dioxide, silicon nitride, polysilicon,
`among others.
`Plasma processing techniques can occur in a variety of
`semiconductor manufacturing processes. Examples of
`plasma processing techniques occur in chemical dry etching
`(CDE),
`ion-assisted etching (IAE), and plasma enhanced
`chemical vapor deposition (PECVD),
`including remote
`plasma deposition (RPCVD) and ion-assisted plasma
`enhanced chemical vapor deposition (IAPECVD). These
`plasma processing techniques often rely upon radio fre-
`quency power (rf) supplied to an inductive coil for providing
`power to produce with the aid of a plasma.
`Plasmas can be used to form neutral species (i.e.,
`uncharged) for purposes of removing or forming films in the
`manufacture of integrated circuit devices. For instance,
`chemical dry etching is a technique which generally depends
`on gas-surface reactions involving these neutral species
`without substantial ion bombardment.
`
`In a number of manufacturing processes, ion bombard-
`ment to substrate surfaces is often undesirable. This ion
`bombardment, however, is known to have harmful effects on
`properties of material layers in devices and excessive ion
`bombardment flux and energy can lead to intermixing of
`materials in adjacent device layers, breaking down oxide
`and “wear out,” injecting of contaminative material formed
`in the processing environment into substrate material layers,
`harmful changes in substrate morphology (e.g.
`amophotization), etc.
`Ion assisted etching processes, however, rely upon ion
`bombardment to the substrate surface in defining selected
`films. But these ion assisted etching processes commonly
`have a lower selectivity relative to conventional CDE pro-
`cesses. Hence, CDE is often chosen when high selectivity is
`desired and ion bombardment to substrates is to be avoided.
`
`In generally most, if not all, of the above processes
`maintain temperature in a “batch” mode. That is, the tem-
`perature of surfaces in a chamber and of the substrate being
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`
`processed in such chamber are controlled to be at a sub-
`stantially a single value of temperature during processing.
`From the above it is seen that an improved technique,
`including a method and apparatus, for plasma processing is
`often desired.
`
`SUMMARY OF THE INVENTION
`
`The present invention provides a technique, including a
`method and apparatus, for fabricating a product using a
`plasma discharge. One aspect of the present technique relies
`upon multi-stage etching processes for selectively removing
`a film on a workpiece using differing temperatures.
`It
`overcomes serious disadvantages of prior art methods in
`which throughput and etching rate were lowered in order to
`avoid excessive device damage to a workpiece. In particular,
`this technique is extremely beneficial for removing resist
`masks which have been used to effect selective ion implan-
`tation of a substrate in some embodiments. In general,
`implantation of ions into a resist masking surface causes the
`upper surface of said resist to become extremely cross-
`linked and contaminated by materials from the ion bom-
`bardment. If the cross-linked layer is exposed to excessive
`temperature, it is prone to rupture and forms contaminative
`particulate matter. Hence, the entire resist layer is often
`processed at a low temperature to avoid this particle prob-
`lem. Processing at a lower temperature often requires exces-
`sive time which lowers throughput. Accordingly, the present
`invention overcomes these disadvantages of conventional
`processes by rapidly removing a majority of resist at a higher
`temperature after an ion implanted layer is removed without
`substantial particle generation at a lower temperature.
`In another aspect, the present invention provides a process
`which utilizes temperature changes to achieve high etch
`rates while simultaneously maintaining high etch selectivity
`between a layer which is being pattered or removed other
`material layers. An embodiment of this process advanta-
`geously employs a sequence of temperature changes as an
`unexpected means to avoid various types of processing
`damage to the a device and material layers. A novel inven-
`tive means for effecting a suitable controlled change in
`temperature as part of a process involves the use of a
`workpiece support which has low thermal mass in compari-
`son to the heat transfer means. In an aspect of this invention,
`a fluid is utilized to change the temperature of a workpiece.
`In another aspect, the thermal capacity of a circulating fluid
`is sufficiently greater than the thermal capacity of the
`workpiece support that it permits maintaining the workpiece
`at a substantially uniform temperature.
`Still another aspect of the invention provides an apparatus
`for etching a substrate in the manufacture of a device using
`diiferent
`temperatures during etching. The apparatus
`includes a chamber and a substrate holder disposed in the
`chamber. The substrate holder has a selected thermal mass to
`
`facilitate changing the temperature of the substrate to be
`etched. That is, the selected thermal mass of the substrate
`holder allows for a change from a first temperature to a
`second temperature within a characteristic time period to
`process a film. The present apparatus can, for example,
`provide different processing temperatures during an etching
`process or the like.
`The present
`invention achieves these benefits in the
`context of known process technology. However, a further
`understanding of the nature and advantages of the present
`invention may be realized by reference to the latter portions
`of the specification and attached drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a simplified diagram of a plasma etching
`apparatus according to the present invention;
`
`Intel Corp. et al. Exhibit 1 001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`US RE40,264 E
`
`3
`FIGS. 2A—2E are simplified configurations using wave
`adjustment circuits according to the present invention;
`FIG. 3 is a simplified diagram of a chemical vapor
`deposition apparatus according to the present invention;
`FIG. 4 is a simplified diagram of a stripper according to
`the present invention;
`FIGS. 5A—5C are more detailed simplified diagrams of a
`helical resonator according to the present invention;
`FIG. 6 is a simplified block diagram of a substrate holder
`according to the present invention;
`FIG. 7 is a simplified diagram of a temperature control
`system according to an embodiment of the present inven-
`tion;
`FIG. 8 is a simplified diagram of a fluid reservoir system
`according to an embodiment of the present invention;
`FIG. 9 is a [simplified diagram of a] simplified diagram of
`a semiconductor substrate according to an embodiment of
`the present invention; and
`FIG. 10 is a simplified [flow diagram of a heating] process
`according to the present invention.
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`FIG. 1 is a simplified diagram of a plasma etch apparatus
`10 according to the present invention. This etch apparatus is
`provided with an inductive applicator, e.g., inductive coil.
`This etch apparatus depicted, however,
`is merely an
`illustration, and should not limit the scope of the claims as
`defined herein. One of ordinary skilled in the art may
`implement the present invention with other treatment cham-
`bers and the like.
`
`The etch apparatus includes a chamber 12, a feed source
`14, an exhaust 16, a product support check or pedestal 18,
`an inductive applicator 20, a radio frequency (“rf”) power
`source 22 to the inductive applicator 20, wave adjustment
`circuits 24, 29 (WACs), a radio frequency power source 35
`to the pedestal 18, a controller 36, an agile temperature
`control means [19], and other elements. Optionally, the etch
`apparatus includes a gas distributor 17.
`The chamber 12 can be any suitable chamber capable of
`housing a product 28, such as a wafer to be etched, and for
`providing a plasma discharge therein. The chamber can be a
`domed chamber for providing a uniform plasma distribution
`over the product 28 to be etched, but the chamber also can
`be configured in other shapes or geometries, e.g., flat ceiling,
`truncated pyramid, cylindrical, rectangular, etc. Depending
`upon the application, the chamber is selected to produce a
`uniform entity density over the pedestal 18, providing a high
`density of entities (i.e., etchant species) for etching unifor-
`mity.
`The product support chuck can rapidly change its tem-
`perature in ways defined herein as well as others. The wafer
`is often thermally coupled to the support check which
`permits maintaining the wafer temperature in a known
`relationship with respect to the chuck. Coupling will often
`comprise an electrostatic chuck or mechanical clamps,
`which apply a pressure to bring the product
`into close
`proximity with the support check, which enables a relatively
`good thermal contact between the wafer and support chuck.
`The support chuck and wafer are often maintained at a
`substantially equal temperature. A pressure of gas is often
`applied through small openings in the support chuck behind
`the wafer in order to improve thermal contact and heat
`transfer between the wafer and support chuck.
`The present chamber includes a dome 25 having an
`interior surface 26 made of quartz or other suitable materi-
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
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`
`60
`
`65
`
`4
`
`als. The exterior surface of the chamber is typically a
`dielectric material such as a ceramic or the like. Chamber 12
`also includes a process kit with a focus ring 32, a cover (not
`shown), and other elements. Preferably,
`the plasma dis-
`charge is derived from the inductively coupled plasma
`source that is a de-coupled plasma source (“DPS”) or a
`helical resonator, although other sources can be employed.
`The de-coupled source originates from rf power derived
`from the inductive applicator 20. Inductively coupled power
`is derived from the power source 22. The rf signal frequen-
`cies ranging from 800 kHz to 80 MHZ can be provided to the
`inductive applicator 20. Preferably, the rf signal frequencies
`range from 5 MHZ to 60 MHZ. The inductive applicator
`(e.g., coil, antenna, transmission line, etc.) overlying the
`chamber ceiling can be made using a variety of shapes and
`ranges of shapes. For example, the inductive applicator can
`be a single integral conductive film, a transmission line, or
`multiple coil windings. The shape of the inductive applicator
`and its location relative to the chamber are selected to
`
`provide a plasma overlying the pedestal to improve etch
`uniformity.
`The plasma discharge (or plasma source) is derived from
`the inductive applicator 20 operating with selected phase 23
`and anti-phase 27 potentials (i.e., voltages) that substantially
`cancel each other. The controller 36 is operably coupled to
`the wave adjustment circuits 24, 29. In one embodiment,
`wave adjustment circuits 24, 29 provide an inductive appli-
`cator operating at full-wave multiples 21. This embodiment
`of full-wave multiple operation provides for balanced
`capacitance of phase 23 and anti-phase voltages 27 along the
`inductive applicator (or coil adjacent to the plasma). This
`full-wave multiple operation reduces or substantially elimi-
`nates the amount of capacitively coupled power from the
`plasma source to chamber bodies (e.g., pedestal, walls,
`wafer, etc.) at or close to ground potential. Alternatively, the
`wave adjustment circuits 24, 29 provide an inductive appli-
`cator that
`is effectively made shorter or longer than a
`full-wave length multiple by a selected amount,
`thereby
`operating at selected phase and anti-phase voltages that are
`not full-wave multiples. Alternatively, more than two, one or
`even no wave adjustment circuits can be provided in other
`embodiments. But in all of these above embodiments, the
`phase and anti-phase potentials substantially cancel each
`other,
`thereby providing substantially no capacitively
`coupled power from the plasma source to the chamber
`bodies.
`
`In alternative embodiments, the wave adjustment circuit
`can be configured to provide selected phase and anti-phase
`coupled voltages coupled from the inductive applicator to
`the plasma that do not cancel. This provides a controlled
`potential between the plasma and the chamber bodies, e.g.,
`the substrate, grounded surfaces, walls, etc.
`In one
`embodiment, the wave adjustment circuits can be used to
`selectively reduce current (i.e., capacitively coupled current)
`to the plasma. This can occur when certain high potential
`difference regions of the inductive applicator to the plasma
`are positioned (or kept) away from the plasma region (or
`inductor-containing-the-plasma region) by making them go
`into the wafer adjustment circuit assemblies, which are
`typically configured outside of the plasma region. In this
`embodiment, capacitive current is reduced and a selected
`degree of symmetry between the phase and anti-phase of the
`coupled voltages is maintained, thereby provided a selected
`potential or even substantially ground potential. In other
`embodiments, the wave adjustment circuits can be used to
`selectively increase current
`(i.e., capacitively coupled
`current) to the plasma.
`
`Intel Corp. et al. Exhibit 1 001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`US RE40,264 E
`
`5
`As shown, the wave adjustment circuits are attached (e.g.,
`connected, coupled, etc.) to ends of the inductive applicator.
`Alternatively, each of these wave adjustment circuits can be
`attached at an intermediate position away from the inductive
`application ends. Accordingly, upper and lower tap positions
`for respective wave adjustment circuits can be adjustable.
`But both the inductive applicator portions below and above
`each tap position are active. That is, they both can interact
`with the plasma discharge.
`A sensing apparatus can be used to sense plasma voltage
`which is used to provide automatic turning of the wave
`adjustment circuits and any rf matching circuit between the
`rf generator and the plasma treatment chamber. This sensing
`apparatus can maintain the average AC potential at zero or
`a selected value relative to ground or any other reference
`value. This wave adjustment circuit provides for a selected
`potential difference between the plasma source and chamber
`bodies. These chamber bodies may be at a ground potential
`or a potential supplied by another bias supply, e.g., See FIG.
`1 reference numeral 35. Examples of wave adjustment
`circuits are described by way of the FIGS. below.
`For instance, FIGS. 2A to 2E are simplified configurations
`using the wave adjustment circuits according to the present
`invention. These simplified configurations should not limit
`the scope of the claims herein. In an embodiment, these
`wave adjustment circuits employ substantially equal circuit
`elements (e.g.,
`inductors, capacitors,
`transmission line
`sections, and others) such that the electrical length of the
`wave adjustment circuits in series with the inductive appli-
`cator coupling power to the plasma is substantially an
`integral multiple of one wavelength. In other embodiments,
`the circuit elements provide for inductive applicators at
`other wavelength multiples, e.g., one-sixteenth-wave, one-
`eighth-wave, quarter-wave, half-wave, three-quarter wave,
`etc. In these embodiments (e.g., full-wave multiple, half-
`wave, quarter-wave, etc.), the phase and anti-phase relation-
`ship between the plasma potentials substantially cancel each
`other. In further embodiments, the wave adjustment circuits
`employ circuit elements that provide plasma applicators
`with phase and anti-phase potential relationships that do not
`cancel each other out using a variety of wave length por-
`tions.
`
`FIG. 2A is a simplified illustration of a plasma source 50
`using wave adjustment circuits and an agile temperature
`chuck 75 according to an embodiment of the present inven-
`tion. This plasma source 50 includes a discharge tube 52, an
`inductive applicator 55, an exterior shield 54, an upper wave
`adjustment circuit 57, a lower wave adjustment circuit 59, an
`rf power supply 61, and other elements. The upper wave
`adjustment circuit 57 is a helical coil
`transmission line
`portion 69, outside of the plasma source region 60. Lower
`wave adjustment circuit 59 also is a helical coil transmission
`line portion 67 outside of the plasma source region 60. The
`power supply 61 is attached 65 to this lower helical coil
`portion 67, and is grounded 63. Each of the wave adjustment
`circuits also are shielded 66, 68.
`In this embodiment,
`the wave adjustment circuits are
`adjusted to provide substantially zero AC voltage at one
`point on the inductive coil (refer to point 00 in FIG. 2A).
`This embodiment also provides substantially equal phase 70
`and anti-phase 71 voltage distributions in directions about
`this point (refer to 00-A and 00-C in FIG. 2A) and provides
`substantially equal capacitance coupling to the plasma from
`physical inductor elements (00-C) and (00-A), carrying the
`phase and anti-phase potentials. Voltage distributions 00-A
`and 00-C are combined with C-D and A-B (shown by the
`phantom lines) to substantially comprise a full-wave voltage
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`distribution in this embodiment where the desired configu-
`ration is a selected phase/anti-phase portion of a full-wave
`inductor (or helical
`resonator) surrounding the plasma
`source discharge tube.
`In this embodiment, it is desirable to reduce or minimize
`capacitive coupling current from the inductive element to
`the plasma discharge in the plasma source. Since the capaci-
`tive current increases monotonically with the magnitude of
`the difference of peak phase and anti-phase voltages, which
`occur at points A and C in FIG. 2A, this coupling can be
`lessened by reducing this voltage difference. In FIG. 2A, for
`example,
`it is achieved by way of two wave adjustment
`circuits 57, 59. Coil 55 (or discharge source) is a helical
`resonator and the wave adjustment circuits 57, 59 are helical
`resonators.
`
`The discharge source helical resonator 53 can be con-
`structed using conventional design formulae. Generally, this
`helical resonator includes an electrical length which is a
`selected phase portion “x” (A to 00 to C) of a full-wave
`helical resonator. The helical resonator wave adjustment
`circuits are each selected to jointly comprise a portion (231-x)
`of full-wave helical resonators. Physical parameters for the
`wave adjustment helical resonators can be selected to realize
`practical physical dimensions and appropriate Q, Z0, etc
`values. In particular, some or even all of the transmission
`line parameters (Q, Z0, etc.) of the wave adjustment circuit
`sections may be selected to be substantially the same as the
`transmission line parameters of the inductive applicator. The
`portion of the inductive plasma applicator helical resonator,
`on the other hand, is designed and sized to provide selected
`uniformity values over substrate dimensions within an eco-
`nomical equipment size and reduced Q.
`The wave adjustment circuit provides for external rf
`power coupling, which can be used to control and match
`power to the plasma source, as compared to conventional
`techniques used in helical resonators and the like.
`In
`particular, conventional techniques often match to, couple
`power to, or match to the impedance of the power supply to
`the helical resonator by varying a tap position along the coil
`above the grounded position, or selecting a fixed tap position
`relative to a grounded coil end and matching to the imped-
`ance at this position using a conventional matching network,
`e.g., LC network, at network, etc. Varying this tap position
`along the coil within a plasma source is often cumbersome
`and generally imposes difficult mechanical design problems.
`Using the fixed tap and external matching network also is
`cumbersome and can cause unanticipated changes in the
`discharge Q, and therefore influences its operating mode and
`stability. In the present embodiments, the wave adjustment
`circuits can be positioned outside of the plasma source (or
`constrained in space containing the inductive coil, e.g., See
`FIG. 2A. Accordingly, the mechanical design (e.g., means
`for varying tap position, change in the effective rf power
`coupling point by electrical means, etc.) of the tap position
`are simplified relative to those conventional techniques.
`In the present embodiment, rf power is fed into the lower
`wave adjustment circuit 59. Alternatively, rf power can be
`fed into the upper wave adjustment circuit (not shown). The
`rf power also can be coupled directly into the inductive
`plasma coupling applicator (e.g., coil, etc.) in the wave
`adjustment circuit design, as illustrated by FIG. 2B.
`Alternatively, other applications will use a single wave
`adjustment circuit, as illustrated by FIG. 2C. Power can be
`coupled into this wave adjustment circuit or by conventional
`techniques such as a tap in the coil phase.
`In some
`embodiments, this tap in the coil phase is positioned above
`the grounded end. An external impedance matching network
`
`Intel Corp. et al. Exhibit 1 001
`
`Intel Corp. et al. Exhibit 1001
`
`

`
`US RE40,264 E
`
`7
`may then be operably coupled to the power for satisfactory
`power transfer efficiency from, for example, a conventional
`coaxial cable to impedances (current to voltage rations)
`existing between the wave adjustment circuit terminated end
`of the applicator and the grounded end.
`A further embodiment using multiple inductive plasma
`applicators also is provided, as shown in FIG. 2D. This
`embodiment includes multiple plasma applicators (PA 1,
`PA2. .
`. PAn). These plasma applicators respectively provide
`selected combinations of inductively coupled power and
`capacitively coupled power from respective voltage poten-
`tials (V1, V2.
`.
`. Vn). Each of these plasma applicators
`derives power from its power source (PS1, PS2.
`.
`. PSn)
`either directly through an appropriate matching or coupling
`network or by coupling to a wave adjustment circuit as
`described. Alternatively, a single power supply using power
`splitters and impedance matching networks can be coupled
`to each (or more than two) of the plasma applicators.
`Alternatively, more than one power supply can be used
`where at least one power supply is shared among more than
`one plasma applicator. Each power source is coupled to its
`respective wave adjustment circuits (WACI, WAC2.
`.
`.
`WACn).
`Generally, each plasma applicator has an upper wave
`adjustment circuit (e.g., WACla, WAC2a. .
`. WACna) and a
`lower wave adjustment circuit (e.g., WAClb, WAC2b.
`.
`.
`WACnb). The combination of upper and lower wave adjust-
`ment circuits are used to adjust the plasma source potential
`for each plasma source zone. Alternatively, a single wave
`adjustment circuit can be used for each plasma applicator.
`Each wave adjustment circuit can provide substantially the
`same impedance characteristics, or substantially distinct
`impedance characteristics. Of course, the particular configu-
`ration used will depend upon the application.
`For instance, multiple plasma applicators can be used to
`employ distinct excitation frequencies for selected zones in
`a variety of applications. These applications include film
`deposition using plasma enhanced chemical deposition,
`etching by way of ion enhanced etching or chemical dry
`etching and others. Plasma cleaning also can be performed
`by way of the multiple plasma applicators. Specifically, at
`least one of the plasma applicators will define a cleaning
`plasma used for cleaning purposes. In one embodiment, this
`cleaning plasma can have an oxygen containing species.
`This cleaning plasma is defined by using an oxygen
`discharge, which is sustained by microwave power to a
`cavity or resonant microwave chamber abutting or surround-
`ing a conventional dielectric vessel. Of course, a variety of
`other processes also can be performed by way of this
`multiple plasma applicator embodiment.
`This present application using multiple plasma applica-
`tors can provide a multi-zone (or multi-chamber) plasma
`source without the use of conventional mechanical separa-
`tion means (e.g., balfles, separate process chambers, etc.).
`Alternatively, the degree of interaction between adjacent
`zones or chambers can be relaxed owing to the use of
`voltage potential control via wave adjustment circuits. This
`plasma source provides for multiple plasma source
`chambers, each with its own control via its own plasma
`applicator. Accordingly, each plasma applicator provides a
`physical zone region (i.e., plasma source) with selected
`plasma characteristics (e.g., capacitively coupled current,
`inductively coupled current, etc.). These zones can be used
`alone or can be combined with other zones. Of course, the
`particular configuration will depend upon the application.
`In the present embodiments, the wave adjustment circuit
`can be made from any suitable combi