Trials@uspto.gov
`571.272.7822
`
`
` Paper No. 9
`
`Filed: June 13, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`and MICRON TECHNOLOGY, INC.
`Petitioner,
`
`v.
`
`DANIEL L. FLAMM,
`Patent Owner.
`
`____________
`
`Case IPR2017-00280
`Patent RE40,264 E
`____________
`
`
`
`Before CHRISTOPHER L. CRUMBLEY, JO-ANNE M. KOKOSKI, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`
`
`
`571.272.7822
`
`
` Paper No. 9
`
`Filed: June 13, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`and MICRON TECHNOLOGY, INC.
`Petitioner,
`
`v.
`
`DANIEL L. FLAMM,
`Patent Owner.
`
`____________
`
`Case IPR2017-00280
`Patent RE40,264 E
`____________
`
`
`
`Before CHRISTOPHER L. CRUMBLEY, JO-ANNE M. KOKOSKI, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`
`
`
`
`IPR2017-00280
`Patent RE40,264 E
`
`
`I. INTRODUCTION
`
`Intel Corporation, GLOBALFOUNDRIES U.S., Inc., and Micron
`
`Technology, Inc. (collectively “Petitioner”), filed a Petition requesting an
`
`inter partes review of claims 27–36, 51–55, 66, 68, and 69 (“the challenged
`
`claims”) of U.S. Patent No. RE40,264 E (Ex. 1001, “the ’264 patent”).
`
`Paper 1 (“Pet.”). Daniel L. Flamm (“Patent Owner”), filed a Preliminary
`
`Response. Paper 8 (“Prelim. Resp.”).
`
`Under 35 U.S.C. § 314(a), an inter partes review may not be instituted
`
`unless the information presented in the Petition shows “there is a reasonable
`
`likelihood that the petitioner would prevail with respect to at least 1 of the
`
`claims challenged in the petition.” Taking into account the arguments
`
`presented in Patent Owner’s Preliminary Response, we conclude that the
`
`information presented in the Petition establishes that there is a reasonable
`
`likelihood that Petitioner would prevail in challenging claims 27–36, 51–55,
`
`66, 68, and 69 as unpatentable under 35 U.S.C. § 103(a). Pursuant to § 314,
`
`we hereby institute an inter partes review as to these claims of the ’264
`
`patent.
`
`A. Related Matters
`
`Petitioner reports that the Patent Owner has asserted the ’264 patent
`
`against Petitioner and other defendants in five proceedings in the Northern
`
`District of California: Case Nos. 5:16-cv-01578-BLF, 5:16-cv-1579-BLF,
`
`5:16-cv-1580-BLF, 5:16-cv-1581-BLF, and 5:16-cv-02252-BLF. Pet. 2.
`
`The parties also state that Lam Research Corporation has filed a declaratory
`
`judgment action against Patent Owner on the ’264 patent (N.D. Cal. Case
`
`No. 5:15-cv-01277-BLF) and has filed seven IPR petitions on the ’264
`
`patent: IPR2015-01759; IPR2015-01764; IPR2015-01766; IPR2015-01768;
`
`2
`
`
`
`IPR2017-00280
`Patent RE40,264 E
`
`
`IPR2016-00468; IPR2016-00469; and IPR2016-00470. Pet. 2; Prelim.
`
`Resp. 1.1 The parties also represent that Samsung Electronics, Co., Ltd. has
`
`filed two IPR petitions on the ’264 patent: IPR2016-01510 and IPR2016-
`
`01512. Id. In addition, we note that Petitioner also filed three other
`
`petitions challenging the patentability of certain claims of the ’264 patent:
`
`IPR2017-00279 (claims 13–26, 64, and 65); IPR2017–00281 (claims 37–50
`
`and 67); and IPR2017–00282 (claims 57–63 and 70–71).
`
`B. The ’264 Patent
`.
`The ’264 patent, titled “Multi-Temperature Processing,” reissued on
`
`April 29, 2008 from U.S. Patent Application No. 10/439,245 (“the ’245
`
`application”), filed on May 14, 2003. Ex. 1001, at [54], [45], [21], [22].
`
`The ’264 patent is a reissue of U.S. Patent No. 6,231,776 B1 (“the ’776
`
`patent”), which issued on May 15, 2001, from U.S. Patent Application No.
`
`09/151,163 (“the ’163 application”) filed September 10, 1998. Id. at [64].
`
`The ’264 patent is directed to a method “for etching a substrate in the
`
`manufacture of a device,” where the method “provide[s] different processing
`
`temperatures during an etching process or the like.” Id. at Abstract. The
`
`apparatus used in the method is shown in Figure 1, reproduced below.
`
`
`
`1 Although Patent Owner notes the prior challenges to the claims of the ’264
`patent, it does not argue that we should exercise our discretion to deny
`institution of the instant Petition on the basis that the same or substantially
`the same art or arguments previously were presented to the Office. See 35
`U.S.C. § 325(d).
`
`3
`
`
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`IPR2017-00280
`Patent RE40,264 E
`
`
`Figure 1 depicts a substrate (product 28, such as a wafer to be etched) on a
`
`substrate holder (product support chuck or pedestal 18) in a chamber
`
`(chamber 12 of plasma etch apparatus 10). Id. at 3:24–25, 3:32–33, 3:40–
`
`
`
`41.
`
`Figures 6 and 7, reproduced below, depict a temperature-controlled
`
`substrate holder and temperature control systems.
`
`4
`
`
`
`
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`IPR2017-00280
`Patent RE40,264 E
`
`
`Figures 6 and 7 depict temperature-controlled fluid flowing through
`
`substrate holder (600, 701), guided by baffles 605, where “[t]he fluid [is]
`
`used to heat or cool the upper surface of the substrate holder.” Ex. 1001,
`
`14:28–63, 16:5–67. Figure 6 also depicts heating elements 607 underneath
`
`the substrate holder, where “[t]he heating elements can selectively heat one
`
`or more zones in a desirable manner.” Id. at 15:10–26. Referring to Figure
`
`7, the operation of the temperature control system is described as follows:
`
`The desired fluid temperature is determined by comparing the
`desired wafer or wafer chuck set point temperature to a measured
`wafer or wafer chuck temperature . . . . The heat exchanger, fluid
`flow rate, coolant-side fluid temperature, heater power, chuck,
`etc. should be designed using conventional means to permit the
`heater to bring the fluid to a setpoint temperature and bring the
`temperature of
`the chuck and wafer
`to predetermined
`temperatures within specified time intervals and within specified
`uniformity limits.
`
`Id. at 16:36–39, 16:50–67.
`
`An example of a semiconductor substrate to be patterned is shown in
`
`Figure 9, reproduced below.
`
`
`
`5
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`
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`IPR2017-00280
`Patent RE40,264 E
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`Figure 9 depicts substrate 901 having a stack of layers including oxide layer
`
`903, polysilicon layer 905, tungsten silicide layer 907, and photoresist
`
`masking layer 909 with opening 911, from the treatment method shown in
`
`Figure 10, reproduced below. Ex. 1001, 17:58–18:57.
`
`Figure 10 depicts the tungsten silicide layer being etched between
`
`points B and D at a constant temperature; the polysilicon layer being
`
`exposed between Points D and E; the polysilicon layer being etched at a
`
`constant temperature beyond point E; and the resist being ashed beyond
`
`
`
`6
`
`
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`IPR2017-00280
`Patent RE40,264 E
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`Point I. Ex. 1001, 18:58–19:64. The plasma’s optical emission at 530
`
`nanometers is monitored to determine when there is breakthrough to the
`
`polysilicon layer (Point D) and a lower etch temperature is required to etch
`
`the polysilicon layer (Point E). Id. at 19:8–24, 19:45–52.
`
`C. Illustrative Claims
`
`
`
`Of the challenged claims, claims 27 and 51 are the only independent
`
`claims at issue. Independent claim 27 is directed to a method of etching a
`
`substrate in the manufacture of a device. Claims 28–36 and 66 depend
`
`directly from independent claim 27. Independent claim 51 is directed to a
`
`method of processing a substrate in the manufacture of a device. Claims 52–
`
`55, 68, and 69 depend directly from claim 51. Independent claims 27 and 51
`
`are reproduced below, with bracketed material added:2
`
`27. A method of etching a substrate in the manufacture of a
`device, the method comprising:
`
`[a] heating a substrate holder to a first substrate holder
`temperature with a heat transfer device, the substrate
`holder having at least one temperature sensing unit;
`
`[b] placing a substrate having a film thereon on a substrate
`holder in a chamber,
`
`[c] etching a first portion of the film at a selected first
`substrate temperature; and
`
`[d] etching a second portion of the film at a selected second
`substrate temperature, the selected second substrate
`temperature being different from the selected first
`substrate temperature
`
`
`
`2 Although the bracketed material is not present in the text of claims 27 or
`51, for clarity and consistency, this Decision will use the bracketed
`nomenclature as utilized by both Petitioner and Patent Owner.
`
`7
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`IPR2017-00280
`Patent RE40,264 E
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`[e] wherein substrate temperature is changed from the
`selected first substrate temperature to the selected
`second substrate
`temperature, using a measured
`substrate temperature, within a preselected time
`interval for processing,
`
`[f] and at least the first substrate temperature or the second
`substrate temperature, in single or in combination, is
`above room temperature.
`
`
`
`51. A method of processing a substrate in the manufacture
`of a device, the method comprising:
`
`[a] placing a substrate having a film thereon on a substrate
`holder in a processing chamber;
`
`[b] the processing chamber comprising the substrate holder, a
`substrate control circuit operable to adjust the substrate
`temperature, a substrate holder temperature sensor, and
`a substrate holder control circuit operable to maintain
`the substrate holder temperature;
`
`[c] performing the first etching of a first portion of the film at
`a selected first substrate temperature;
`
`[d] performing a second etching of a second portion of the
`film at a selected second substrate temperature, the
`second temperature being different from the first
`temperature;
`
`[e] wherein at least one of the film portions is etched while
`heat is being transferred to the substrate holder with the
`substrate holder control circuit; and
`
`[f] the substrate temperature control circuit effectuates the
`change from the first substrate temperature to the
`second substrate temperature within a preselected time
`period.
`
`
`
`
`
`
`
`8
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`IPR2017-00280
`Patent RE40,264 E
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`D. Prior Art Relied Upon
`
`Petitioner relies upon the following prior art references:
`
`Inventor3
`
`Patent
`
`Relevant Dates
`
`Kadomura
`
`Matsumura
`
`Kikuchi
`
`Muller
`
`
`Pet. 4–5.
`
`U.S. Patent No.
`6,063,710
`U.S. Patent No.
`5,151,871
`U.S. Patent No.
`5,226,056
`U.S. Patent No.
`5,605,600
`
`issued May 16, 2000,
`filed Feb. 21, 1997
`issued Sept. 29, 1992,
`filed June 15, 1990
`Issued July 6, 1993,
`filed Jan. 9, 1990
`issued Feb. 25, 1997,
`filed Mar. 13, 1995
`
`Exhibit
`No.
`1005
`
`1003
`
`1004
`
`1002
`
`E. Asserted Grounds of Unpatentability
`
`
`
`Petitioner challenges claims 27–36, 51–55, 66, 68, and 69 of the ’264
`
`patent based on the asserted grounds of unpatentability (“grounds”) set forth
`
`in the table below. Id.
`
`References
`
`Basis
`
`Challenged Claims
`
`Kadomura & Matsumura
`
`Kadomura, Matsumura, & Kikuchi
`
`Kadomura, Matsumura, & Muller
`
`Kikuchi & Matsumura
`
`§ 103(a) 27, 29, 32, 34, 36, and
`66
`§ 103(a) 31 and 35
`
`§ 103(a) 28, 30, 33, 51–55, 68,
`and 69
`
`§ 103(a) 27–28, 31–36, 51–54,
`66, 68, and 69
`
`Kikuchi, Matsumura, & Muller
`
`§ 103(a) 29–30, 34, 55, and 68
`
`
`
`3 For clarity and ease of reference, we only list the first named inventor.
`
`9
`
`
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`IPR2017-00280
`Patent RE40,264 E
`
`
`II. ANALYSIS
`
`A. Claim Construction
`
`The ’264 patent has expired.4 For claims of an expired patent, the
`
`Board’s claim interpretation is similar to that of a district court. See In re
`
`Rambus, Inc., 694 F.3d 42, 46 (Fed. Cir. 2012). Claim terms are given their
`
`ordinary and customary meaning as would be understood by a person of
`
`ordinary skill in the art at the time of the invention, and in the context of the
`
`entire patent disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257
`
`(Fed. Cir. 2007). Only those terms in controversy need to be construed, and
`
`only to the extent necessary to resolve the controversy. See Vivid Techs.,
`
`Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`
`For purposes of this Decision, based on the record before us, we
`
`determine that none of the claim terms requires an explicit construction.
`
`B. Priority Date for the Challenged Claims of the ’264 Patent
`
`As explained previously, the ’264 patent reissued from the ’245
`
`application, filed on May 14, 2003. Ex. 1001, at [21], [22]. The ’245
`
`
`
`4 The ’264 patent expired no later than December 4, 2015, which is twenty
`years after December 4, 1995, the earliest filing date of an application to
`which the ’264 claims priority. See Ex. 1001 [63]; 35 U.S.C. § 154(a)(2)
`(2012 & Supp. III 2015) (stating patent term ends twenty (20) years from the
`date on which the application for the patent was filed in the United States,
`“or, if the application contains a specific reference to an earlier filed
`application or applications under section 120, 121, 365(c), or 386(c), from
`the date on which the earliest such application was filed”).
`
`
`10
`
`
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`IPR2017-00280
`Patent RE40,264 E
`
`
`application is a reissue of the ’776 patent, which issued May 15, 2001 from
`
`the ’163 application, which was filed September 10, 1998. Id. at [64].
`
`The ’163 application is a continuation-in-part of the following two
`
`applications: (1) U.S. Provisional Application No. 60/058,650 (“the ’650
`
`provisional application”), filed on September 11, 1997; and (2) U.S. Patent
`
`Application No. 08/567,224 (“the ’224 application”), filed on December 4,
`
`1995. Id. at [60], [63], 1:11–15.
`
`
`
`Petitioner contends that September 11, 1997 is the earliest possible
`
`priority date for the challenged claims, arguing that the ’224 application,
`
`filed on December 4, 1995, does not disclose the claimed subject matter.
`
`Pet. 9–11. Relying upon the testimony of its Declarant, Dr. John Bravman
`
`(Ex. 1006 “the Bravman Declaration”), Petitioner contends the ’224
`
`application fails to disclose changing the temperature of a substrate on a
`
`substrate holder from a first to a second substrate temperature, using a
`
`measured substrate temperature “within a preselected time interval” as
`
`required by independent claim 27, and a “substrate temperature control
`
`circuit effectuates the change from the first substrate temperature to the
`
`second substrate temperature within a preselected time period” as required
`
`by independent claim 51. Id. at 9–10 (citing Ex. 1006 ¶¶ 30–33).
`
`Consequently, Petitioner asserts that, because the ’224 application does not
`
`provide sufficient written description support for certain limitations required
`
`by independent claims 27 and 51, the challenged claims only are entitled to
`
`claim priority to the filing date of the ’650 provisional application (i.e.,
`
`September 11, 1997). See id. at 9–11. Patent Owner does not argue that the
`
`’264 patent is entitled to claim a priority date earlier than September 11,
`
`1997.
`
`11
`
`
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`IPR2017-00280
`Patent RE40,264 E
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`
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`On this record, we are persuaded by Petitioner’s argument that the
`
`’224 application does not provide sufficient written description support for
`
`the “within a preselected time interval” limitation recited in independent
`
`claim 27 or a “substrate temperature control circuit effectuates the change
`
`from the first substrate temperature to the second substrate temperature
`
`within a preselected time period” recited in independent claim 51, and
`
`therefore the challenged claims of the ’264 patent are not entitled to claim
`
`priority to the December 4, 1995 filing date of the ’224 application.
`
`As such, based on the this record, we agree with Petitioner that
`
`Kadomura, which was filed on February 21, 1997, and the remaining
`
`asserted references, each of which were filed before the December 4, 1995
`
`filing date of the ’224 application, qualify as prior art to the challenged
`
`claims of the ’264 patent.
`
`C. Asserted Obviousness of Claims 27, 29, 32, 34, 36, and 66 Based on
`the Combination of Kadomura and Matsumura
`
`
`
`Petitioner contends that claims 27, 29, 32, 34, 36, and 66 are
`
`unpatentable under § 103(a) as having been obvious over the combination of
`
`Kadomura and Matsumura. Pet. 21–38. Petitioner explains how this
`
`proffered combination purportedly teaches the subject matter of each
`
`challenged claim, and asserts that a person of ordinary skill in the art would
`
`have had reason to combine or modify Kadomura with the teachings from
`
`Matsumura. Id. Petitioner also relies upon the Bravman Declaration (Ex.
`
`1006) to support its positions.
`
`1. Overview of Kadomura
`
`Kadomura generally relates to a dry etching method used primarily for
`
`the production of semiconductor devices and, in particular, to a dry etching
`
`12
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`IPR2017-00280
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`method and apparatus that provides compatibility for anisotropic fabrication
`
`and high selectivity. Ex. 1005, 1:6–10. According to Kadomura, one
`
`objective of the disclosed dry etching method is to apply an etching
`
`treatment that includes a plurality of steps to a specimen within the same
`
`processing apparatus, wherein the temperature of the specimen is changed
`
`between etching in a first step and etching in a second step. Id. at 2:65–3:5.
`
`Because the disclosed dry etching method conducts each of the etching
`
`treatments in the same processing apparatus, the time for changing the
`
`specimen temperature between the steps may be shortened. Id. at 4:46–49.
`
`Moreover, by conducting the change of specimen temperature within a short
`
`period of time, dry etching treatment may be applied without deteriorating
`
`the throughput. Id. at 4:49–54. Kadomura discloses several examples of
`
`multi-temperature etch processes, including etching silicide and polysilicon
`
`at room temperature (20°C) in a first step, followed by etching polysilicon at
`
`-30°C in a second step. Id. at 6:18–7:7. After completing those two steps, a
`
`heater within substrate holder stage 12 brought the holder back up to 20ºC
`
`before the tool repeated the same two temperature etch process. Id. at 6:63–
`
`7:7, 7:31–47. Kadomura also discloses etching polysilicon at higher
`
`temperatures because “radical reaction is promoted by increasing the
`
`specimen temperature (50°C).” Id. at 10:28–35.
`
`In the third embodiment discussed in relation to Figures 3A–3C,
`
`Kadomura discloses a method of fabricating polysilicon on a SiO2 layer
`
`having a high step. Id. at 9:36–10:27. The main etching in the first step is
`
`applied at a low temperature (i.e., -30ºC), whereas the overetching in the
`
`second step is applied at a much higher temperature (i.e., 50ºC) within a
`
`short period of time of about fifty (50) seconds. Id. at 9:54– 62, 10:11–27.
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`13
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`IPR2017-00280
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`According to Kadomura, the change in temperature of specimen W is
`
`controlled by “the cooling means and the heater disposed to the stage 12.”
`
`Id. at 10:7–10. The functioning of the cooling means is controlled by
`
`thermometer 18, which is “connected for measuring the temperature of the
`
`specimen W.” Id. at 11:48–51, 12:36–47.
`
`2. Overview of Matsumura
`
`Matsumura generally relates to heat-processing a semiconductor
`
`wafer and, in particular, to controlling temperatures of the semiconductor
`
`wafer when it is heated or cooled. Ex. 1003, 1:8–13. According to
`
`Matsumura, one objective of the disclosed invention is to provide a “method
`
`of heat-processing semiconductor devices whereby temperatures of the
`
`semiconductor devices can be controlled at devices-heating and -cooling
`
`times so as to accurately control their thermal history curve.” Id. at 2:60–65.
`
`Matsumura discloses applying the method to plasma etching when it states
`
`that, although “the present invention has been applied to the adhesion and
`
`baking processes for semiconductor wafers in the above-described
`
`embodiments . . . , it can also be applied to any of the ion implantation,
`
`[chemical vapor deposition (“CVD”)], etching and ashing processes.” Id. at
`
`10:3–7. Figure 5A, reproduced below, is a schematic diagram of an
`
`embodiment for heat-processing a substrate (wafer W) on a substrate holder
`
`14
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`
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`IPR2017-00280
`Patent RE40,264 E
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`(wafer-stage 12, which includes upper plate 13 and conductive thin film 14)
`
`in chamber 11.
`
`
`
`As shown in Figure 5A above, adhesion unit 42 along with control system
`
`20 measures the temperature of thin film 14 deposited on the underside of
`
`upper plate 13 by using thermal sensor 25. Id. at 5:13–17, 5:32–47, 5:67–
`
`6:4, 6:45–50. Control system 20 sends signals (SM) to power supply circuit
`
`19 to heat semiconductor wafer W on upper plate 13 by conductive thin film
`
`14, and sends signals (SC) to cooling system 23 to control the amount of
`
`coolant supplied to jacket 22. Id. at 5:52–6:32, Figs. 5A, 5B. Inside the
`
`15
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`IPR2017-00280
`Patent RE40,264 E
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`control system is a “recipe,” such as that shown in Figure 9, reproduced
`
`below.
`
`
`
`Figure 9, shown above, depicts a recipe with a “thermal history curve”
`
`showing temperature as a function of time. Id. at 4:42–43. At a given time
`
`(or pulse), the control system measures the substrate holder temperature with
`
`thermal sensor 25, compares this measurement to that of the recipe shown in
`
`Figure 9, and either (1) sends a signal (SM) to power supply circuit 19 to
`
`heat the substrate (wafer W) (e.g., heating wafer W from 20ºC to 90ºC
`
`within 60 seconds); (2) sends a signal (SC) to cooling system 23 to cool the
`
`substrate by allowing jacket 22 arranged under stage 12 to exchange heat
`
`with thin film 14 (e.g., cooling wafer W from 140ºC to 20ºC within 60
`
`seconds); or (3) sends no signal and waits for the next measurement time
`
`(e.g., holding the temperature of wafer W at 140ºC for 30 seconds). Id. at
`
`5:52–6:32, Figs. 5A, 5B.
`
`16
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`IPR2017-00280
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`3. Analysis
`
`Petitioner contends that the combination of Kadomura and Matsumura
`
`teaches all of the elements of independent claim 27 and provide arguments
`
`setting forth were each of the limitations may be found. Pet. 21–38. For
`
`example, Petitioner contends that Kadomura teaches “heating a substrate
`
`holder to a first substrate holder temperature with a heat transfer device, the
`
`substrate holder having at least one temperature sensing unit” because
`
`Kadomura teaches raising a wafer’s temperature by heating the substrate
`
`holder (stage 12) to a desired temperature. Pet. 21 (citing Ex. 1005, 3:19–
`
`65). With respect to “the substrate holder having at least one temperature
`
`sensing unit” as recited in claim element 27[a], Petitioner contends that
`
`Kadomura’s control device 25 measures wafer temperature with
`
`thermometer 18 and adjusts the measured temperature to match a desired
`
`temperature. Id. at 22 (citing Ex. 1005 12:37–48; Fig. 4). Relying on the
`
`testimony of Dr. Bravman, Petitioner argues that it would have been obvious
`
`to one of ordinary skill in the art to measure the substrate holder temperature
`
`to confirm that the desired temperature was actually achieved. Id. at 22–23
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`(citing Ex. 1006 ¶ 119).
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`Petitioner also argues that, to the extent Kadomura does not expressly
`
`disclose a substrate temperature holder temperature sensor, Matsumura
`
`teaches this feature as it discloses a multi-temperature processing tool with a
`
`temperature sensor 25 embedded within the substrate holder 12. Id. at 23
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`(citing Ex. 1003 5:32–33, 7:20–22, Fig. 5A). Relying on the testimony of
`
`Dr. Bravman, Petitioner asserts that it would have been obvious to one of
`
`ordinary skill in the art to use the substrate holder temperature sensor of
`
`Matsumura to measure and set the temperature of the substrate holder in
`
`17
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`Patent RE40,264 E
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`Kadomura. Id. at 24 (citing Ex. 1006 ¶¶ 75–79, 120–21). Petitioner
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`contends that the combination would allow a chipmaker to directly gauge
`
`how well heat transferred between the holder and the wafer (and vice versa)
`
`and use the resulting holder-to-wafer temperature transfer and relationship
`
`data to adjust receipts and improve processing efficiency. Id. at 25–26
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`(citing Ex. 1005, 11:48–51; Ex. 1006 ¶¶ 75–79, 121). Petitioner also
`
`contends that use of substrate and substrate holder temperature sensors were
`
`generally known in the prior art, that relying on two sensors instead of one
`
`would result in a more accurate understanding of processing temperatures,
`
`and that more comprehensive temperature measurements would facilitate
`
`analysis of how to accelerate temperature changes and increase throughput.
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`Id. at 26 (citing Ex. 1005, 3:19–22, 5:18–26; Ex. 1006 79, 121; Ex. 1008,
`
`321, Fig. 6).
`
`With respect to changing from a first substrate temperature to a
`
`second substrate temperature “using a measured substrate temperature,
`
`within a preselected time interval for processing,” Petitioner contends that
`
`Kadomura in combination with Matsumura teaches or suggests this
`
`limitation. Pet. 29–34. Petitioner argues that Kadomura teaches a chiller
`
`and electrostatic chuck with a heater to change wafer temperature, that
`
`thermometer 18 measures the wafer temperature, and that control device 25
`
`brings the temperature to the desired value and adjusts the “detected
`
`temperature” to match the “predetermined temperature.” Id. at 29 (citing
`
`Ex. 1005, 3:34–36, 6:30–35, 6:52–55, 8:17–23, 10:4–6, 11:48–59, 12:37–48,
`
`Fig. 4). Petitioner turns to Matsumura’s temperature control system that
`
`uses “predetermined recipes” to heat or cool an object over a predetermined
`
`period of time to teach changing from a first substrate temperature to a
`
`18
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`second substrate temperature “within a preselected time interval for
`
`processing.” Id. at 30–31 (citing Ex. 1003, 3:1–7, 5:60–63). For example,
`
`Petitioner argues that Figures 8 and 9 of Matsumura show predetermined
`
`recipes with precise processing times and temperatures and temperature
`
`change times. Id. at 32 (citing Ex. 1003, Figs. 8, 9, 8:4–12, 8:56–68).
`
`Relying on the testimony of Dr. Bravman, Petitioner asserts that use
`
`of predetermined recipes and programmable control circuits (e.g., CPUs) in
`
`semiconductor manufacturing was well known and wide spread and that it
`
`would have been obvious to one of ordinary skill in the art to use
`
`Matsumura’s predetermined recipe approach and programmable CPU in
`
`Kadomura’s processing tool in order to increase accuracy in temperature
`
`control and greater process control and reliability. See, e.g., id. at 33–34
`
`(citing Ex. 1006 ¶¶ 70–71, 130–35).
`
`
`
`We are persuaded, based on the current record, that Petitioner’s
`
`discussions of the disclosures in Kadomura and Matsumura and the
`
`explanations in the Bravman Declaration are sufficient to establish a
`
`reasonable likelihood that Petitioner would prevail in demonstrating that
`
`claim 27 would have been obvious over the combination of Kadomura and
`
`Matsumura.
`
` We have considered Patent Owner’s arguments and do not find them
`
`persuasive on this record. For example, Patent Owner argues that neither
`
`Kadomura nor Matsumura individually teach changing from a first substrate
`
`temperature to a second substrate temperature within a “preselected time
`
`interval for processing” as required by independent claim 27[e]. Prelim.
`
`Resp. 3. Specifically, Patent Owner argues that “the time interval in
`
`Kadomura is not selected at all and is not within an interval for processing.”
`
`19
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`Id. at 4, 7. Rather, Patent Owner argues that the time period is dictated by
`
`the period required to evacuate the first gas from the vacuum chamber and
`
`introduce and stabilize the flow of the second gas, during which period no
`
`processing is occurring. Id. (citing Ex. 1005, 6:55–65, 7:19–30, 8:43–50).
`
`Patent Owner also argues that Matsumura does not teach “etching a
`
`substrate” and therefore does not teach the “for processing” limitation of
`
`claim element 27[e] which is “etching a substrate.” Id. at 7–8.
`
`On this record, we are not persuaded by Patent Owner’s individual
`
`attacks on Kadomura and Matsumura. It is well-settled that “non-
`
`obviousness [cannot be established] by attacking references individually,”
`
`when, as here, the asserted ground of obviousness is based upon the
`
`combined teachings of Kadomura and Matsumura. In re Keller, 642 F.2d
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`413, 426 (CCPA 1981). Instead, the test is what the combined teachings of
`
`these references would have taught or suggested to one with ordinary skill in
`
`the art. In re Young, 927 F.2d 588, 591 (Fed. Cir. 1991). In this case,
`
`Petitioner’s asserted ground of obviousness does not rely solely upon
`
`Kadomura to teach a preselected time interval or period. Rather, Petitioner
`
`turns to Kadomura’s disclosure of etching silicon dioxide and polysilicon at
`
`room temperature (20°C) in a first step, followed by etching polysilicon at
`
`–30°C in a second step, and that the wafer temperature changed from 20°C
`
`to –30°C within about 30 seconds. See, e.g., Pet. 29–30. We understand
`
`Petitioner to argue that using Matsumura’s predetermined recipes that
`
`specify precise processing times and temperatures as well as precise
`
`temperature changes in Kadomura’s dry etching apparatus would result in an
`
`apparatus that changes from a first substrate temperature to a second
`
`substrate temperature over a preselected time interval or period. Pet. 30–34.
`
`20
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`Patent Owner also argues that Petitioner has not provided a motivation
`
`to combine the teachings of Kadomura and Matsumura. Prelim. Resp. 12–
`
`14. Specifically, Patent Owner argues that there would be no benefit
`
`achieved by combining the teachings of Kadomura with Matsumura. Patent
`
`Owner argues the primary object of Kadomura is “to attain high selectivity
`
`and accuracy” while “actually putting the low temperature etching technique
`
`into practical use” and that this object is achieved by changing the
`
`temperature between the two steps. Id. at 12 (citing Ex. 1005, 2:58–3:5,
`
`6:55–62). Patent Owner argues that Petitioner does not articulate a reason
`
`why one of ordinary skill in the art would incorporate Matsumura’s baking
`
`recipes in Kadomura’s tool, particularly as no time would be saved between
`
`the etching steps. Id. at 12 citing (Ex. 1005, 6:55–62, 8:43–50, 10:11–16).
`
`Patent Owner also argues that Petitioner’s reliance on Matsumura’s
`
`temperature recipes in the adhesion and baking unit for applying a uniform
`
`resist on a substrate is impermissible hindsight. Id. at 13–14.
`
`On this record, we are persuaded that Petitioner has articulated
`
`sufficient reasons to combine the references. See, e.g., Pet. 33–34. For
`
`example, Petitioner contends that using predetermined recipes and
`
`programmable control circuits in semiconductor manufacturing was well
`
`known and that programming selected times and temperatures into tools
`
`before processing allowed chipmakers to control their processes, to make the
`
`processes predictable and reliable, and to maximize efficiency. Pet. 33
`
`(citing Ex. 1006 ¶¶ 70, 71, 130). Petitioner further argues that the use of
`
`Matsumura’s predetermined recipe approach and programmable CPU in
`
`Kadomura’s tool would have been straightforward, as Kadomura already
`
`used control device 25, similar to Matsumura’s control system 20, to manage
`
`21
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`and change temperature rapidly. Id. (citing Ex. 1005, 6:52–55; Ex. 1006
`
`¶ 131, 133–135). Petitioner contends that a person skilled in the art would
`
`have been motivated to incorporate Matsumura’s recipes and control system
`
`into Kamoura’s tool to provide for increased accuracy in temperature control
`
`and greater process control and reliability. Id. at 33–34 (citing Ex. 1006
`
`¶¶ 133–135; Ex. 1003, 10:22–29),
`
`Consequently, we are persuaded, based on the current record at this
`
`stage of the proceeding, that Petitioner has established a reasonable
`
`likelihood that claim 27 would have been unpatentable over Kadomura and
`
`Matsumura.
`
`We have also considered Petitioner’s arguments and evidence with
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`respect to dependent claims 29, 32, 34, 36, and 66, which depend from claim
`
`27. Patent Owner presents no arguments directed specifically to these
`
`claims. We are persuaded, on the current record, that Petitioner has
`
`demonstrated a reasonable likelihood that it would prevail as to those claims
`
`as well. See, e.g., Pet. 36–38
`
`D. Asserted Obviousness of Claims 31 and 35 over
`Kadomura, Matsumura, & Kikuchi
`
`Petitioner contends that claims 31 and 35, which depend from claim
`
`27, would have been obvious under 35 U.S.C. § 103(a) over the combined
`
`teachings of Kadomura, Matsumura, and Kikuchi. Pet. 39–42. Petitioner
`
`explains how this proffered combination
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