Trials@uspto.gov
`571-272-7822
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` Paper 30
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` Entered: January 31, 2019
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`MICRON TECHNOLOGY, INC. and
`SAMSUNG ELECTRONICS COMPANY, LTD.1,
`Petitioner,
`
`v.
`
`DANIEL L. FLAMM,
`Patent Owner.
`____________
`
`Case IPR2017-00280
`Patent RE40,264 E
`____________
`
`
`Before CHRISTOPHER L. CRUMBLEY, JO-ANNE M. KOKOSKI, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`1 Samsung Electronics Company, Ltd. was joined as a party to this
`proceeding via a Motion for Joinder in IPR2017-01750.
`
`
`571-272-7822
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`
`
`
`
` Paper 30
`
`
`
` Entered: January 31, 2019
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`MICRON TECHNOLOGY, INC. and
`SAMSUNG ELECTRONICS COMPANY, LTD.1,
`Petitioner,
`
`v.
`
`DANIEL L. FLAMM,
`Patent Owner.
`____________
`
`Case IPR2017-00280
`Patent RE40,264 E
`____________
`
`
`Before CHRISTOPHER L. CRUMBLEY, JO-ANNE M. KOKOSKI, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`1 Samsung Electronics Company, Ltd. was joined as a party to this
`proceeding via a Motion for Joinder in IPR2017-01750.
`
`
`
`IPR2017-00280
`Patent RE40,264 E
`
`
`I. INTRODUCTION
`
`In this inter partes review, instituted pursuant to 35 U.S.C. § 314,
`
`Intel Corporation, GLOBALFOUNDRIES U.S., Inc., Micron Technology,
`
`Inc., and Samsung Electronics Company, Ltd., (collectively “Petitioner”)
`
`challenge the patentability of claims 27–36, 51–55, 66, 68, and 69 of U.S.
`
`Patent No. RE40,264 E (Ex. 1001, “the ’264 patent”), owned by Daniel L.
`
`Flamm (“Patent Owner”).
`
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`
`Decision, issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73,
`
`addresses issues and arguments raised during trial. For the reasons discussed
`
`below, we determine that Petitioner has shown by a preponderance of the
`
`evidence that claims 27–36, 51–55, 66, 68, and 69 of the ’264 patent are
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`unpatentable.
`
`A. Procedural History
`
`On December 2, 2016, Intel Corporation, GLOBALFOUNDRIES
`
`U.S., Inc., and Micron Technology, Inc. (collectively, “Initial Petitioners”)
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`filed a Petition requesting an inter partes review of claims 27–36, 51–55, 66,
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`68, and 69 of the ’264 patent. Paper 2 (“Pet.”). Patent Owner filed a
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`Preliminary Response. Paper 8. On June 13, 2017, we instituted an inter
`
`partes review of the challenged claims. Paper 9 (“Decision on Institution” or
`
`“Dec. on Inst.”). Subsequent to institution, Samsung Electronics Company,
`
`Ltd. (“Samsung”) filed a petition and motion for joinder with the instant
`
`proceeding. Samsung Electronics Company, Ltd. v. Daniel L. Flamm, Case
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`IPR2017-01750, Papers 1, 3. On September 15, 2017, we granted
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`2
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`IPR2017-00280
`Patent RE40,264 E
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`Samsung’s petition and motion for joinder, joining Samsung as a petitioner
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`in this inter partes review. Paper 12, 7.
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`Thereafter, Patent Owner filed a Patent Owner Response (Paper 13,
`
`“PO Resp.”) and Petitioner filed a Reply (Paper 14, “Reply”). In support of
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`their respective arguments, Petitioner relies upon the declaration testimony
`
`of Dr. John Bravman (Exs. 1006 and 1023) and Patent Owner relies upon the
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`declaration testimony of Dr. Daniel L. Flamm2 (Ex. 2001).
`
`Oral hearing was requested by both parties. Papers 15, 16. A
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`consolidated oral hearing for this proceeding and Cases IPR2017-00279,
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`IPR2017-00281, and IPR2017-000282, involving the same parties and the
`
`’264 patent, and Cases IPR2017-00391, IPR2017-00392, and IPR2017-
`
`00406, involving the same parties and unrelated patents, was held on March
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`7, 2018. A transcript of the consolidated hearing has been entered into the
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`record. Paper 28 (“Tr.”).
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`B. Related Proceedings
`
`Petitioner reports that the Patent Owner has asserted the ’264 patent in
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`five proceedings in the Northern District of California (Case Nos. 5:16-cv-
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`01578-BLF, 5:16-cv-1579-BLF, 5:16-cv-1580-BLF, 5:16-cv-1581-BLF, and
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`5:16-cv-02252-BLF) and that Lam Research Corporation has filed a
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`declaratory judgment action against Patent Owner on the ’264 patent, also in
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`the Northern District of California (Case No. 5:15-cv-01277-BLF). Pet. 2.
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`
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`2 Daniel L. Flamm is both the Patent Owner and Patent Owner’s declarant in
`this proceeding.
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`3
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`IPR2017-00280
`Patent RE40,264 E
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`Petitioner also challenges certain claims of the ’264 patent in
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`IPR2017-00279, IPR2017-00281, and IPR2017-00282, which were filed
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`concurrently with the Petition in this proceeding. The parties also identified
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`nine other IPR petitions for review of the ’264 patent, filed by Lam Research
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`Corporation or Samsung, none of which are currently pending. See Pet. 2;
`
`Prelim. Resp. 1–2 (identifying IPR2015-01759 (institution denied);
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`IPR2015-01764 (terminated-settled); IPR2015-01766 (institution denied);
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`IPR2015-01768 (terminated-settled); IPR2016-00468 (institution denied);
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`IPR2016-00469 (institution denied); and IPR2016-00470 (institution
`
`denied); IPR2016-01510 (institution denied) and; IPR2016-01512 (Final
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`Written Decision – challenged claims unpatentable)).
`
`C. The ’264 Patent
`
`The ’264 patent, titled “Multi-Temperature Processing,” relates
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`generally to methods and systems for controlling the heating and cooling
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`time of a substrate (e.g., wafer) during plasma processing in a single
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`processing chamber. See, e.g., Ex. 1001, 1:18–21. A “plasma etching
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`apparatus according to the present invention” is shown in Figure 1 of
`
`the ’264 patent, reproduced below. Id. at 2:66–67.
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`4
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`Figure 1 above illustrates a plasma etching apparatus having chamber
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`12 and a substrate holder (product support chuck or pedestal 18) for holding
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`a substrate (product 28, such as a wafer to be etched). Id. at 3:24–25, 3:32–
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`33, 3:40–42. The substrate holder, which is thermally coupled to the
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`substrate, “can rapidly change its temperature.” Id. at 3:51–55.
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`One embodiment of a temperature control system according to the
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`invention is shown in Figure 7 below. Id. at 3:11–13, 15:65–67.
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`5
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`Patent RE40,264 E
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`Figure 7, shown above, depicts a temperature control system having
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`substrate holder (also called “wafer chuck” or “wafer holder”) 701, heater
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`705, heat transfer fluid reservoir 713, and heat exchanger 723. Id. at 15:65–
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`16:8. Fluid is “pumped from the reservoir through the heating unit, which
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`selectively sets the temperature of the fluid.” Id. at 16:9–11. The fluid
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`“transfers energy in the form of heat to the wafer holder to a desirable
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`temperature.” Id. at 16:14–16. In another embodiment, the fluid can also be
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`cooled using heat exchanger 723. Id. at 16:20–21. In a specific embodiment,
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`“system 700 operates in a manner to program a process temperature of the
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`substrate holder.” Id. at 16:28–30. An electrical heater heats the fluid to a
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`desired temperature, which is “determined by comparing the desired wafer
`
`or wafer chuck set point temperature to a measured wafer or wafer chuck
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`temperature.” Id. at 16:36–41.
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`A microprocessor-based system can be used to control the
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`temperature of the substrate holder by selectively turning elements of the
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`system (e.g., heater, fluid reservoir) on or off. Id. at 17:1–9. For example, if
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`the measured temperature of the wafer or chuck is below the desired
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`temperature “a suitable control algorithm such as a proportional controller or
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`a proportional-integral-derivative (i.e., ‘PID’) controller algorithm increases
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`the temperature by supplying more power to the heater.” Id. at 16:41–46.
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`“The heat exchanger, fluid flow rate, coolant-side fluid temperature, heater
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`power, chuck, etc., should be designed using conventional means to permit
`
`the heater to bring the fluid to a setpoint temperature and bring the
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`temperature of the chuck and wafer to predetermined temperatures within
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`6
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`Patent RE40,264 E
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`specified time intervals and within specified uniformity limits.” Id. at 16:60–
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`67.
`
`The ’264 patent states that conventional processing of resist layers,
`
`which is performed at low temperatures in order to help prevent rupturing of
`
`cross-linked layers and contaminative particulate matter, requires excessive
`
`time and lower throughput. Id. at 2:17–26. The ’264 patent states that the
`
`present invention overcomes these disadvantages by removing the ion
`
`implanted layer at a lower temperature followed by rapidly removing a
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`majority of resist at a higher temperature. See id. at 2:26–30. For example, a
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`“sequence of temperature changes” may be employed to avoid “various
`
`types of processing damage to the device and material layers.” Id. at 2:34–
`
`37. Figure 10, shown below, illustrates a simplified process according to the
`
`invention. Id. at 18:58–59.
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`7
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`
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`The process shown in Figure 10 above plots changes in temperature
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`against processing time. See id., Fig. 10; see also id. at 18:58–19:64
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`(providing details of the process shown in Figure 10). For example, during
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`the isotropic breakthrough step (time A through BB), an SF6 plasma is used
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`to remove native oxide at a low temperature, such as room temperature. Id.
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`at 18:63–66, Fig. 10. At the end of this step, at time BB, the control program
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`increases within several seconds to a higher steady state value at time B. Id.
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`at 19:8–10. The tungsten silicide layer is then etched at a constant
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`temperature until the layer is breached. Id. at 19:10–15. At point D, the
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`wafer temperature is gradually reduced in order to achieve a slower and
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`more anisotropic polysilicon etching step. Id. at 19:36–28.
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`8
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`IPR2017-00280
`Patent RE40,264 E
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`
`D. Illustrative Claims
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`Of the claims challenged by Petitioner, only claims 27 and 51 are
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`independent. Claims 28–36 and 66 depend directly from independent claim
`
`27. Claims 52–55, 68, and 69 depend directly from claim 51. Independent
`
`claims 27 and 51 are reproduced below, with bracketed material and
`
`formatting added:
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`27. A method of etching a substrate in the manufacture of a
`device, the method comprising:
`
`[a] heating a substrate holder to a first substrate holder
`temperature with a heat transfer device, the substrate
`holder having at least one temperature sensing unit;
`
`[b] placing a substrate having a film thereon on a substrate
`holder in a chamber,
`
`[c] etching a first portion of the film at a selected first
`substrate temperature; and
`
`[d] etching a second portion of the film at a selected second
`substrate temperature, the selected second substrate
`temperature being different from the selected first
`substrate temperature;
`
`[e] wherein substrate temperature is changed from the
`selected first substrate temperature to the selected
`second substrate temperature, using a measured
`substrate temperature, within a preselected time
`interval for processing,
`
`and at least the first substrate temperature or the second
`substrate temperature, in single or in combination, is
`above room temperature.
`
`[f]
`
`
`
`51. A method of processing a substrate in the manufacture
`of a device, the method comprising:
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`[a] placing a substrate having a film thereon on a substrate
`holder in a processing chamber;
`
`[b]
`
`the processing chamber comprising the substrate
`holder, a substrate control circuit operable to adjust the
`substrate temperature, a substrate holder temperature
`sensor, and a substrate holder control circuit operable
`to maintain the substrate holder temperature;
`
`[c] performing the first etching of a first portion of the film at
`a selected first substrate temperature;
`
`[d] performing a second etching of a second portion of the
`film at a selected second substrate temperature, the
`second temperature being different from the first
`temperature;
`
`[e] wherein at least one of the film portions is etched while
`heat is being transferred to the substrate holder with the
`substrate holder control circuit; and
`
`[f]
`
`the substrate temperature control circuit effectuates the
`change from the first substrate temperature to the
`second substrate temperature within a preselected time
`period.
`
`E. Instituted Grounds
`
`We instituted an inter partes review of claims 27–36, 51–55, 66, 68,
`
`and 69 on the following grounds of unpatentability:
`
`(1) Whether claims 27, 29, 32, 34, 36, and 66 are unpatentable under
`
`§ 103(a) over the combination of Kadomura3 and Matsumura4;
`
`
`
`3 U.S. Patent No. 6,063,710, filed Feb. 21, 1997, issued May 16, 2000
`(Ex. 1005, “Kadomura”).
`4 U.S. Patent No. 5,151,871, issued Sept. 29, 1992 (Ex. 1003, “Matsumura”).
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`(2) Whether claims 31 and 55 are unpatentable under § 103(a) over
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`the combination of Kadomura, Matsumura, and Kikuchi5;
`
`(3) Whether claims 28, 30, 33, 51–55, 68, and 69 are unpatentable
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`under § 103(a) over the combination of Kadomura, Matsumura, and Muller6;
`
`(4) Whether claims 27, 28, 31–36, 51–54, 66, 68, and 69 are
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`unpatentable under § 103(a) over the combination of Kikuchi and
`
`Matsumura; and
`
`(5) Whether claims 29, 30, 34, 55, and 68 are unpatentable under
`
`§ 103(a) over the combination of Kikuchi, Matsumura, and Muller.
`
`II. DISCUSSION
`
`A. Principles of Law
`
`To prevail in challenging Patent Owner’s claims, Petitioner must
`
`demonstrate by a preponderance of the evidence that the claims are
`
`unpatentable. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d). A claim is
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`unpatentable under 35 U.S.C. § 103(a) if the differences between the
`
`claimed subject matter and the prior art are such that the subject matter, as a
`
`whole, would have been obvious at the time of the invention to a person
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`having ordinary skill in the art. KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398,
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`406 (2007). The question of obviousness is resolved on the basis of
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`underlying factual determinations including: (1) the scope and content of the
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`prior art; (2) any differences between the claimed subject matter and the
`
`prior art; (3) the level of ordinary skill in the art; and (4) objective evidence
`
`
`
`5 U.S. Patent No. 5,226,056, issued July 6, 1993 (Ex. 1004, “Kikuchi”).
`6 U.S. Patent No. 5,605,600, issued Feb. 25, 1997 (Ex. 1002, “Muller”).
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`IPR2017-00280
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`of nonobviousness, i.e., secondary considerations.7 See Graham v. John
`
`Deere Co., 383 U.S. 1, 17–18 (1966). The level of ordinary skill in the art
`
`may be reflected by the prior art of record. See Okajima v. Bourdeau, 261
`
`F.3d 1350, 1355 (Fed. Cir. 2001).
`
`B. Level of Ordinary Skill in the Art
`
`Citing its declarant, Petitioner contends that a person of ordinary skill
`
`in the art at the relevant time (a “POSITA”) would have had (i) a Bachelor’s
`
`degree in chemical engineering, materials science engineering, electrical
`
`engineering, physics, chemistry, or a similar field, and three or four years of
`
`work experience in semiconductor manufacturing or related fields; or (ii) a
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`Master’s degree in chemical engineering, materials science engineering,
`
`electrical engineering, physics, chemistry, or a similar field, and two or three
`
`years of work experience in semiconductor manufacturing or related fields;
`
`or (iii) a Ph.D. in chemical engineering, materials science engineering,
`
`electrical engineering, physics, chemistry, or a similar field. Pet. 20–21
`
`(citing Ex. 1006 ¶¶ 20–22).
`
`Patent Owner does not contest Petitioner’s description of the level of
`
`ordinary skill in its Response. Based on our review of the ’264 patent, the
`
`cited prior art, and the testimony of the parties’ declarants, we agree with
`
`Petitioner’s assessment of the level of ordinary skill in the art and apply it
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`for purposes of this Decision. See Okajima, 261 F.3d at 1355 (explaining
`
`that specific findings regarding ordinary skill level are not required “where
`
`
`
`7 The record does not contain evidence or argument of objective evidence of
`non-obviousness.
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`the prior art itself reflects an appropriate level and a need for testimony is
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`not shown”).
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`C. Claim Construction
`
`The ’264 patent has expired.8 For claims of an expired patent, the
`
`Board’s claim interpretation is similar to that of a district court. See In re
`
`Rambus, Inc., 694 F.3d 42, 46 (Fed. Cir. 2012). Claim terms are given their
`
`ordinary and customary meaning as would be understood by a person of
`
`ordinary skill in the art at the time of the invention, and in the context of the
`
`entire patent disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257
`
`(Fed. Cir. 2007). Only those terms in controversy need to be construed, and
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`only to the extent necessary to resolve the controversy. See Vivid Techs., Inc.
`
`v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`
`For purposes of our Decision on Institution, we determined that none
`
`of the claims terms requires an explicit construction. Dec. on Inst. 10.
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`During the instituted trial, neither party disagreed with this assessment, and
`
`
`
`8 Neither party disputes that the ’264 patent has expired. The earliest patent
`application referenced for the benefit of priority under 35 U.S.C. § 120 for
`the ’264 patent was filed on December 4, 1995, and the patent has no term
`extensions. The term of the ’264 patent, therefore, expired no later than
`December 4, 2015. See 35 U.S.C. § 154(a)(2) (2012 & Supp. III 2015)
`(stating that the term of a patent grant ends twenty (20) years from the date
`on which the application for the patent was filed in the United States, “or, if
`the application contains a specific reference to an earlier filed application or
`applications under section 120, 121, 365(c), or 386(c), from the date on
`which the earliest such application was filed”).
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`we again see no need to provide an express construction for any of the terms
`
`in the challenged claims.
`
`D. Priority Date for the Challenged Claims of the ’264 Patent
`
`The ’264 patent is a reissue of U.S. Patent No. 6,231,776 B1, which
`
`issued from U.S. Patent Application No. 09/151,163 (“the ’163 application”)
`
`filed on September 10, 1998. Ex. 1001, [64]. The ’163 application claims
`
`priority to both (1) U.S. Provisional Application No. 60/058,650 (“the ’650
`
`provisional application”), filed on September 11, 1997 and (2) U.S. Patent
`
`Application No. 08/567,224 (“the ’224 application”), filed on December 4,
`
`1995. Id. at [60], [63], [64], 1:11–15.
`
`Petitioner contends that the challenged claims of the ’264 patent are
`
`not entitled to claim priority to a filing date any earlier than the
`
`September 11, 1997, filing date of the ’650 provisional application, and,
`
`therefore, each of the asserted references qualifies as prior art to the
`
`challenged claims. See Pet. 9–12, 16, 18. Specifically, Petitioner contends
`
`that the ’264 patent is not entitled to claim priority to the December 4, 1995,
`
`filing date of the ’224 application because the ’224 application fails to
`
`disclose changing the temperature of a substrate on a substrate holder from a
`
`first to a second substrate temperature using a measured substrate
`
`temperature “within a preselected time interval” as required by independent
`
`claim 27, and a “substrate temperature control circuit effectuates the change
`
`from the first substrate temperature to the second substrate temperature
`
`within a preselected time period” as required by independent claim 51. See
`
`id. at 9–10 (citing Ex. 1006 ¶¶ 30–33).
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`Patent Owner has not introduced any evidence or argument that
`
`the ’224 application provides written description support for the independent
`
`claims. See generally PO Resp. Nor does Patent Owner contend that any of
`
`the asserted references are not prior art to the ’264 patent. See id. Evaluating
`
`Petitioner’s unchallenged arguments, we determine that the challenged
`
`claims of the ’264 patent are not entitled to claim priority to the December 4,
`
`1995, filing date of the ’224 application. As a consequence, we find that
`
`Kadomura, which was filed on February 21, 1997, and the remaining
`
`asserted references, each of which issued before the September 11, 1997,
`
`filing date of the ’650 provisional application, qualify as prior art to the
`
`challenged claims of the ’264 patent. See Pet. at 11–12, 16, 18 (stating each
`
`of the references was either filed or issued before September 11, 1997); see
`
`also Tech. Licensing Corp. v. Videotek, Inc., 545 F.3d 1316, 1327 (Fed. Cir.
`
`2008) (stating that the patent owner has the burden of production to make a
`
`claim of priority that the challenged claims are entitled to a filing date prior
`
`to the date of the alleged prior art).
`
`E. Asserted Art
`
`1. Kadomura
`
`Kadomura, titled “Method and Apparatus for Dry Etching with
`
`Temperature Control,” discloses, inter alia, a multi-temperature process for
`
`etching portions of a semiconductor wafer. Ex. 1005 at [54], [57]. The
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`etching tool of Kadomura shown in Figure 4 has a wafer stage for holding
`
`the wafer/substrate during processing, a thermometer for measuring wafer
`
`temperature, and a control device, having a PID controller, for controlling
`
`the temperature of wafer based on temperature measurements from the
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`thermometer. See id. at 11:36–59, 12:37–48, Fig. 4. Kadomura adjusts the
`
`wafer temperature by adjusting the temperature of wafer stage 12, using a
`
`heater or chiller 17. See id. at 10:7–10 (stating the change in temperature of
`
`specimen W is controlled by “the cooling means and the heater disposed to
`
`the stage 12”); see also id. at 12:37–38 (the “cooling degree for the
`
`specimen [] is controlled by the flow rate of the coolant supplied from the
`
`chiller”). The temperature sensed by thermometer 18 is detected by a
`
`feedback control device (feedback control means) 25 comprising a
`
`[proportional-integral-derivative] PID controller. Id. at 12:39–43. Kadomura
`
`explains that feedback control device 25 controls the cryogenic valve “to
`
`obtain a gas coolant flow rate previously determined by experiment or
`
`calculation based on the difference between the detected temperature and the
`
`predetermined temperature for the specimen.” Id. at 12:43–49.
`
`Kadomura discloses several examples of multi-temperature etch
`
`processes. For example, one process includes a first step of etching silicide
`
`and polysilicon at room temperature (20°C) and a second step of etching
`
`polysilicon at a lower temperature (-30°C). See id. at 6:18–7:7; Figs. 1A–1C.
`
`In between these etching steps, gases remaining in the diffusion chamber are
`
`exhausted and the etching gas used in the second step is introduced; the gas
`
`is stabilized and the inside of the diffusion chamber is controlled to a
`
`constant pressure. See id. at 6:36–44. During “a series of such operations,
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`that is directly after the completion of the etching of the first step,” gas
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`coolant at -140°C from the chiller is supplied to the wafer stage to rapidly
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`cool the wafer. Id. at 6:44–51. The temperature of the wafer reaches -30 ºC
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`“within a short period of time of about 30 sec by such rapid cooling.” Id. at
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`6:52–55.
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`After completing these two steps, a heater within substrate holder
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`stage 12 returns the wafer specimen temperature back up to 20 ºC. See id. at
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`7:31–47. The tool then repeats the same two-temperature etch process. See
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`id. at 6:63–7:7, 7:31–47.
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`In another embodiment, the first etching step occurs at a low
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`temperature (i.e., -30ºC) and the second etching step is applied at a much
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`higher temperature (i.e., 50ºC). See id. at 9:54–10:27. A control mechanism
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`for the cooling means and the heater disposed to the wafer stage are
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`controlled to rapidly heat the specimen W between the etching steps. See id.
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`at 10:7–10. The temperature of the wafer reaches 50ºC “within a short
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`period of time of about fifty (50) seconds.” Id. at 10:11–27.
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`2. Matsumura
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`Matsumura generally relates to heat-processing semiconductor wafers
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`and, in particular, to controlling the temperature of a semiconductor wafer
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`during processing. See Ex. 1003, 1:8–13; see also id. at 2:60–65 (stating one
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`objective is to provide a “simpler method of heat-processing semiconductor
`
`devices whereby temperatures of the semiconductor devices can be
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`controlled at devices-heating and -cooling times so as to accurately control
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`their thermal history curve”).
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`Matsumura’s temperature control system uses a central processing
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`unit (“CPU”) having a PID controller that stores “as a predetermined recipe,
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`information showing a time-temperature relationship and applicable for
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`either heating [a wafer] to a predetermined temperature for a predetermined
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`period of time or cooling the [wafer] from a predetermined temperature over
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`a predetermined period of time.” See id. at 3:1–7, 5:64–6:6, 8:56–62; see
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`also id. at [57] (stating a “control system controls either the heating of the
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`wafer or the cooling thereof, or both, in accordance with the detected
`
`temperature signal and the [stored] information”).
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`An example of a predetermined recipe is shown in Figure 9 below.
`
`See id. at 8:56–57.
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`
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`Figure 9, shown above, is a diagram showing a “recipe relating to a thermal
`
`history curve of a wafer-stage,” showing temperature as a function of time.
`
`See id. at 4:42–43; see also id. at 8:56–68 (stating “Points P10 to P19 shown
`
`in figure 9 are set in the recipe to surely reproduce the thermal history curve
`
`of the wafer”). The information “relating to temperatures and times at these
`
`points P10 to P19 is inputted as a command temperature table to the CPU.”
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`Id. at 8:59–62.
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`Figure 5A, reproduced below, is a schematic diagram of an adhesion
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`unit included in a resist processing system of Matsumura that includes wafer
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`stage 12 for heating and cooling wafer W in accordance with recipes
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`inputted into a CPU. See id. at 4:28–29, 5:13–17, 6:6–9.
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`
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`Figure 5A, reproduced above, depicts adhesion unit 42 having wafer-stage
`
`12 that can heat and cool the semiconductor wafers (e.g., wafer W). Id. at
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`5:14–16. Recipes, including heating and other conditions, are inputted to the
`
`CPU by keyboard 20a. Id. at 6:6–9. Thermometer 24, which has thermal
`
`sensor attached to thin film 14, is attached to a control system 20. See id. at
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`5:57–6:4. Based on the recipe and temperature detecting signal, control
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`system 20 controls the amount of coolant supplied from the cooling system
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`to cooling jacket 22 under stage 12 and the current applied to conductive
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`thin film 14 to raise the temperature of the wafer. Id. at 5:64–6:61.
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`Matsumura states that, although “the present invention has been
`
`applied to the adhesion and baking processes for semiconductor wafers in
`
`the above-described embodiments . . . , it can also be applied to any of the
`
`ion implantation, [chemical vapor deposition (“CVD”)], etching and ashing
`
`processes.” Id. at 10:3–7.
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`3. Muller
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`Muller is directed to methods of shaping etch profiles by controlling
`
`wafer temperature using an electrostatic chuck and coolant circulating
`
`through a cathode and by changing the pressure of the gas filled in the gaps
`
`between the wafer and the cathode. Ex. 1002 at [54], Abstract, 1:7–12, 1:44–
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`64, 4:51–5:25. Figure 4 of Muller, which depicts an example of an apparatus
`
`used to accomplish the multi-temperature etching methods, is reproduced
`
`below.
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`
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`Figure 4 depicts wafer 104, electrostatic chuck 105, cathode 106, and gas
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`filled gap 110 between cathode 106 and wafer 104.Id. at 4:33–54.
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`Muller teaches that the change in taper angle of etched trenches
`
`correlates with increasing wafer temperature during the etching processes.
`
`Ex. 1002, 3:33–66, Figs. 1, 2. Muller explains that changing pressure of the
`
`gas filled in the gaps between the wafer and cathode, which can be
`
`accomplished in a very short period of time, results in an immediate effect
`
`on wafer temperature. Id. For example, wafer temperature can be increased
`
`by approximately 50ºC over a time of “several seconds” during etching. Id.
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`at 4:64–5:25, 5:41–48.
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`In one example, Muller teaches performing an initial etch at either
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`125ºC or 145ºC. Id. at 3:45–52, 3:56–66. The two etching temperature
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`examples correspond to two different coolant temperatures. For example,
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`use of a cathode coolant at 10ºC results in a wafer temperature of
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`approximately 125°C, while use of a cathode coolant at 30ºC results in a
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`wafer temperature of approximately 145ºC. Id. at 3:45–52. Figure 3 below
`
`shows the wafer temperature at the two cathode coolant temperatures as a
`
`function of time.
`
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`Figure 3 depicts a graph illustrating the change in wafer temperature for
`
`various coolant temperatures as a function of etch time.
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`In another example of an etching process, the gas-filled gap is
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`pressurized for a first time period and then the pressure in the gap is rapidly
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`changed to a second pressure for a second period of time. Id. at 4:64–5:3.
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`Then, the gas pressure underneath the chuck is changed to increase wafer
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`temperature by 50ºC in “several seconds” during etching. Id. at 4:64–5:25,
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`5:41–48. In this example, using a 30°C coolant, the initial pressure is
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`maintained for 70 seconds, after which the gap pressure is decreased for the
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`remaining 6 minutes of etch time. Id. at 5:26–33.
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`4. Kikuchi
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`Kikuchi is directed to methods for plasma ashing a resist film by
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`initially controlling the temperature of the substrate below that at which
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`explosion of the resist film occurs until after a surface portion of a resist film
`
`has been removed. Ex. 1004, Abstract. Kikuchi describes ashing a wafer’s
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`photoresist film at two sequential temperatures using either infrared heat
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`lamp 5 or hot plate 7 to raise the temperature, and thermometers 10, 66 to
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`measure the wafer and hot plate temperatures. See, e.g., id. at 1:56–2:3,
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`7:20–34, 7:62–68, 8:8–14, 11:6–9, Figs. 12, 13. Figure 1 of Kikuchi is
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`reproduced below.
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`
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`Figure 1 depicts a “conventional ashing method” in which substrate 1 is
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`placed on rack 8 and is heated by infrared lamps 5 to a predetermined
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`temperature in about 5 seconds (as shown by curve A in Figure 3). See id. at
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`1:56–60. The temperature of the substrate is controlled by infrared
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`thermometer 9. Id. at 1:56–65, 4:62–63. Kikuchi explains that in this
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`embodiment, it is difficult to coat the resist film 11 on only the front surface
`
`of substrate 1 as film will also be deposited on the rear surface of the
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`substrate. See id. at 2:47–61. Kikuchi states that if the substrate is heated in
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`contact with hot plate 7 to remove the resist film by ashing, hot plate 7
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`prevents the reactive radicals from working on that resist film and the resist
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`film may remain on the rear surface of substrate 1. Id. at 2:61–67; Figs. 8, 9.
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`Figure 11, shown below, depicts a sectional side view of an
`
`embodiment of the invention of Kikuchi.
`
`
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`Figure 11 depicts a semiconductor substrate (wafer) 1, thermometer
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`10, pins 16, and heating means 51 having hot plate 7, inside of vacuum
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`treatment chamber 4. Id. at 7:19–33. Kikuchi describes using the pins to
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`suspend the substrate being ashed above the hot plate to remove a surface
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`layer of photoresist, lowering pins 16 to place the substrate on the hot plate,
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`and then raising the temperature to ash the remaining portion of the
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`photoresist at a high temperature. See id. at 8:1–14.
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`Kikuchi describes etching a photoresist over a range of temperatures,
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`with an initial step of 70°C–160°C and a rapid increase to 200°C over a time
`
`period of 5 to 10 seconds. See, e.g., Ex. 1004, 2:37–46, 3:33–44, 5:46–54,
`
`Figs. 12, 13.
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`F. Asserted Obviousness of
`Independent Claim 27 over Kadomura and Matsumura and
`Independent Claim 51 over Kadomura, Matsumura, and Muller
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`Claim 27 is directed to a method of etching a substrate in the
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`manufacture of a device. In general, the claim requires [a]9 heating a
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`substrate holder having a temperature sensing unit to a first temperature with
`
`a heat transfer device, [b] placing a substrate on the substrate holder,
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`[c] etching a portion of film on the substrate at a selected first substrate
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`temperature, [d] etching
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