Trials@uspto.gov
`571-272-7822
`
`
` Paper 9
`
`Entered: June 13, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`and MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`DANIEL L. FLAMM,
`Patent Owner.
`____________
`
`Case IPR2017-00279
`Patent RE 40,264 E
`____________
`
`
`
`
`
`Before CHRISTOPHER L. CRUMBLEY, JO-ANNE M. KOKOSKI, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`CRUMBLEY, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`
`571-272-7822
`
`
` Paper 9
`
`Entered: June 13, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`INTEL CORPORATION, GLOBALFOUNDRIES U.S., INC.,
`and MICRON TECHNOLOGY, INC.,
`Petitioner,
`
`v.
`
`DANIEL L. FLAMM,
`Patent Owner.
`____________
`
`Case IPR2017-00279
`Patent RE 40,264 E
`____________
`
`
`
`
`
`Before CHRISTOPHER L. CRUMBLEY, JO-ANNE M. KOKOSKI, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`CRUMBLEY, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`
`
`IPR2017-00279
`Patent RE 40,264 E
`
`I. INTRODUCTION
`
`Intel Corporation, GLOBALFOUNDRIES U.S., Inc., and Micron
`Technology, Inc. (collectively, “Intel”) filed a Petition requesting an inter
`partes review of claims 13–26, 64, and 65 of U.S. Patent No. RE 40,264 E
`(Ex. 1001, “the ’264 patent”). Paper 2 (“Pet.”). Daniel L. Flamm, the
`named inventor on the ’264 patent and the Patent Owner, filed a Preliminary
`Response to the Petition. Paper 8 (“Prelim. Resp.”).
`Pursuant to 35 U.S.C. § 314(a), an inter partes review may not be
`instituted unless the information presented in the Petition shows “there is a
`reasonable likelihood that the petitioner would prevail with respect to at least
`1 of the claims challenged in the petition.” Taking into account the
`arguments presented in Flamm’s Preliminary Response, we conclude that
`the information presented in the Petition establishes that there is a reasonable
`likelihood that Intel will prevail in challenging claims 13–26, 64, and 65 of
`the ’264 patent as unpatentable. Accordingly, we institute trial on those
`claims.
`
`A. Related Matters
`
`The ’264 patent is the subject of thirteen prior or pending inter partes
`review proceedings: seven filed by Lam Research Corporation (IPR2015-
`01759; IPR2015-01764; IPR2015-01766; IPR2015-01768; IPR2016-00468;
`IPR2016-00469; and IPR2016-00470), each of which was denied institution
`or terminated pursuant to settlement; two filed by Samsung Electronics Co.,
`Ltd. (IPR2016-01510 and IPR2016-01512), of which the latter is currently
`pending; and three filed by Intel concurrently with the instant Petition
`(IPR2017-00280, IPR2017-00281, and IPR2017-00282). Although Flamm
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`Patent RE 40,264 E
`notes the prior challenges to the claims of the ’264 patent (Prelim. Resp. 1–
`2), he does not argue that we should exercise our discretion to deny
`institution of the instant Petition on the basis that the same or substantially
`the same art or arguments previously were presented to the Office. See 35
`U.S.C. § 325(d).
`Intel reports that Flamm has asserted the ’264 patent against it and
`other defendants in five proceedings in the Northern District of California:
`Case Nos. 5:16-cv-01578-BLF, 5:16-cv-1579-BLF, 5:16-cv-1580-BLF,
`5:16-cv-1581-BLF, and 5:16-cv-02252-BLF. Pet. 2.
`
`B. The ’264 Patent
`
`The ’264 patent, titled “Multi-Temperature Processing,” reissued
`April 29, 2008, from U.S. Patent Application No. 10/439,245, filed on May
`14, 2003. Ex. 1001, (54), (45), (21), (22). The ’264 patent is a reissue of
`U.S. Patent No. 6,231,776, which issued May 15, 2001 from U.S. Patent
`Application 09/151,163, filed September 10, 1998. Id. at (64). The patent is
`directed to a method “for etching a substrate in the manufacture of a device,”
`where the method “provide[s] different processing temperatures during an
`etching process or the like.” Ex. 1001, Abstract. The apparatus used in the
`method is shown in Figure 1 below.
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`Patent RE 40,264 E
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`Figure 1 depicts a substrate (product 28, such as a wafer to be etched) on a
`substrate holder (product support chuck or pedestal 18) in a chamber
`(chamber 12 of plasma etch apparatus 10). Id. at 3:24–25, 3:32–33, 3:40–
`41.
`
`Figures 6 and 7, below, depict a temperature-controlled substrate
`holder and temperature control systems.
`
`Figures 6 and 7 depict temperature-controlled fluid flowing through
`substrate holder (600, 701), guided by baffles 605, where “[t]he fluid [is]
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`used to heat or cool the upper surface of the substrate holder.” Id. at 14:28–
`63, 16:5–67. Figure 6 also depicts heating elements 607 underneath the
`substrate holder, where “[t]he heating elements can selectively heat one or
`more zones in a desirable manner.” Id. at 15:10–26. Referring to Figure 7,
`the operation of the temperature control system is described as follows:
`The desired fluid temperature is determined by comparing the
`desired wafer or wafer chuck set point temperature to a measured
`wafer or wafer chuck temperature . . . . The heat exchanger, fluid
`flow rate, coolant–side fluid temperature, heater power, chuck,
`etc. should be designed using conventional means to permit the
`heater to bring the fluid to a setpoint temperature and bring the
`temperature of
`the chuck and wafer
`to predetermined
`temperatures within specified time intervals and within specified
`uniformity limits.
`Id. at 16:36–39, 50–67.
`An example of a semiconductor substrate to be patterned is shown in
`Figure 9, below.
`
`
`Figure 9 depicts substrate 901 having a stack of layers including oxide layer
`903, polysilicon layer 905, tungsten silicide layer 907, and photoresist
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`IPR2017-00279
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`masking layer 909 with opening 911, from the treatment method shown in
`Fig. 10, below. Id. at 17:58–18:57.
`
`
`Figure 10 depicts the tungsten silicide layer being etched between
`points B and D at a constant temperature; the polysilicon layer being
`exposed between Points D and E; the polysilicon layer being etched at a
`constant temperature beyond point E; and the resist being ashed beyond
`Point I. Id. at 18:58–19:64. The plasma’s optical emission at 530 nm is
`monitored to determine when there is breakthrough to the polysilicon layer
`
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`IPR2017-00279
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`(Point D) and a lower etch temperature is required to etch the polysilicon
`layer (Point E). Id. at 19:8–24, 45–52.
`
`C. Illustrative Claim
`
`Of the challenged claims, only claim 13 is independent, and is
`
`reproduced below:
`13. A method of etching a substrate in the manufacture of a
`device, the method comprising:
`placing a substrate having a film thereon on a substrate
`holder in a chamber, the substrate holder having a
`selected thermal mass;
`setting the substrate holder to a selected first substrate holder
`temperature with a heat transfer device;
`etching a first portion of the film while the substrate holder
`is at the selected first substrate holder temperature;
`with the heat transfer device, changing the substrate holder
`temperature from the selected first substrate holder
`temperature to a selected second substrate holder
`temperature; and
`etching a second portion of the film while the substrate
`holder is at the selected second substrate holder
`temperature;
`wherein the thermal mass of the substrate holder is selected
`for a predetermined temperature change within a specific
`interval of time during processing; the predetermined
`temperature change comprises the change from the
`selected first substrate holder temperature to the selected
`second substrate holder temperature, and the specified
`time interval comprises the time for changing from the
`selected first substrate holder temperature to the selected
`second substrate holder temperature.
`Ex. 1001, 20:50–21:10.
`
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`Patent RE 40,264 E
`D. Asserted Grounds of Unpatentability
`
`Intel challenges claims 13–26, 64, and 65 of the ’264 patent as
`
`unpatentable under 35 U.S.C. § 103(a)1 on the grounds of unpatentability set
`forth in the table below. Pet. 5.
`References
`
`Challenged Claim(s)
`
`Muller2, Matsumura,3 Anderson,4 Hinman5 13–16, 18–19, 21–23, 64–65
`
`Muller, Matsumura, Anderson, Hinman,
`Wright6
`Miller, Matsumura, Anderson, Hinman,
`Kikuchi7
`Miller, Matsumura, Anderson, Hinman,
`Moslehi8
`Kadomura9, Matsumura, Anderson,
`Hinman
`Kadomura, Matsumura, Anderson,
`Hinman, Kikuchi
`Kadomura, Matsumura, Anderson,
`Hinman, Moslehi
`Kadomura, Matsumura, Anderson,
`Hinman, Muller
`
`19–20
`
`17
`
`24–26
`
`13–16, 18–23, 64–65
`
`17
`
`24–26
`
`15
`
`
`1 The relevant sections of the Leahy-Smith America Invents Act (“AIA”),
`Pub. L. No. 112–29, took effect on March 16, 2013. Because the application
`from which the ’264 patent issued was filed before that date, our citations to
`Title 35 are to its pre-AIA version.
`2 U.S. Patent 5,605,600 to Muller et al., issued Feb. 25, 1997 (Ex. 1002).
`3 U.S. Patent 5,151,871 to Matsumura et al., issued Sept. 29, 1992 (Ex.
`1003).
`4 U.S. Statutory Invention Registration No. H1145 to Anderson, published
`Mar. 2, 1993 (Ex. 1011).
`
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`
`II. ANALYSIS
`
`A. Claim Construction
`
`The ’264 patent has expired.10 For claims of an expired patent, the
`Board’s claim interpretation is similar to that of a district court. See In re
`Rambus, Inc., 694 F.3d 42, 46 (Fed. Cir. 2012). Claim terms are given their
`ordinary and customary meaning as would be understood by a person of
`ordinary skill in the art at the time of the invention, and in the context of the
`entire patent disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257
`(Fed. Cir. 2007). Only those terms in controversy need to be construed, and
`only to the extent necessary to resolve the controversy. See Vivid Techs.,
`Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`
`
`5 U.S. Patent No. 3,863,049 to Hinman, issued Jan. 28, 1975 (Ex. 1010).
`6 D.R. Wright et al., A Closed Loop Temperature Control System for a Low-
`Temperature Etch Chuck, Advanced Techniques for Integrated Processing
`II, Vol. 1803 (1992) (Ex. 1008).
`7 U.S. Patent 5,226,056 to Kikuchi et al., issued July 6, 1993 (Ex. 1004).
`8 U.S. Patent 5,192,849 to Moslehi, issued Mar. 9, 1993 (Ex. 1009).
`9 U.S. Patent 6,063,710 to Kadomura et al., filed Feb. 21, 1997 and issued
`May 16, 2000 (Ex. 1005).
`10 The ’264 patent expired no later than December 4, 2015, which is twenty
`years after December 4, 1995, the earliest filing date of an application to
`which the ’264 claims priority. See Ex. 1001 [63]; 35 U.S.C. § 154(a)(2)
`(2012 & Supp. III 2015) (stating patent term ends twenty (20) years from the
`date on which the application for the patent was filed in the United States,
`“or, if the application contains a specific reference to an earlier filed
`application or applications under section 120, 121, 365(c), or 386(c), from
`the date on which the earliest such application was filed”).
`
`
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`IPR2017-00279
`Patent RE 40,264 E
`1. Selected Thermal Mass
`Claim 13 recites a “substrate holder having a selected thermal mass.”
`Intel notes that, in a prior IPR involving claim 13 of the ’264 patent (Ex.
`1016, “the 1759 Decision”), the Board interpreted “selected thermal mass”
`to mean “thermal mass selected by selecting the mass of the substrate holder,
`the material of the substrate holder, or both.” Pet. 27; see Ex. 1016, 11–13.
`Intel contends that a skilled artisan would have agreed with this
`construction. Pet. 20. Flamm does not address the construction of the term.
`We, therefore, maintain our prior construction of “selected thermal mass.”
`
`2. Thermal Mass . . . Selected For A Predetermined
`Temperature Change Within A Specific Interval Of Time
`
`Claim 13 also requires that the thermal mass of the substrate holder be
`“selected for a predetermined temperature change within a specific interval
`of time.” In the 1759 Decision, we noted that the specification of the ’264
`patent does not disclose how the thermal mass of the substrate holder is
`selected, and makes only passing reference to the thermal mass being “low.”
`Ex. 1016, 11. For instance, the specification states that “[i]n a specific
`embodiment, the upper surface [of the substrate holder] is made using a low
`thermal mass, high conductivity material.” Ex. 1001, 15:42–44. The
`Summary of the Invention also states that the substrate holder has a “low
`thermal mass” as compared to the thermal capacity of the fluid that
`circulates through the substrate holder, in order to “permit[] maintaining the
`workpiece at a substantially uniform temperature.” Id. at 2:37–46. The
`specification does not describe how one of ordinary skill in the art is to
`select the thermal mass of the substrate holder “for a predetermined
`
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`IPR2017-00279
`Patent RE 40,264 E
`temperature change within a specific interval of time,” as required by claim
`13.
`
`In denying institution of trial on claim 13 in the 1759 Decision, we
`noted that “selected for a predetermined temperature change within a
`specific interval of time” requires that the “thermal mass must be selected in
`order to undergo a predetermined temperature change within a specific
`interval of time (for example, a change of 10ºC per minute).” Ex. 1016, 17.
`This is more than merely reducing the mass of the substrate holder in order
`to achieve a faster temperature change—we held that the limitation requires
`a discrete period of time. Id.
`Citing these holdings, Intel asserts that the proper construction of
`“thermal mass . . . selected for a predetermined temperature change within a
`specific interval of time” is “the material and/or mass of the substrate holder
`are chosen to effect a predetermined change in substrate holder temperature
`from a selected first temperature to a selected second temperature within a
`specific time period.” Pet. 21. Again, Flamm does not address this
`proffered construction. Upon review, we consider Intel’s construction to be
`consistent with our prior holdings regarding claim 13 of the ’264 patent and
`adopt it for purposes of this Decision.
`
`B. Priority Date for the Challenged Claims of the ’264 Patent
`
`As explained above, the ’264 patent reissued from the ’245
`application, filed on May 14, 2003. Ex. 1001, [21], [22]. The ’245
`application is a reissue of the ’776 patent, which issued May 15, 2001 from
`the ’163 application, which was filed September 10, 1998. Id. at [64].
`The ’163 application is a continuation-in-part of the following two
`applications: (1) U.S. Provisional Application No. 60/058,650 (“the ’650
`11
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`provisional application”), filed on September 11, 1997; and (2) U.S. Patent
`Application No. 08/567,224 (“the ’224 application”), filed on December 4,
`1995. Id. at [60], [63], 1:11–15.
`
`Intel contends that September 11, 1997 is the earliest possible priority
`date for the challenged claims, arguing that the ’224 application, filed on
`December 4, 1995, does not disclose the claimed subject matter. Pet. 9.
`Relying upon the testimony of its declarant, Dr. John Bravman (Ex. 1006,
`“the Bravman Declaration”), Intel contends the ’224 application fails to
`recite the term “thermal mass,” or describe selecting the thermal mass of a
`substrate holder in order to achieve a temperature change within a specific
`interval of time. Id. at 9 (citing Ex. 1006 ¶¶ 30–31). Consequently, Intel
`asserts that, because the ’224 application does not provide sufficient written
`description support for the thermal mass limitations of claim 13, the
`challenged claims only are entitled to claim priority to the filing date of the
`’650 provisional application (i.e., September 11, 1997). See id. Flamm does
`not argue that the ’264 patent is entitled to claim a priority date earlier than
`September 11, 1997.
`
`On this record, we are persuaded by Intel’s argument that the ’224
`application does not provide sufficient written description support for the
`selected thermal mass limitations of independent claim 13, and therefore the
`challenged claims of the ’264 patent are not entitled to claim priority to the
`December 4, 1995 filing date of the ’224 application.
`As such, based on the this record, we agree with Intel that Kadomura,
`which was filed on February 21, 1997, and the remaining asserted
`references, each of which were filed or published before the December 4,
`
`
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`IPR2017-00279
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`1995 filing date of the ’224 application, qualify as prior art to the challenged
`claims of the ’264 patent.
`
`C. Obviousness over Muller, Matsumura, Anderson, and Hinman
`
`Intel contends that claims 13–16, 18–19, 21–23, 64, and 65 are
`
`unpatentable under 35 U.S.C. § 103(a), as they would have been obvious
`over the combined disclosures of Muller, Matsumura, Anderson, and
`Hinman. Pet. 22–45. Intel explains how the combined references teach the
`subject matter of each challenged claim, and asserts that a person of ordinary
`skill in the art would have had reason to combine or modify the references.
`Id. Intel also relies upon the Bravman Declaration to support its positions.
`
`1. Muller
`Muller is directed to methods of shaping etch profiles by controlling
`wafer temperature using an electrostatic chuck and coolant circulating
`through a cathode, and by changing the pressure of the gas filled in the gaps
`between the wafer and the cathode. Ex. 1002, [54], Abstract, 1:7–12, 1:44–
`64, 4:51–5:25. Figure 4 of Muller is reproduced below.
`
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`IPR2017-00279
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`
`Figure 4 depicts wafer 104, electrostatic chuck 105, cathode 106, and gas
`filled gap 110 between wafer 104 and chuck 105 on the top and cathode 106
`on the bottom. Id. at 4:39–43, 51–55.
`Muller teaches that the change in taper angle of etched trenches
`correlates with increasing wafer temperature during the etching processes.
`Id. at 3:33–66, Figs. 1, 2. Muller explains that changing pressure of the gas
`filled in the gaps between the wafer and cathode, which can be accomplished
`in a very short period of time, results in an immediate effect on wafer
`temperature. Id. For example, wafer temperature can be increased by
`approximately 50ºC over a time of “several seconds” during etching. Id. at
`4:64–5:25, 5:41–48.
`In one example, Muller teaches performing an initial etch at either
`125ºC or 145ºC. Id. at 3:45–52, 3:56–66. The two etching temperature
`examples corresponded to two different coolant temperatures. For example,
`use of a cathode coolant at 10ºC results in a wafer temperature of
`approximately 125°C, while use of a cathode coolant at 30ºC results in a
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`IPR2017-00279
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`wafer temperature of approximately 145ºC. Id. at 3:45–52. Figure 3 below
`shows the wafer temperature at the two cathode coolant temperatures as a
`function of time.
`
`
`Figure 3 depicts a graph illustrating the change in wafer temperature for
`various coolant temperatures as a function of etch time. Id. at 2:55–57.
`In another example of an etching process, the gas-filled gap is
`pressurized for a first time period and then the pressure in the gap is rapidly
`changed to a second pressure for a second period of time. Id. at 4:64–5:3.
`Then, the gas pressure underneath the chuck is changed to increase wafer
`temperature by 50ºC in “several seconds” during etching. Id. at 4:64-5:25,
`5:41–48. In this example, using a 30°C coolant, the initial pressure is
`maintained for 70 seconds, after which the gap pressure is decreased for the
`remaining 6 minutes of etch time. Id. at 5:26–33.
`
`2. Matsumura
`Matsumura generally relates to heat-processing a semiconductor
`wafer and, in particular, to controlling temperatures of the semiconductor
`
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`wafer when it is heated or cooled. Ex. 1003, 1:8–13. According to
`Matsumura, one objective of the disclosed invention is to provide a “method
`of heat-processing semiconductor devices whereby temperatures of the
`semiconductor devices can be controlled at devices-heating and -cooling
`times so as to accurately control their thermal history curve.” Id. at 2:60–65.
`Matsumura discloses applying the method to plasma etching when it states
`that, although “the present invention has been applied to the adhesion and
`baking processes for semiconductor wafers in the above-described
`embodiments . . . , it can also be applied to any of the ion implantation,
`[chemical vapor deposition (“CVD”)], etching and ashing processes.” Id. at
`10:3–7. Figure 5A, reproduced below, is a schematic diagram of an
`embodiment for heat-processing a substrate (wafer W) on a substrate holder
`(wafer-stage 12, which includes upper plate 13 and conductive thin film 14)
`in chamber 11.
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`
`As shown in Figure 5A above, adhesion unit 42 along with control
`system 20 measures the temperature of thin film 14 deposited on the
`underside of upper plate 13 by using thermal sensor 25. Id. at 5:13–17,
`5:32–47, 5:67–6:4, 6:45–50. Control system 20 sends signals (SM) to power
`supply circuit 19 to heat semiconductor wafer W on upper plate 13 by
`conductive thin film 14, and sends signals (SC) to cooling system 23 to
`control the amount of coolant supplied to jacket 22. Id. at 5:52–6:32, Figs.
`5A, 5B. Inside the control system is a “recipe,” such as that shown in Figure
`9, reproduced below.
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`
`Figure 9, shown above, depicts a recipe with a “thermal history curve”
`showing temperature as a function of time. Id. at 4:42–43. At a given time
`(or pulse), the control system measures the substrate holder temperature with
`thermal sensor 25, compares this measurement to that of the recipe shown in
`Figure 9, and either (1) sends a signal (SM) to power supply circuit 19 to
`heat the substrate (wafer W) (e.g., heating wafer W from 20ºC to 90ºC
`within 60 seconds); (2) sends a signal (SC) to cooling system 23 to cool the
`substrate by allowing jacket 22 arranged under stage 12 to exchange heat
`with thin film 14 (e.g., cooling wafer W from 140ºC to 20ºC within 60
`seconds); or (3) sends no signal and waits for the next measurement time
`(e.g., holding the temperature of wafer W at 140ºC for 30 seconds). Id. at
`5:52–6:32, Figs. 5A, 5B.
`
`3. Anderson
`Anderson generally relates to the field of semiconductor
`manufacturing devices and, in particular, to chucks for controlling wafer
`temperature. Ex. 1011, 1:10–12. Anderson discloses that, in order to
`achieve maximum throughput of a tool in certain high energy processes,
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`such as plasma processes that include plasma etching, it is “imperative” that
`a wafer be set to its operating temperature as soon as possible and, once the
`operating temperature has been reached, to remove the process that
`generates heat for the wafer in a controlled manner. Id. at 2:60–65. For
`instance, Anderson discloses that, in one embodiment employing a low
`thermal mass heater, a chuck may be heated from room temperature to an
`operating temperature of 100º to 500ºC in a matter of seconds. Id. at 6:24–
`28.
`
`4. Hinman
`Hinman is directed to an improved temperature control system for use
`in controlling the temperature of small volumes of liquid undergoing
`analysis in a centrifugal chemistry analyzer. Ex. 1010, Abstract, 1:4–9.
`Specifically, Hinman notes that rapidly applying heat to a sample may result
`in “overshoot” in which the temperature rises above the desired range, while
`insufficient heat may result in a lower than desired temperature. Id. at 1:26–
`36, Fig. 3 (curve B showing overshoot, curve A showing insufficient heat).
`Hinman addresses this problem, in part, by heating the samples in cuvettes
`located in a ring member that has a substantially larger thermal mass than
`the liquid in the cuvettes. Id. at 2:41–45. The heat stored in the ring
`member permits a temperature change from about 15°–20°C to about 25°–
`40°C within 20–40 seconds, which Hinman notes can be achieved through
`the use of a ring member having a thermal mass of about 5–20 times the
`thermal mass of the liquid samples. Id. at 2:53–62. Hinman provides two
`examples of ring members with the appropriate thermal mass, an aluminum
`ring member of about 1 kg, and a copper ring member of about 2.5 kg, and
`provides exemplary calculations of their thermal masses. Id. at 2:65–3:6.
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`5. The Proposed Combination
`Intel provides detailed analysis setting forth how the combined
`disclosures of Muller, Matsumura, Anderson, and Hinman teach or suggest
`all limitations of independent claim 13, and relies on the testimony of
`Dr. Bravman in support thereof. Pet. 29–37. Intel contends that Muller
`discloses a method of etching a substrate using a substrate holder in a
`chamber, as well as the use of two different etch temperatures during the
`etching process. Id. at 29–30, 32–40. Intel also relies on Matsumura’s
`disclosure of a “predetermined recipe” for changing etch temperature over
`time as teaching two-temperature etching, as well as a temperature change
`over a predetermined time, and contends that it would have been obvious to
`combine “Matsumura’s substrate holder heater and temperature sensor,
`control system, and predetermined recipe process with Muller’s tool to carry
`out Muller’s multi-temperature process.” Id. at 33–35.
`With respect to claim 13’s requirement that the substrate holder have
`a selected thermal mass, Intel relies on Anderson’s disclosure of a substrate
`holder having a low thermal mass heater, and notes that Anderson teaches
`that the use of the low thermal mass heater permits temperature change from
`100° to 500°C in a matter of seconds. Id. at 30. Intel argues that “it was
`well known to select a low thermal mass substrate holder material for rapid
`temperature changes,” and that the math used to calculate the thermal mass
`of an object was also well-known. Id. at 31. Therefore, Intel concludes, it
`would have been obvious in view of Anderson to use a substrate holder with
`a selected thermal mass in the device of Muller. Id.
`Finally, claim 13 also requires that the thermal mass of the substrate
`holder be selected for “a predetermined temperature change with a specific
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`Patent RE 40,264 E
`interval of time during processing.” In our prior decisions addressing claim
`13 of the ’264 patent, we found the prior art lacking this limitation, because,
`like Anderson, the cited prior art only required a low thermal mass, not that
`the thermal mass is selected to achieve a chosen change in temperature over
`a specific period of time. See, e.g., Ex. 1017, 17–18. Intel relies on Hinman
`to disclose this limitation, arguing that Hinman describes “how to preselect
`the thermal mass of a material in a chemical analyzer’s ‘temperature control
`system’ to effectuate predetermined temperature changes within a specific
`interval.” Pet. 33, 40–41. Specifically, Hinman discloses that its metal ring
`member should have a thermal mass selected to be 5–20 times the thermal
`mass of the sample, in order to change from a “cold” temperature of 15°–
`20°C to a desired temperature of 25°–40°C within 20 to 40 seconds. Ex.
`1010, 2:41–3:6. Hinman proceeds to supply exemplary calculations for a
`ring of aluminum or copper, concluding that a 1 kg aluminum ring or 2.5 kg
`copper ring would have an appropriate thermal mass. Id.
`Given this disclosure, Intel concludes that it would have been obvious
`in view of Anderson and Hinman to select the precise thermal mass of the
`substrate holder used in Muller, to achieve a predetermined temperature
`change of a specific interval of time. Pet. 41–42. Intel argues that person of
`ordinary skill in the art would have had reason to use Hinman’s teachings to
`calculate the precise thermal mass of the substrate holder taught by
`Anderson, to address the goal of throughput in semiconductor wafer
`processing as addressed by both Muller and Anderson. Id. at 42–43.
`
`6. Analysis
`Upon review, Intel’s Petition reasonably sets forth how the disclosures
`of Muller, Matsumura, Anderson, and Hinman teach or suggest all
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`Patent RE 40,264 E
`limitations of claim 13, as well as the challenged dependent claims.
`Flamm’s response focuses primarily on the disclosures of Anderson and
`Hinman, and we address these arguments below.
`Flamm first argues that Anderson was previously cited to the Board
`against claim 13 in IPR2016-01510, and the panel found the cited art in that
`case did not establish a reasonable likelihood of success. Prelim. Resp. 3.
`We recognize that Anderson was at issue in that proceeding, but was relied
`on to teach the “thermal mass selected for a predetermined temperature
`change with a specific interval of time” limitation. See Samsung Elecs. Co.,
`Ltd. v. Daniel L. Flamm, IPR2016-01510, slip. op. at 17–20 (PTAB Feb, 14,
`2017) (Paper 6). We found that Anderson’s disclosure of a “low” thermal
`mass was insufficient to disclose this limitation, but that is not the purpose
`for which Intel cites Anderson in this case, and we note Hinman is cited here
`to supply the disclosure we previously found missing from Anderson.
`Second, Flamm argues that Anderson does not disclose selecting a
`thermal mass of a substrate holder, alleging that Anderson merely discloses
`that its heater has a low thermal mass. Prelim. Resp. 3–4. As shown in
`Figure 1 of Anderson, however, heating layer 15 is disposed on top of chuck
`11 and between insulating layers 13 and 14; wafer 20 is positioned onto
`upper insulating layer 14. Ex. 1011, 5:41–62. It is reasonable to conclude,
`as Intel suggests, that heating layer 15 is part of the substrate holder of
`Anderson such that modifying the thermal mass of the heater affects the
`overall thermal mass of the substrate holder. In this vein, we note that the
`’264 patent specification only describes selecting the thermal mass of a
`portion of the substrate holder, namely the upper surface of the substrate
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`Patent RE 40,264 E
`holder. See Ex. 1001, 15:40–48 (“the upper surface [of the substrate holder]
`is made using a low thermal mass, high conductivity material”).
`Turning to Hinman, Flamm argues that the reference does not teach a
`selected thermal mass, because it discloses only “an indefinite range of
`thermal mass from 5–10 and more, which teaches away from any concept of
`selected thermal mass.” Prelim. Resp. 5. We disagree, on this record, that
`Hinman’s disclosure that the ratio of the thermal mass of the ring to the
`thermal mass of the sample should be within a certain range is “indefinite;”
`in any event, Hinman also provides a more definite example of selecting a
`specific thermal mass, for example a 1 kg aluminum ring. Ex. 1010, 2:63–
`68.
`
`Flamm also argues that Hinman is not analogous art to the claimed
`invention of the ’264 patent, because it is neither in the same field of
`endeavor nor reasonably pertinent to the problem faced by the ’264 patent.
`Prelim. Resp. 5–10. Because we, on this record, conclude that Hinman is
`reasonably pertinent to the problem addressed by the ’264 patent, we need
`not address whether the reference is in the same field of endeavor.
`A reference is “reasonably pertinent” to a problem if it “logically
`would have commended itself to an inventor’s attention in considering his
`problem.” In re Icon Health and Fitness, Inc., 496 F.3d 1374, 1379–80
`(Fed. Cir. 2007) (quoting In re Clay, 966 F.2d 656, 658, 23 USPQ2 1058,
`1061 (Fed. Cir. 1992)). In defining the problem addressed by the inventor,
`the specification of the challenged patent is often instructive. Here, the ’264
`patent notes that prior art substrate etching processes used “batch” modes in
`which etching was done at a single temperature, and that the invention
`improves upon these processes by providing a multi-stage etching process
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`Patent RE 40,264 E
`using different temperatures. Ex. 1001, 1:65–2:11. As such, the invention
`allegedly overcame disadvantages of prior art processes, which required
`lowered throughput and etch rate in order to avoid excessive damage to a
`workpiece. Id. at 2:11–14.
`Flamm argues that the problem addressed by the ’264 patent is that of
`increased throughput while maintaining high etch selectivity, and that
`temperature control is not part of that problem, but rather the “solution to the
`problem.” Prelim. Resp. 10. As Intel and Dr. Bravman note, however, both
`Anderson and Muller recognize the importance of throughput in etching
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