UNITED STATES PATENT AND TRADEMARK OFFICE
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`______________________
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`
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`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
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`______________________
`
`NETAPP, INC
`Petitioner
`
`v.
`
`INTELLECTUAL VENTURES II, LLC
`Patent Owner
`
`
`
`Case No. IPR2017-00276
`U.S. Patent No. 6,633,945
`
`
`
`DECLARATION OF IAN JESTICE
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`1
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`I, Ian Jestice, do hereby declare and say:
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`1.
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`I am over the age of twenty-one (21) and competent to make this
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`declaration. I am also qualified to give testimony under oath. The facts and
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`opinions listed below are within my personal knowledge.
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`2.
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`I am being compensated for my time in this matter at my standard consulting
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`rate of $325/hr. My compensation in no way depends on the outcome of this
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`proceeding or the content of my opinions. I am not employed by, nor receiving
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`grant support from, Petitioner NetApp, Inc. in this matter. I am receiving
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`compensation from Petitioner solely for my involvement in this matter based only
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`on my standard hourly consulting fees.
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`3.
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`I have been asked to review certain documents, including U.S. Patent No.
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`6,633,945 (which I refer to as the ’945 Patent) (Ex. 1001), and to provide my
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`opinions on what those documents disclose. The documents I was asked to review
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`include those addressed in more detail in the rest of this declaration. I provide my
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`conclusions regarding the disclosures of these documents below. I was also asked
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`to review and provide opinions regarding U.S. Patent Nos. 6,516,442 and
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`6,968,459, which I understand are also involved in litigation against Petitioner
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`along with the ’945 Patent.
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`4.
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`In addition to the ’945 Patent, I have reviewed and am familiar with the
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`following documents:
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`a.
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`U.S. Patent No. 6,085,295 to Ekanadham et al. (“Ekanadham”) (Ex.
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`1003);
`
`b.
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`U.S. Patent No. 5,754,877 to Hagersten et al. (“Hagersten”) (Ex.
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`1004);
`
`c.
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`U.S. Patent No. 6,055,605 to Sharma et al. (“Sharma”) (Ex. 1002);
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`d. Meryem Primmer, An Introduction to Fibre Channel, Hewlett-
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`Packard Journal, October 1996 (Ex. 1014);
`
`e.
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`Enterprise System Connection (ESCON) Implementation Guide, IBM,
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`July 1996 (Ex. 1008);
`
`f.
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`Gheith A. Abandah et al., Characterizing Shared Memory and
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`Communication Performance: A case Study of the Convex SPP-1000,
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`January 8, 1996 (Ex. 1010);
`
`g.
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`U.S. Patent No. 6,065,077 to Fu (the “’077 Patent” or the “’430
`
`Application”) (Ex. 1015)
`
`h.
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`U.S. Patent No. 6,292,705 to Wang et al. (the “’294 Application”)
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`(Ex. 1016)
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`i.
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`U.S. Patent No. 6,516,442 to Wang et al. (the “’749 Application”)
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`(Ex. 1017)
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`5.
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`I was also asked to provide my opinions on the technical feasibility of
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`combining certain aspects of certain documents, and whether those combinations
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`would have been made from a technical perspective. I have offered my opinions
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`on the feasibility of such combinations in this declaration.
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`6.
`
`I am not offering any conclusions as to the ultimate determinations I
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`understand the Patent Trial and Appeal Board will make in this proceeding.
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`Specifically, I am not offering opinions on ultimate issues of validity or claim
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`construction. I am simply providing my opinion on technical issues, including on
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`the technical aspects of the documents as compared to the claims of the ’945 Patent
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`as a factual matter and on the combinability of the concepts disclosed in those
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`documents from a technical perspective.
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`BACKGROUND
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`7.
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`I hold the equivalent of an undergraduate degree in Telecommunications and
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`Computer Science from the City and Guilds Institute of London, which I obtained
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`in 1971.
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`8.
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`As described in more detail in my curriculum vitae (Ex. 1007) I have more
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`than 40 years of industry experience with storage devices, embedded software
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`systems for industry and consumer products, and other systems including Flash
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`Memory (Solid State Disks, memory cards, flash drives), Optical Storage (CD,
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`DVD, WORM, Magneto-Optical), Magnetic Storage (Hard Disk, Floppy Disk,
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`Tape), RAID/Disk Arrays
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`and
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`jukeboxes; USB,
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`SCSI,
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`iSCSI,
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`IDE/ATA/ATAPI/SATA, Fibre Channel, PCMCIA, game programming, home
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`appliances and telecommunications.
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`9.
`
`As part of my experience, I have worked as a design and systems engineer at
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`Amdahl Corporation, IBM and Fujitsu, designing, building, testing and supporting
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`Multi-Processor hardware and software.
`
`10.
`
`I have been familiar with the field of multiprocessing systems, specifically
`
`symmetric multiprocessing systems, over at least the past 30 years. For these
`
`reasons and because of my technical experience and training as outlined in my
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`curriculum vitae (Ex. 1007), I believe I am capable of offering technical opinions
`
`regarding the ’945 Patent and the other documents I reviewed as part of my work
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`in this matter. I believe I am capable of opining about the state of the art in these
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`areas at various points in time from the early 1970s to the present.
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`OVERVIEW OF SYMMETRIC MULTIPROCESSOR SYSTEMS
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`11. Multiprocessing originated in the mid-1950s in the computing industry, and
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`by the early 1960s, Burroughs Corporation had introduced a symmetrical
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`multiprocessor (“SMP”) with four central processing units (“CPUs”) and up to
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`sixteen memory modules connected with a crossbar switch. Ex. 1011. An SMP
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`system can process a single program on multiple processors that share a common
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`operating system and memory. As early as the late 1960s, Honeywell was selling
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`SMP systems. Ex. 1011. Honeywell’s system, known as “Multics” (Multiplexed
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`Information and Computing Service), represented one of the first commercial SMP
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`systems and was introduced in a series of academic papers presented at a
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`conference in 1965. Ex. 1011. The Multics system supported multiple CPUs
`
`sharing the same physical memory. Ex. 1011.
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`12. The Cray X-MP multiprocessor system in the 1980’s included a plurality of
`
`CPUs sharing the same central memory with a central control component
`
`connecting the CPU controls and data paths. Ex. 1009 at 3.
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`13. At least as early as 1996, distributed-memory multiprocessor systems
`
`employing a plurality of nodes were interconnected to allow physical memory to
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`be distributed among nodes; the memory was accessible as one global address
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`space by any of the nodes in the system. Ex. 1010 at 1-2. In one 1996 system,
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`ConvEx SPP-1000, the individual nodes were described as being symmetric
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`multiprocessors connecting one or more processors, local memory, and a remote
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`memory controller. Ex. 1010 at 2. The remote memory controller in this 1996
`
`system handled internode memory access using point-to-point transactions. Ex.
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`1010 at 2.
`
`14. Some early SMP systems did not maintain cache consistency between nodes,
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`leading to errors when one processor changed an original bit without updating any
`
`corresponding cached bits. When such a change occurred in systems that did not
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`have means for correcting for such errors, another processor would be unaware that
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`the edit had been made and would continue to use the outdated cached memory
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`line, as opposed to the updated memory line.
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`15. Early symmetric multiprocessor systems relied on software and hardware
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`protocols such as IBM’s Direct Control Interface (“DCI”) and Channel-to-Channel
`
`Adapters (“CTCA”) to maintain cache consistency between nodes. However, as
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`performance demand increased, performance was throttled by the software-
`
`controlled maintenance of cache consistency. The performance restrictions
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`imposed by software-based cache coherency maintenance drove the industry to
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`continue exploring cache coherency maintenance techniques using various
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`different hardware and software configurations.
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`16.
`
`In 1993, IBM introduced the Enterprise System Connectivity (ESCON)
`
`channel, which replaced copper cables with direct fiber optic connections. Ex.
`
`1008 at 1. ESCON introduced what was, at the time, a new topology of control
`
`unit and channel attachment. ESCON control units and channels were “attached in
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`a switched point-to-point arrangement. The switching capabilities allow[ed]
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`multiple connections between channels and control units without requiring
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`permanent physical connections.” Ex. 1008 at 1.
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`17.
`
`In 1994, The American National Standards Institute (ANSI) adopted a
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`common standard for “Fibre Channel,” ISO 14165-1, which was provided for the
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`standardization of a fiber optic network that could be configured to directly
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`connect nodes of the network with fiber channels.
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`18. Thus, at least by the mid-1990s, it was known that nodes of a network could
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`be connected by using direct fiber channels between all nodes in a system. This
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`type of topology could properly be described as a “point-to-point” system.
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`U.S. PATENT NO. 6,633,945
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`19. The ’945 Patent is titled “Fully connected cache coherent multiprocessing
`
`systems.” Ex. 1001. The ’945 Patent discloses a multi-node symmetric
`
`multiprocessor system with a plurality of processors in each node, memory in each
`
`node, and a flow control unit, or “FCU”, in each node. Ex. 1001, Figs 2, 3, 12 and
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`13. Each FCU of the ’945 Patent includes at least a switch, an internal bus, and a
`
`plurality of controllers. Ex. 1001, Fig. 3. Each node of the system described in the
`
`’945 Patent is connected to the other node(s) of the system via a so-called point-to-
`
`point connection (referred to in the claims as the “third point-to-point connection”)
`
`coupled to the data switch included in each FCU.
`
`20. The ’945 Patent was filed on July 8, 1999, as a continuation-in-part of U.S.
`
`Patent App. No. 09/281,749, filed on March 30, 1999, now U.S. Patent No.
`
`6,516,442 (the “’749 Application”) which is a continuation-in-part of U.S. Patent
`
`App. No. 09/163,294, filed on September 29, 1998, now U.S. Patent No.
`
`6,292,705 (the “’294 Application”), which is a continuation-in-part of U.S. Patent
`
`
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`App. No. 08/986,430, filed on December 7, 1997, now U.S. Patent No. 6,065,077
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`(the “’430 Application”). I was asked to review these various applications as part
`
`of my review and offer certain opinions on their disclosures; I have given those
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`opinions below.
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`21. Claim 1 of the ’945 Patent recites:
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`[a] A multi-processor shared memory system comprising:
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`[b] a first set of point-to-point connections;
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`[c] a first set of processors each coupled to one of the first set of point-
`to-point connections;
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`[d] a first memory coupled to one of the first set of point-to-point
`connections;
`
`[e] a first flow control unit including a first data switch coupled to the
`first set of point-to-point connections wherein the first data switch is
`configured to interconnect the first set of point-to-point connections to
`provide first data paths between the first memory and the first set of
`processors;
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`[f] a second set of point-to-point connections;
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`a second set of processors each coupled to one of the second set of
`point-to-point connections;
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`a second memory coupled to one of the second set of point-to-point
`connections;
`
`a second flow control unit including a second data switch coupled to the
`second set of point-to-point connections wherein the second data switch is
`configured to interconnect the second set of point-to-point connections to
`provide second data paths between the second memory and the second set of
`processors; and
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`[g] a third point-to-point connection coupled to the first data switch and
`to the second data switch wherein the first data switch is configured to
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`interconnect the first set of point-to-point connections to the third point-to-
`point connection and the second data switch is configured to interconnect the
`second set of point-to-point connections to the third point-to-point
`connection to provide third data paths between the second memory and the
`first set of processors and between the first memory and the second set of
`processors.
`
`Ex. 1001 at 9:1-36.
`
`22.
`
` Claim 6 of the ’945 Patent recites:
`
`[a] A method of operating a multi-processor shared memory system
`comprising a first set of point-to-point connections, a first set of processors
`each coupled to one of the first set of point-to-point connections, a first
`memory coupled to one of the first set of point-to-point connections, a first
`flow control unit including a first data switch coupled to the first set of
`point-to-point connections, a second set of point-to-point connections, a
`second set of processors each coupled to one of the second set of point-to-
`point connections, a second memory coupled to one of the second set of
`point-to-point connections, a second flow control unit including a second
`data switch coupled to the second set of point-to-point connections, and a
`third point-to-point connection coupled to the first data switch and to the
`second data switch, the method comprising:
`
`[b] interconnecting the first set of point-to-point connections in the first
`data switch to provide first data paths between the first memory and the first
`set of processors;
`
`[c] interconnecting the second set of point-to-point connections in the
`second data switch to provide second data paths between the second memory
`and the second set of processors; and
`
`[d] interconnecting the first set of point-to-point connections to the third
`point-to-point connection in the first data switch and interconnecting the
`second set of point-to-point connections to the third point-to-point
`connection in the second data switch to provide third data paths between the
`second memory and the first set of processors and between the first memory
`and the second set of processors.
`
`Ex. 1001 at 10:1-16.
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`23. The ’945 Patent is directed to a symmetric multiprocessor memory system.
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`Ex. 1001 9:2; Abstract. The ’945 Patent is further directed to a first set of
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`processors, each coupled to a point-to-point connection. A memory is coupled to a
`
`point-to-point connection. These point-to-point connections comprise a first set of
`
`point-to-point connections. A flow control unit (“FCU”), which includes a data
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`switch, also is coupled to the first set of point-to-point connections. The switch
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`connects the processors to the memory and provides data paths between the
`
`processors and memory. Ex. 1001 9:3-13.
`
`24.
`
`In my opinion, it is technically proper to consider this collection of
`
`processors and memory a “node.” With this understanding, the ’945 Patent is
`
`further directed to a second node, containing the same components as the first: a
`
`second set of processors, a second memory, a second FCU, all coupled with a
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`second set of point-to-point connections. Ex. 1001 9:14-25.
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`25. Finally, the ’945 Patent is directed to a third point-to-point connection
`
`coupled to the first data switch of the first FCU and the second data switch of the
`
`second FCU, where the third connection provides data paths between the second
`
`memory and the first set of processors and between the first memory and the
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`second set of processors. Ex. 1001 9:26-35.
`
`26. Claim 1 of the ’945 Patent requires, for example, “a third point-to-point
`
`connection coupled to the first data switch and to the second data switch wherein
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`the first data switch is configured to interconnect the first set of point-to-point
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`connections to the third point-to-point connection and the second data switch is
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`configured to interconnect the second set of point-to-point connections to the third
`
`point-to-point connection to provide third data paths between the second memory
`
`and the first set of processors and between the first memory and the second set of
`
`processors.” Ex. 1001, Claim 1 (emphasis added). Claim 6 of the ’945 Patent
`
`similarly requires “a third point-to-point connection coupled to the first data
`
`switch and to the second data switch, the method comprising: . . . interconnecting
`
`the first set of point-to-point connections to the third point-to-point connection in
`
`the first data switch and interconnecting the second set of point-to-point
`
`connections to the third point-to-point connection in the second data switch to
`
`provide third data paths between the second memory and the first set of processors
`
`and between the first memory and the second set of processors.” Ex. 1001, Claim
`
`6 (emphasis added).
`
`27. Based on my review of the applications to which the ’945 Patent claims
`
`priority (i.e., the ’749 Application, the ’294 Application, and the ’430 Application),
`
`I do not believe that any of those applications teach the idea of using a “third point-
`
`to-point connection” to connect nodes as recited in the claims.
`
`28. On the contrary, the first disclosure I was able to identify as relevant to the
`
`claimed “third point-to-point connection” was in the filing of U.S. Patent App.
`
`
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`No. 09/349,641 on July 8, 1999, which issued as the ’945 Patent. The portions of
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`disclosure in the ’945 Patent most relevant to the claimed “third point-to-point
`
`connection” are col. 6, line 62 to col. 8, line 54 in the specification and FIG. 12 in
`
`the drawings. Based on my review, corresponding disclosures to the passages I
`
`identified from the ’945 Patent as filed are not found in the ’749 Application, the
`
`’294 Application, or the ’430 Application. Nor could I find any separate support
`
`for the claimed “third point-to-point connection” in the ’749 Application, the ’294
`
`Application, or the ’430 Application.
`
`29. Based on the failure to disclose the “third point-to-point connection” prior to
`
`July 8, 1999, I have been asked to assume for purposes of my analysis that the
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`relevant filing date for the ’945 Patent is July 8, 1999. I have therefore tried to
`
`offer opinions in this declaration through the eyes of one of skill in the art (as
`
`defined below in paragraph 37) as of July 8, 1999.
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`SUMMARY OF OPINIONS
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`30. At a high level, the symmetric multiprocessor (“SMP”) system disclosed in
`
`the ’945 Patent was not new as of July 8, 1999. My review of the documents
`
`referenced herein comports with my experience that those of skill in the art prior to
`
`1999 knew of multi-node systems, where each node included a plurality of
`
`processors, a memory, and an internal data switch. Further, those of skill in the art
`
`prior to 1999 knew that one node could be connected to another node to form a
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`multi-node system and that such a connection could be accomplished via a point-to
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`point connection.
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`31. As discussed in more detail below, my review of prior art documents in this
`
`proceeding demonstrates that the individual components of Claims 1 and 6 of the
`
`’945 Patent were well-known as of the priority date of July 8, 1999. Specifically,
`
`U.S. Patent No. 6,085,295 to Ekanadham et al. (“Ekanadham”) discloses each and
`
`every element of Claims 1 and 6 of the ’945 Patent. Ex. 1003.
`
`32. Additionally, U.S. Patent No. 6,055,605 to Sharma et al. (“Sharma”)
`
`discloses each and every element of claims 1 and 6 the ’945 Patent. Ex. 1002.
`
`33. U.S. Patent No. 5,754,877 to Hagersten et al. (“Hagersten”) strengthens the
`
`understanding that the node connection techniques of the ’945 Patent were known
`
`techniques for connecting nodes in SMP systems before the filing of the ’945
`
`Patent. Ex. 1004.
`
`34. The combinations I have been asked to consider in the instant proceeding
`
`(i.e., Ekanadham in view of Hagersten and Sharma in view of Hagersten) could
`
`and would have been made by a person of ordinary skill in the art (“POSA”), as I
`
`describe in more detail below in paragraphs 37-40 as of July 8, 1999. In
`
`considering those combinations, I was asked not to use “hindsight” reasoning.
`
`Rather, I was asked to consider the feasibility and combinability of references
`
`through the eyes of a POSA as of July 8, 1999. As I describe below, the individual
`
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`references, which are all attributable to well-known industry leaders in the SMP
`
`space in the 1990s, contain statements and teachings that motivate those of skill in
`
`the art to look to the other references in the combinations I was asked to consider.
`
`35.
`
`In my opinion, a POSA would have been motivated to combine Ekanadham
`
`with Hagersten; the resulting system discloses each feature of Claims 1 and 6 of
`
`the ’945 Patent. Likewise, in my opinion, a POSA would have been motivated to
`
`combine Sharma with Hagersten; the resulting system also discloses each feature
`
`of Claims 1 and 6 of the ’945 Patent.
`
`36. As I describe below, the prior art discloses the features claimed in Claims 1
`
`and 6 of the ’945 Patent, including multi-node symmetric multiprocessor systems
`
`wherein each node includes a plurality of processors, a memory, a data switch,
`
`point-to-point connections within the node, as well as a point-to-point connection
`
`between nodes.
`
`LEVEL OF SKILL IN THE ART
`
`37.
`
`I was asked to provide my opinion about the experience and background a
`
`POSA of the ’945 Patent would have had as of July 8, 1999. In my opinion, such a
`
`POSA would have had at least a bachelor’s degree in computer science or
`
`electrical engineering or its equivalent and at least four years of experience
`
`designing, testing or implementing with multi-processing computer systems.
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`38. The multi-processor systems field was a relatively specialized field as it
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`would have required understanding of both conventional hardware and software
`
`techniques at the time. Individuals focused on writing operating systems in 1999
`
`for example, would not have had the requisite understanding of the hardware
`
`requirements. Further, individuals developing the physical computer systems
`
`would not have been familiar with the software considerations associated with
`
`cache consistency.
`
`39. Accordingly, a POSA would understand how SMP systems could be built,
`
`would recognize potential pitfalls in various design choices of both hardware and
`
`software solutions, and would understand how to research the state of the industry
`
`as well as academic research in the area.
`
`40.
`
`I believe that I was a POSA as of July 8, 1999 because I had the requisite
`
`understanding of both the hardware and software issues present in a system
`
`described in the ’945 Patent. Furthermore, I believe that I can opine today about
`
`what those of skill in the art would have known and understood as of July 8, 1999.
`
`POINT-TO-POINT CONNECTION
`
`41.
`
`I have been asked to explain my understanding of the term “point-to-point
`
`connection” to a POSA as of July 8, 1999.
`
`42. Concerning the third point-to-point connection between a data switches in
`
`separate nodes, the ’945 Patent states that “[t]he interconnection between FCUs are
`
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`point to point and fully connected. Each FCU has direction connection to all other
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`FCUs.” Ex. 1001 7:14-16; Fig. 12.
`
`43.
`
`I believe that the statement “each FCU has direction connection to all other
`
`FCUs” contains a typographical error, and should read that each FCU has direct
`
`connection to all other FCUs. This interpretation of what I believe to be a typo is
`
`consistent with the other disclosures of the ’945 Patent, as well as the disclosures
`
`incorporated therein.
`
`44. Fig. 12 confirms the recited direct connections between each FCU and all
`
`other FCUs, as it illustrates three bi-directional arrows, each described as a “PT-
`
`TO-PT CHANNEL,” connecting each FCU to the other three FCUs:
`
`
`
`45.
`
`In my study of documents as part of my work in this case, I note that U.S.
`
`Patent No. 6,065,077 (“the ’077 Patent), which is the ultimate parent of the ’945
`
`Patent, defines a point-to-point connection (although it does not indicate how to
`
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`connect multiple nodes in an SMP system and thus does not describe the claimed
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`“third” point-to-point connection) as follows:
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`A channel 210 is a point-to-point connection between the FCU
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`212 and either a CIU 208, BBU 206 or MCU 204. A point-to-
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`point connection is a statically-configured communication link
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`between two devices. The channel 210 provides a direct
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`communication path and is only used by the two connected
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`devices.
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`Ex. 1015 12:15-23.
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`46. This use of the term “point-to-point” is consistent with my understanding, as
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`well as the understanding of those in the art as of July 8, 1999. As described
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`herein, I have been asked to consider “a statically configured communications link
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`between two devices” as the definition of a point-to-point connection when
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`analyzing whether the prior art discloses the elements of Claims 1 and 6 of the
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`’945 Patent. I have done that herein.
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`THE EKANADHAM PATENT
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`47. As part of my work in this proceeding, I was asked to review Ekanadham.
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`Ex. 1003.
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`48. Ekanadham is entitled “Method of maintaining data coherency in a
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`computer system having a plurality of interconnected nodes” and is generally
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`directed to providing coherent shared memory access among a plurality of shared
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`memory multiprocessor nodes. Ex. 1003 at Abstract.
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`49. Ekanadham teaches a method of providing cache coherency in a shared
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`memory system, where the shared memory system comprises a network of nodes
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`and each node includes a plurality of processors. Ex. 1003 1:9-10. Further,
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`Ekanadham teaches that “all communications between processors, the memories
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`and the adapters are made point to point without the need for broadcasts within the
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`SMP node.” Ex. 1003 2:14-16.
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`50. Ekanadham teaches “coherent shared memory access across a number of
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`interconnected multi-processor nodes.” Ex. 1003 2:48-50. When managing
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`commands between nodes, Ekanadham teaches that “a memory command is issued
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`from one of the processors of a node to a memory of another node; the command is
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`directed to an adapter of the issuing node. The adapter of the issuing node then
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`receives the command and forwards the command to the adapter at the remote
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`node. When the adapter at the remote node receives the command, it then
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`forwards the command to its local memory, which then updates its list of
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`processors to include or exclude the adapter.” Ex. 1003 2:52-61.
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`51. When Ekanadham states that “all communications between the processors,
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`the memories, and the adapters are made point to point without the need for
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`broadcasts within
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`the SMP node,” I understand
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`that
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`to mean
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`that all
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`communications “between . . . the adapters,” including between an adapter of one
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`node and an adapter of a second node, are point-to-point communications. This is
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`further supported by the understanding that a node can only have one adapter and
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`the disclosure uses a plural form of adapters. Further in this regard, Ekanadham
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`teaches that the adapter consults its node list for the line to determine which remote
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`nodes to forward the invalidations to, and sends a message to all such nodes. Ex.
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`1003 4:57-60. Such communications are only sent to nodes that require the receipt
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`of the communication, and the communication would not be sent to nodes not in
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`need of the same.
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`52. Claim 1 of Ekanadham recites sending a memory command direct to an
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`adapter of said one node. Claim 1 of Ekanadham thus further supports my view
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`that the column 2 disclosure means that connections between adapters can be
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`point-to-point connections.
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`53. Each node of Ekanadham includes a plurality of processors P1, P2, . . . , PN
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`interconnected together by a switch (SW). The switch also interconnects the
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`memory modules M1, M2, . . . , MN and adapters A. The nodes are connected to
`
`each other through a network. Ex. 1003 3:37-45.
`
`54. When the need exists to update a cache line, “the adapter consults its node
`
`list for the line to determine which remote nodes to forward the invalidations to,
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`and sends a message to all such nodes.” Ex. 1003 4:57-60. Ekanadham teaches
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`that “if [a] command is directed to a memory of another node of said system, then
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`sending [the] memory command directly to an adapter of said one node.” Ex. 1003
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`8:40-43. This passage of Ekanadham therefore teaches a point-to-point connection
`
`between nodes that allows for a command to be sent directly to a recipient node
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`from an origin node, without the need to address the recipient node.
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`’945 Patent Claim Analysis
`
`55. Element [a] of Claim 1 of the ’945 Patent, the preamble, recites “a multi-
`
`processor shared memory system.”
`
`56. Ekanadham teaches “a method of providing cache coherence in a shared
`
`memory system composed of a network of multiprocessor nodes.” Ex. 1003 1:9-
`
`10. Because of the disclosures I reference above, I believe that Ekanadham
`
`discloses the preamble.
`
`57. Element [b] of Claim 1 of the ’945 Patent recites “a first set of point-to-point
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`connections.”
`
`58. As noted above, Ekanadham teaches that “all communications between the
`
`processors, the memories and the adapters are made point to point without the need
`
`for broadcasts within the SMP node.” Ex. 1003 2:14-16. The intra-node
`
`communications described by Ekanadham are, therefore, via point to point
`
`connections. Because of the disclosures I reference above, I believe that
`
`Ekanadham teaches a first set of point-to-point connections.
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`59. Element [c] of Claim 1 of the ’945 Patent recites “a first set of processors
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`each coupled to one of the first set of point-to-point connections.”
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`60. Ekanadham teaches “[e]ach node has a plurality of processors P1, P2, . . . ,
`
`PN interconnected to each other by a switch (SW). The switch also interconnects
`
`the memory modules M1, M2, . . . , MN and adapters A.” Ex. 1003 3:37-45. And
`
`once again, Ekanadham teaches that “all communications between the processors,
`
`the memories and the adapters are made point to point . . . .” Ex. 1003 2:14-16.
`
`The processors described in Ekanadham are, therefore, coupled to the point-to-
`
`point connections. Because of the disclosures I reference above, I believe
`
`Ekanadham teaches a first set of processors each coupled to one of the first set of
`
`point-to-point connections.
`
`61. Element [d] of Claim 1 of the ’945 Patent recites “a first memory coupled to
`
`one of the first set of point-to-point connections.”
`
`62. Ekanadham teaches “The switch also interconnects the memory modules
`
`M1, M2, . . . , MN and adapters A.” Ex. 1003 3:41-45. And once again,
`
`Ekanadham teaches that “all communications between the processors, the
`
`memories and the adapters are made point to point . . . .” Ex. 1003 2:14-16. The
`
`memory described in Ekanadham is, therefore, coupled to the point-to-point
`
`connections. Because of the disclosures I reference above, I believe Ekanadham
`
`teaches a first memory coupled to one of the first set of point-to-point connections.
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`63. Element [e] of Claim 1 of the ’945 Patent recites “a first flow control unit
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`including a first data switch coupled to the first set of point-to-point connections
`
`wherein the first data switch is configured to interconnect the first set of point-to-
`
`point connections to provide first data paths between the first memory and the first
`
`set of processors.”
`
`64. Ekanadham teaches a switch and an adapter in each node. Ex. 1003 3:37-
`
`43. Ekanadham teaches that “[t]he adapter connects to the switch and plays the
`
`role of either a memory or a processor. The behavior of the adapter is different for
`
`different memory lines. When a line is homed at the local memory of the node, the
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`adapter behaves as a proxy processor for that line. When a line is homed at the
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`memory of a remote node, the adapter behaves