UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`______________________
`
`NETAPP, INC.
`Petitioner
`
`v.
`
`INTELLECTUAL VENTURES II, LLC
`Patent Owner
`
`Case No.: IPR2017-00276
`U.S. Patent No. 6,633,945
`
`PETITION FOR INTER PARTES REVIEW
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`NETAPP, INC. EXHIBIT 1018
`NetApp, Inc. v. Intellectual Ventures II, LLC
`IPR2017-00276
`
`Page 1 of 81
`
`
`
`______________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`______________________
`
`NETAPP, INC.
`Petitioner
`
`v.
`
`INTELLECTUAL VENTURES II, LLC
`Patent Owner
`
`Case No.: IPR2017-00276
`U.S. Patent No. 6,633,945
`
`PETITION FOR INTER PARTES REVIEW
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`NETAPP, INC. EXHIBIT 1018
`NetApp, Inc. v. Intellectual Ventures II, LLC
`IPR2017-00276
`
`Page 1 of 81
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 6,633,945
`
`Table of Contents
`
`I.
`II.
`
`INTRODUCTION
`BRIEF HISTORY OF SYMMETRIC MULTIPROCESSOR
`SYSTEMS
`III. THE ’945 PATENT
`A.
`Overview
`B.
`Prosecution History
`C.
`The ’945 Patent Is Not Entitled to a Priority Date Earlier than
`July 8, 1999.
`IV. GROUNDS FOR STANDING (37 C.F.R. § 42.104(A))
`V.
`PAYMENT OF FEES (37 C.F.R. §§ 42.15 AND 42.103)
`VI. MANDATORY NOTICES (37 C.F.R. § 42.8(B))
`A.
`Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))
`B.
`Related Matters (37 C.F.R. § 42.8(b)(2))
`C.
`Lead and Backup Counsel and Service (37 C.F.R. §
`42.8(b)(3)-(4))
`VII. PERSON OF ORDINARY SKILL IN THE ART
`VIII. CLAIM CONSTRUCTION
`A.
`Broadest Reasonable Interpretation Standard
`B.
`Point-to-Point Connection(s)
`IX. STATEMENT OF THE PRECISE RELIEF REQUESTED AND
`THE REASONS THEREFOR (37 C.F.R. § 42.22(A) AND
`42.104(B))
`
`6
`
`6
`9
`9
`12
`
`14
`17
`17
`17
`17
`17
`
`18
`18
`19
`19
`20
`
`25
`
`2
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`
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`Petition for Inter Partes Review of U.S. Patent No. 6,633,945
`
`A.
`
`B.
`
`C.
`
`Ground 1: Claims 1 and 6 are Unpatentable Under 35 U.S.C.
`§ 103 as obvious in view of Ekanadham and Hagersten.
`25
`Overview of the Prior Art of Ground 1
`1.
`Motivation to Combine the Art Applied in Ground 1
`2.
`Independent Claim 1
`3.
`Independent Claim 6
`4.
`Ground 2: Claims 1 and 6 are Unpatentable Under 35 U.S.C.
`§ 103 as obvious in view of Ekanadham.
`Ground 3: Claims 1 and 6 are Unpatentable Under 35 U.S.C.
`§ 103 as obvious in view of Sharma and Hagersten.
`1.
`Overview of the Prior Art of Ground 3
`2.
`Motivation to Combine the Art Applied in Ground 3
`3.
`Independent Claim 1
`4.
`Independent Claim 6
`Ground 4: Claims 1 and 6 are Unpatentable Under 35 U.S.C.
`§ 103 as obvious in view of Sharma.
`EXPLANATION OF GROUNDS UNDER ALTERNATIVE
`CONSTRUCTIONS
`XI. SECONDARY CONSIDERATIONS OF OBVIOUSNESS
`XII. CONCLUSION
`
`D.
`
`X.
`
`3
`
`26
`30
`34
`46
`
`49
`
`50
`5051
`53
`56
`6970
`
`7273
`
`7374
`7475
`7576
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`Page 3 of 81
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`Petition for Inter Partes Review of U.S. Patent No. 6,633,945
`
`Ex. 1001
`
`Ex. 1002
`
`Ex. 1003
`
`Ex. 1004
`
`Ex. 1005
`
`Ex. 1006
`
`Ex. 1007
`
`Ex. 1008
`
`Ex. 1009
`
`Ex. 1010
`
`Ex. 1011
`
`Ex. 1012
`
`Ex. 1013
`
`Ex. 1014
`
`LIST OF EXHIBITS
`
`U.S. Patent No. 6,633,945 (filed July 8, 1999) (the “’945
`Patent”)
`
`U.S. Patent No. 6,055,605 to Sharma et al. (filed October 24,
`1997) (“Sharma”)
`
`U.S. Patent No. 6,085,295 to Ekanadham et al. (filed October
`20, 1997) (“Ekanadham”)
`
`U.S. Patent No. 5,754,877 to Hagersten et al. (filed July 2,
`1996) (“Hagersten”)
`
`Patent Owner’s Complaint in Intellectual Ventures I, LLC,
`Intellectual Ventures II, LLC v. NetApp, Inc., Case No. 1:16-cv-
`10868-IT (D. Mass.), filed May 11, 2016, Doc. No. 1.
`
`Declaration of Ian Jestice in Support of Petition for Inter Partes
`Review of U.S. Patent 6,633,945
`
`Curriculum Vitae of Mr. Ian Jestice
`
`Enterprise System Connection (ESCON) Implementation
`Guide, IBM, July 1996
`
`The CRAY X-MP Series of Computer Systems, CRAY, 1985
`
`Gheith A. Abandah et al., Characterizing Shared Memory and
`Communication Performance: A case Study of the Convex SPP-
`1000, January 8, 1996
`
`Multics History, MULTICS,
`http://multicians.org/history.html
`
`(November
`
`16,
`
`2016),
`
`Prosecution History of the ’945 Patent
`
`[Reserved]
`
`Meryem Primmer, An Introduction to Fibre Channel, HEWLETT-
`PACKARD JOURNAL, October 1996
`
`4
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`Petition for Inter Partes Review of U.S. Patent No. 6,633,945
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`Ex. 1015
`
`Ex. 1016
`
`Ex. 1017
`
`U.S. Patent No. 6,065,077 to Fu (“the ’077 Patent)
`
`U.S. Patent No. 6,292,705 to Wang et al.
`
`U.S. Patent No. 6,516,442 to Wang et al.
`
`5
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`Petition for Inter Partes Review of U.S. Patent No. 6,633,945
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`I.
`
`INTRODUCTION
`
`NetApp, Inc., (“Petitioner”) requests inter partes review of Claims 1 and 6
`
`of U.S. Patent No. 6,633,945 (“the ’945 Patent”) (Ex. 1001) under 35 U.S.C. §§
`
`311–319.
`
`II.
`
`BRIEF HISTORY OF SYMMETRIC MULTIPROCESSOR SYSTEMS
`
`Multiprocessing originated in the mid-1950s in the computing industry, and
`
`by the early 1960s, Burroughs Corporation had introduced a so-called symmetrical
`
`multiprocessor (“SMP”) with four central processing units (“CPUs”) and up to
`
`sixteen memory modules connected with a crossbar switch. Ex. 1011; Ex. 1006 at
`
`¶11. An SMP system can process a single program on multiple processors that
`
`share a common operating system and memory. Ex. 1006 at ¶11. As early as the
`
`late 1960s, Honeywell was selling SMP systems. Ex. 1011; Ex. 1006 at ¶11.
`
`Honeywell’s system, known as “Multics” (Multiplexed Information and
`
`Computing Service) represented one of the first commercial SMP systems and was
`
`introduced in a series of academic papers presented at a conference in 1965. Ex.
`
`1011; Ex. 1006 at ¶11. The Multics system supported multiple CPUs sharing the
`
`same physical memory. Ex. 1011; Ex. 1006 at ¶11.
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`The Cray X-MP multiprocessor system in the 1980s included a plurality of
`
`CPUs sharing the same central memory with a central control component
`
`connecting the CPU controls and data paths. Ex. 1009 at 3; Ex. 1006 at ¶12.
`
`At least as early as 1996, distributed-memory multiprocessor systems
`
`employing a plurality of nodes were interconnected to allow physical memory to
`
`be distributed among nodes; the memory was accessible as one global address
`
`space by any of the nodes in the system. Ex. 1010 at 1-2; Ex. 1006 at ¶13. In one
`
`1996 system, ConvEx SPP-1000, the individual nodes were described as being
`
`symmetric multiprocessors, connecting one or more processors, local memory, and
`
`a remote memory controller. Ex. 1010 at 2; Ex. 1006 at ¶13. The remote memory
`
`controller handled internode memory access using point-to-point transactions. Ex.
`
`1010 at 2; Ex. 1006 at ¶13.
`
`Some early SMP systems did not maintain cache consistency between nodes,
`
`leading to errors when one processor changed an original bit without updating any
`
`corresponding cached bits. Ex. 1006 at ¶14. In these systems, when such a change
`
`occurred, another processor would be unaware that the edit had been made and
`
`would continue to use the outdated cached memory line, as opposed to the updated
`
`memory line. Ex. 1006 at ¶14.
`
`To address these problems, early SMP systems relied on software and
`
`hardware protocols such as IBM’s “Direct Control Interface” (“DCI”) and
`
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`Channel-to-Channel Adapters (“CTCA”) to maintain cache consistency between
`
`nodes. Ex. 1006 at ¶15. However, as demand increased, performance was
`
`throttled by the software-controlled maintenance of cache consistency. Ex. 1006 at
`
`¶15. The performance restrictions imposed by software-based cache coherency
`
`maintenance drove
`
`the
`
`industry
`
`to continue exploring cache coherency
`
`maintenance techniques. Ex. 1006 at ¶15.
`
`In 1993, IBM introduced the Enterprise System Connectivity (ESCON)
`
`channel, which replaced copper cables with fiber optic point-to-point connections.
`
`Ex. 1008 at 1; Ex. 1006 at ¶16. ESCON introduced a new topology of control unit
`
`and channel attachment. Ex. 1006 at ¶16. ESCON control units and channels
`
`were “attached
`
`in a switched point-to-point arrangement. The switching
`
`capabilities allow[ed] multiple connections between channels and control units
`
`without requiring permanent physical connections.” Ex. 1008 at 1; Ex. 1006 at
`
`¶16.
`
`In 1994, The American National Standards Institute (ANSI) adopted a
`
`common standard for “Fibre Channel,” ISO 14165-1, which was provided for the
`
`standardization of a fiber optic network that could be configured as a point-to-point
`
`network. Ex. 1006 at ¶17.
`
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`Thus, symmetric shared-memory multiprocessor systems utilizing point-to-
`
`point connections were well known in the art before July 8, 1999, the filing date of
`
`the ’945 Patent. Ex. 1006 at ¶18.
`
`III.
`
`THE ’945 PATENT
`
`A.
`
`Overview
`
`The ’945 Patent is directed to a symmetric shared-memory multiprocessor
`
`memory system. Ex. 1001 Abstract; 2:59-60; 9:2; 10:1-2. In certain described
`
`embodiments, the ’945 Patent discloses a first set of processors, each coupled to a
`
`point-to-point connection. A memory is also coupled to a point-to-point
`
`connection. These point-to-point connections comprise a first set of point-to-point
`
`connections. A flow control unit (“FCU”), which includes a data switch, is
`
`coupled to the first set of point-to-point connections. The switch connects the
`
`processors to the memory and provides data paths between the processors and
`
`memory. Ex. 1001 9:3-13; Ex. 1006 at ¶¶19, 23.
`
`This collection of processors and memory may be considered a node. Ex.
`
`1006 at ¶24.
`
`The ’945 Patent is further directed to a second node, containing the same
`
`components as the first node: a second set of processors, a second memory, a
`
`second FCU including a second data switch, all coupled with a second set of point-
`
`to-point connections. Ex. 1001 9:14-25, Ex. 1006 at ¶24.
`
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`The ’945 Patent also claims a third point-to-point connection coupled to the
`
`first data switch of the first FCU and the second data switch of the second FCU,
`
`where the third connection provides data paths between the second memory and
`
`the first set of processors and between the first memory and the second set of
`
`processors. Ex. 1001 9:26-35; Ex. 1006 at ¶25.
`
`Figure 12, reproduced below, illustrates the system architecture (including
`
`the third point-to-point connections) described above:
`
`
`
`Ex. 1001 Fig. 12.
`
`Claim 1 is the one of two challenged independent claims of the ’945 Patent.
`
`Claim 1 recites:
`
`[a] A multi-processor shared memory system comprising:
`
`[b] a first set of point-to-point connections;
`
`[c] a first set of processors each coupled to one of the first set of point-
`to-point connections;
`
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`[d] a first memory coupled to one of the first set of point-to-point
`connections;
`
`[e] a first flow control unit including a first data switch coupled to the
`first set of point-to-point connections wherein the first data switch
`is configured to interconnect the first set of point-to-point
`connections to provide first data paths between the first memory
`and the first set of processors;
`
`[f] a second set of point-to-point connections;
`
`a second set of processors each coupled to one of the second set of
`point-to-point connections;
`
`a second memory coupled to one of the second set of point-to-
`point connections;
`
`a second flow control unit including a second data switch coupled
`to the second set of point-to-point connections wherein the second
`data switch is configured to interconnect the second set of point-to-
`point connections to provide second data paths between the second
`memory and the second set of processors; and
`
`[g] a third point-to-point connection coupled to the first data switch
`and to the second data switch wherein the first data switch is
`configured
`to
`interconnect
`the first set of point-to-point
`connections to the third point-to-point connection and the second
`data switch is configured to interconnect the second set of point-to-
`point connections to the third point-to-point connection to provide
`third data paths between the second memory and the first set of
`processors and between the first memory and the second set of
`processors.
`
`Ex. 1001 at 9:1-36; Ex. 1006 at ¶21.
`
`Claim 6 is the second of two challenged independent claims of the ’945
`
`Patent. Claim 6 recites:
`
`[a] A method of operating a multi-processor shared memory system
`comprising a first set of point-to-point connections, a first set of
`processors each coupled to one of the first set of point-to-point
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`connections, a first memory coupled to one of the first set of point-
`to-point connections, a first flow control unit including a first data
`switch coupled to the first set of point-to-point connections, a
`second set of point-to-point connections, a second set of processors
`each coupled to one of the second set of point-to-point
`connections, a second memory coupled to one of the second set of
`point-to-point connections, a second flow control unit including a
`second data switch coupled to the second set of point-to-point
`connections, and a third point-to-point connection coupled to the
`first data switch and to the second data switch, the method
`comprising:
`
`[b] interconnecting the first set of point-to-point connections in the
`first data switch to provide first data paths between the first
`memory and the first set of processors;
`
`[c] interconnecting the second set of point-to-point connections in the
`second data switch to provide second data paths between the
`second memory and the second set of processors; and
`
`[d] interconnecting the first set of point-to-point connections to the
`third point-to-point connection in the first data switch and
`interconnecting the second set of point-to-point connections to the
`third point-to-point connection in the second data switch to provide
`third data paths between the second memory and the first set of
`processors and between the first memory and the second set of
`processors.
`
`Ex. 1001 at 10:1-16; Ex. 1006 at ¶22.
`
`B.
`
`Prosecution History
`
`The application that issued as the ’945 Patent, Application No. 09/349,641
`
`(the “’641 Application”), was filed on July 8, 1999. Ex. 1001 Cover. The ’641
`
`Application claims priority to a series of continuation-in-part applications:
`
`Application No. 09/281,749, filed on March 30, 1999 (the “’749 Application”);
`
`12
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`Petition for Inter Partes Review of U.S. Patent No. 6,633,945
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`Application No. 09/163,294, filed on September 29, 1998 (the “’294
`
`Application”); and Application No. 08/986,430, filed on December 7, 1997 (the
`
`“’430 Application”). Ex. 1006 at ¶20.
`
`Originally, the ’641 Application was filed with only one claim, which was
`
`cancelled after the first office action and replaced with the claims that ultimately
`
`issued. Ex. 1012, pages 33-63, application as filed July 8, 1999. The second set of
`
`claims was initially rejected on July 15, 2002, for being directed to subject matter
`
`not described in the specification. Ex. 1012, pages 109-112, Office Action of July
`
`15, 2002. Applicants allegedly filed a response on October 15, 2002, but it was
`
`never received by the Patent Office. Ex. 1012, page 113, Response dated March
`
`12, 2003. In the follow-up response of March 12, 2003, the specification was
`
`amended, and Applicants argued that Figures 12-14 sufficiently assisted in
`
`allowing one of skill in the art to practice the invention. Ex. 1012, pages 121-122,
`
`Response dated March 12, 2003. Specifically, Applicants argued that “the level of
`
`skill in the art is very high, thus the corresponding teaching [of SMP systems] can
`
`be relatively concise. Ex. 1012, page 121, Response dated March 12, 2003.
`
`Further, Applicants argued that the connections within each node, the processors,
`
`memory and FCU were sufficiently defined in the specification that one of skill in
`
`the art would have been able to provide an additional connection between two
`
`nodes and pointed to the details from page 10, line 6 to page 11, line 39 and Figure
`
`13
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`12 to describe the details. Ex. 1012, page 121, Response dated March 12, 2003.
`
`The disclosures identified by the Applicant can be found in the issued ’945 Patent
`
`at column 6, line 62 to column 7 line 57.
`
`The Examiner never issued a substantive rejection of the second set of
`
`claims over prior art, and in response to the March 19, 2003 communication, the
`
`Examiner issued a notice of allowance. The ’945 Patent issued on October 14,
`
`2003.
`
`C.
`
`The ’945 Patent Is Not Entitled to a Priority Date Earlier than July 8,
`1999.
`
`“In order to gain the benefit of the filing date of an earlier application under
`
`35 U.S.C. § 120, each application in the chain leading back to the earlier
`
`application must comply with the written description requirement of 35 U.S.C.
`
`§ 112.” Lockwood v. Am. Airlines, Inc., 107 F.3d 1565, 1571 (Fed. Cir. 1997).
`
`Each limitation must be disclosed in the specification; it is insufficient for a
`
`limitation to be obvious in view of what is described. See Lockwood, 107 F.3d at
`
`1571-72; see also PowerOasis, Inc. v. T-Mobile USA, Inc., 522 F.3d 1299, 1306
`
`(Fed. Cir. 2008) (subject matter disclosed for first time in a continuation-in-part
`
`does not receive the benefit of the parent’s filing date). Entitlement to priority is
`
`decided on a claim-by-claim basis, not an element-by-element basis. See, e.g.,
`
`PowerOasis, 522 F.3d at 1306; Santarus, Inc. v. Par Pharm., Inc., 694 F.3d 1344,
`
`14
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`1352, 1354 (Fed. Cir. 2012); see also X2Y Attenuators, LLC v. Int’l Trade
`
`Comm’n, 757 F.3d 1358, 1366 (Fed. Cir. 2014).
`
`As noted above, the ’945 Patent purports to claim priority as a continuation-
`
`in-part of the ’749 Application, which is a continuation-in-part of the ’294
`
`Application, which is a continuation-in-part of the ’430 Application.
`
`Among other elements, Claim 1 of the ’945 Patent requires:
`
`a third point-to-point connection coupled to the first data switch and
`to the second data switch wherein the first data switch is configured to
`interconnect the first set of point-to-point connections to the third
`point-to-point connection and the second data switch is configured to
`interconnect the second set of point-to-point connections to the third
`point-to-point connection to provide third data paths between the
`second memory and the first set of processors and between the first
`memory and the second set of processors.
`
`Ex. 1001, Claim 1 (emphasis added); Ex. 1006 at ¶26.
`
`Claim 6 of the ’945 Patent similarly requires:
`
`a third point-to-point connection coupled to the first data switch and
`to the second data switch, the method comprising: . . . interconnecting
`the first set of point-to-point connections to the third point-to-point
`connection in the first data switch and interconnecting the second set
`of point-to-point connections to the third point-to-point connection in
`the second data switch to provide third data paths between the second
`memory and the first set of processors and between the first memory
`and the second set of processors.”
`
`Ex. 1001, Claim 6 (emphasis added); Ex. 1006 at ¶26.
`
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`The earliest disclosures concerning the claimed “third point-to-point
`
`connection”1 appeared in the ’641 Application when it was filed on July 8, 1999.
`
`Ex. 1006 at ¶28. The portions of ’945 Patent disclosure that the Applicant asserted
`
`supported the claimed “third point-to-point connection” are found at col. 6, line 62
`
`to col. 8, line 54 in the specification and FIG. 12 in the drawings (corresponding to
`
`page 10, line 6-page 11 line 39 and Fig. 12 of the as-filed specification). Ex. 1012,
`
`page 121, Response to Office Action dated March 12, 2003 (identifying page 10,
`
`line 6 to page 11, line 39, original Claim 1, and Figure 12); ; Ex. 1006 at ¶28.
`
`These disclosures are found nowhere in the ’749 Application, the ’294 Application,
`
`or the ’430 Application. Ex. 1006 at ¶¶27-28. Nor does the ’749 Application, the
`
`’294 Application, or the ’430 Application provide separate support for the claimed
`
`“third point-to-point connection.” Ex. 1006 at ¶27.
`
`1 Petitioner does not concede that any disclosure(s) relevant to the “third point-to-
`
`point connection” were sufficient under 35 U.S.C. § 112, which is not at issue here.
`
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`Accordingly, Petitioner submits that the appropriate priority date for Claims
`
`1 and 6 of the ’945 Patent is July 8, 1999.2 Ex. 1006 at ¶29.
`
`IV.
`
`GROUNDS FOR STANDING (37 C.F.R. § 42.104(A))
`
`Petitioner certifies that: (1) the ’945 Patent, issued on October 14, 2003, is
`
`available for IPR; (2) Petitioner is not barred or estopped from requesting an IPR
`
`on the Grounds identified herein; and (3) Petitioner has not filed a complaint
`
`relating to the ’945 Patent. This Petition is filed in accordance with 37 C.F.R.
`
`§ 42.106(a). Concurrently filed herewith is a Power of Attorney and an Exhibit
`
`List per 37 C.F.R. § 42.10(b) and § 42.63(e), respectively.
`
`2 Hagersten is prior art under 35 U.S.C. § 102(b) if the Board agrees with
`
`Petitioner’s assertion about the priority date for Claims 1 and 6 of the ’945 Patent;
`
`Hagersten is prior art under 35 U.S.C. § 102(e) if the Board does not adopt
`
`Petitioner’s proposed priority date. Sharma and Ekanadham are prior art under
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`102(e) whether or not the Board adopts Petitioner’s priority date for Claims 1 and
`
`6 of the ’945 Patent.
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`17
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`Petition for Inter Partes Review of U.S. Patent No. 6,633,945
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`V.
`
`PAYMENT OF FEES (37 C.F.R. §§ 42.15 AND 42.103)
`
`In accordance with 37 C.F.R. § 42.15 and § 42.103, Petitioner authorizes the
`
`USPTO to charge any required fees to Deposit Account 02–1818. Please indicate
`
`docket number 1402767.00005 on the account statement if such charges occur.
`
`VI.
`
`MANDATORY NOTICES (37 C.F.R. § 42.8(B))
`
`A.
`
`Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))
`
`Petitioner certifies that the real-party-in-interest is NetApp, Inc., having a
`
`principal place of business at 495 East Java Drive, Sunnyvale, California 94089.
`
`B.
`
`Related Matters (37 C.F.R. § 42.8(b)(2))
`
`The ’945 Patent has been asserted against Petitioner in an ongoing litigation,
`
`Intellectual Ventures I, LLC, Intellectual Ventures II, LLC v. NetApp, Inc., Case
`
`No. 1:16-cv-10868-IT (D. Mass.) (“the Litigation”). The Litigation may affect, or
`
`may be affected by, a decision in this proceeding. A copy of the complaint in the
`
`Litigation is provided as Ex. 1005. The complaint was served on Petitioner on
`
`May 17, 2016.
`
`18
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`Petition for Inter Partes Review of U.S. Patent No. 6,633,945
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`C.
`
`Lead and Backup Counsel and Service (37 C.F.R. § 42.8(b)(3)-(4))
`
`Lead Counsel
`Benjamin E. Weed
`Reg. No. 65,939
`K&L Gates LLP
`70 W. Madison St., Suite 3100
`Chicago, IL 60602
`benjamin.weed.PTAB@klgates.com
`T: (312) 781-7166
`F: (312) 827-8152
`
`Backup Counsel
`Brian J. Ankenbrandt
`Reg. No. 41,586
`K&L Gates LLP
`630 Hansen Way
`Palo Alto, CA 94304
`brian.ankenbrandt@klgates.com
`T: (650) 798-6725
`F: (650) 798-6701
`
`Backup Counsel
`Erik J. Halverson
`Reg. No. 73,552
`K&L Gates LLP
`70 W. Madison St., Suite 3100
`Chicago, IL 60602
`erik.halverson@klgates.com
`T: (312) 807-4240
`F: (312) 345-8529
`
`Petitioner consents to electronic service by email.
`
`VII.
`
`PERSON OF ORDINARY SKILL IN THE ART
`
`A person of ordinary skill in the art (“POSA”) is a hypothetical person who
`
`is presumed to know the relevant prior art. See Gnosis S.P.A et al. v. S. Ala. Med.
`
`Sci. Foundation, Case IPR2013-00116, Paper 68 at 9, 37 (PTAB June 20, 2014).
`
`A POSA has ordinary creativity, is not an automaton, and is capable of combining
`
`19
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`teachings of the prior art. Id. (citing KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398,
`
`420-421 (2007)).
`
`With respect to the ’945 Patent, Petitioner submits that a POSA would have
`
`had at least a bachelor’s degree in computer science or electrical engineering or its
`
`equivalent and at least four years of experience designing, testing or implementing
`
`multi-processing computer systems. Ex. 1006 at ¶37. Such a POSA would have
`
`had knowledge of computer networking systems, more specifically, the software
`
`and hardware options available for symmetric multiprocessor systems, and would
`
`have understood how to search available literature for relevant publications. Ex.
`
`1006 at ¶¶38-39.
`
`VIII.
`
`CLAIM CONSTRUCTION
`
`A.
`
`Broadest Reasonable Interpretation Standard
`
`In accordance with 37 C.F.R. § 42.100(b), the challenged claims must be
`
`given their “broadest reasonable construction in light of the specification” of the
`
`’945 Patent. 37 C.F.R. § 42.100(b); Cuozzo Speed Techs., LLC v. Lee, Slip Op.
`
`No. 15-446, at 20 (U.S. June 20, 2016). Under this broadest reasonable
`
`interpretation standard, claim terms are generally given their ordinary and
`
`customary meaning, as would be understood by a POSA in the context of the entire
`
`disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). If a
`
`special definition for a claim term is proffered, it must be described in the
`
`20
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`specification “with reasonable clarity, deliberateness, and precision.” In re
`
`Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). Absent such a special definition,
`
`limitations are not to be read from the specification into the claims. See In re Van
`
`Genus, 988 F.2d 1181, 1184 (Fed. Cir. 1993).
`
`Where not specified, Petitioner asserts that a POSA would have understood
`
`all the terms of each of the claims of the ’945 Patent to have their ordinary and
`
`customary meaning.3
`
`B.
`
`Point-to-Point Connection(s)
`
`Claim 1 recites a first set of point-to-point connections and a first set of
`
`processors. Ex. 1001 9:3-4. Each processor in the first set of processors is coupled
`
`to one of the first set of point-to-point connections. Ex. 1001 9:4-5. Further, a
`
`memory is coupled to one of the first set of point-to-point connections. Ex. 1001
`
`9:6-7. Claim 1 also requires that a first data switch is coupled to the first set of
`
`point-to-point connections, to provide data paths between the memory and the
`
`3 Any contention by the patent owner that claim terms should have a special
`
`meaning should be disregarded unless the patent owner also moves to amend its
`
`claims as permitted to expressly recite that meaning. (See 77 Fed. Reg. 48764 at
`
`II.B.6 (August 14, 2012)).
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`21
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`processors in what can be considered the first node. Ex. 1001 9:8-13. The second
`
`set of point-to-point connections and coupled components is identical to the first
`
`set and can be considered a second node. Ex. 1001 9:14-25. Finally, a third point-
`
`to-point connection couples the first and second switches. Ex. 1001 9:26-27.
`
`Within each node, therefore, the connection between the data switch and a memory
`
`and the connection between the data switch and a processor each must be a “point-
`
`to-point connection”, as must be the connection between the switches of different
`
`nodes. Ex. 1006 at ¶21. Claim 6 uses similar terminology to describe connections
`
`between among processors and between nodes. Ex. 1001 10:1-15; Ex. 1006 at ¶22.
`
`Within a given node, the ’945 Patent describes interconnects 112, 113 and
`
`114 as “Point-to-Point (PP)” connections, as indicated in the red boxes below. Ex.
`
`1001 2:67-3:1; Figure 2; Figure 3. In the embodiment shown in Figure 3, item 112
`
`indicates a direct connection between the “Channel Interface Block (CIB)” of a
`
`“Dual CPU/Cache Interface” (which is pictured connecting to two CPUs) at one
`
`end and to the FCU 220 at the other end. See Ex. 1001 5:38-40 (“CIBs are the
`
`transmit and receive interface for the Channel connections to and from the FCU”).
`
`Item 114 indicates a direct connection between the CIB of a Memory Interface
`
`Control (which is pictured connecting to two SDRAMs) at one end and to the CIB
`
`of a Memory Channel Control in the FCU at the other end. Thus, in this
`
`embodiment of the ’945 Patent, the disclosed point-to-point connection may be
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`coupled to a CPU, memory or data switch via an interface control device having a
`
`CIB. The ’945 Patent further discloses a “Transaction Controller (TC)” that “acts
`
`as a central system-serialization and cache coherence point,” through which all
`
`requests in the system must pass. Ex. 1001 4:5-11. In sum, in the context of at
`
`least the embodiment of Figs. 2 and 3 of the ’945 Patent, the existence of
`
`intervening components such as an interface controller, a CIB or a Transaction
`
`Controller still allows for a connection between a CPU or memory and a data
`
`switch to be considered “point-to-point.”
`
`Ex. 1001 Fig 3.
`
`Concerning the third point-to-point connection between a data switches in
`
`separate nodes, the ’945 Patent states that “[t]he interconnection between FCUs are
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`point to point and fully connected. Each FCU has direction [sic, direct, see Ex.
`
`1006 at ¶¶42-44] connection to all other FCUs.” Ex. 1001 7:14-16; Fig. 12. Fig.
`
`12 confirms the recited direct connections between each FCU and all other FCUs,
`
`as it illustrates three bi-directional arrows connecting each FCU to the other three
`
`FCUs:
`
`
`
`Ex. 1001 Fig. 12; Ex. 1006 at ¶44.
`
`Thus, at least in the context of the claimed third point-to-point connection,
`
`the ’945 Patent discloses the use of individual, direct connections between the
`
`nodes. Nothing in the portions of the specification the Applicants identified as
`
`relevant to the third point-to-point connection (i.e., Ex. 1001 6:62-8:54 and Fig. 12,
`
`as discussed in Section II.DIII.C) describes or illustrates how such connections are
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`coupled specifically to the data switches in the respective FCUs for different
`
`nodes, as required by claims 1 and 6.
`
`Because Applicants used the same terminology for all three “point-to-point”
`
`connections in the claims, the term should be construed at least broadly enough to
`
`encompass any of the three point-to-point connections as disclosed. See, e.g.,
`
`On–Line Techs., Inc. v. Bodenseewerk Perkin–Elmer GmbH, 386 F.3d 1133, 1138
`
`(Fed. Cir. 2004) (“a claim interpretation that excludes a preferred embodiment
`
`from the scope of the claim is rarely, if ever, correct.”).
`
`Moreover, the specification of the ’945 Patent incorporates by reference a
`
`related application that issued as U.S. Patent No. 6,065,077 (“the ’077 Patent,” Ex.
`
`1015) (Ex. 1001 1:5-20), which defines a point-to-point connection as follows:
`
`A channel 210 is a point-to-point connection between the FCU
`212 and either a CIU 208, BBU 206 or MCU 204. A point-to-
`point connection is a statically-configured communication link
`between two devices. The channel 210 provides a direct
`communication path and is only used by the two connected
`devices. As such, the channel 210 differs from most common
`types of shared or dynamically-configurable interconnect
`structures such as a bus, network, ring, crossbar switch
`network, and the like.
`
`Ex. 1015 12:15-23; see also Ex. 1001 at 1:4-10; 6:31-36.
`
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`Considering the relevant disclosures in the ’945 Patent, the disclosures
`
`incorporated by reference into the ’945 Patent, and the contemporaneous
`
`understanding of one of ordinary skill in the art at the time of filing, Petitioner
`
`submits that the broadest reasonable construction of the term “point-to-point
`
`connection” is: a statically configured communications link between two devices.
`
`See Ex. 1006 at ¶¶41, 45-46.
`
`IX.
`
`STATEMENT OF THE PRECISE RELIEF REQUESTED AND THE
`REASONS THEREFOR (37 C.F.R. § 42.22(A) AND 42.104(B))
`
`Petitioner requests the institution of IPR and the cancellation of Claims 1
`
`and 6 of the ’945 Patent on the Grounds outlined in the table below.
`
`Ground 35 U.S.C. Relied-On References
`1
`§ 103
`U.S. Patent No. 6,085,295 to Ekanadham et al.
`(“Ekanadham”) (Ex. 1003) in view of U.S.
`Patent No. 5,754,877 to Hagersten et al.
`(“Hagersten”) (Ex. 1004)
`Ekanadham (Ex. 1003)
`U.S. Patent No. 6,055,605 to Sharma et al.
`(“Sharma”) (Ex. 1002) in view of Hagersten
`(Ex. 1004)
`Sharma (Ex. 1002)
`
`2
`3
`
`4
`
`§ 103
`§ 103
`
`§ 103
`
`Claims
`1, 6
`
`1, 6
`1, 6
`
`1, 6
`
`Per 37 C.F.R. § 42.6(c), copies of the references are filed herewith.
`
`Additionally, Petitioner provi
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