UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
` 
`
`
`
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner v.
`POLARIS INNOVATIONS LTD.,
`Patent Owner
`
`
`
`
`
`
`
`
`
`Case No. IPR2017-00238
`Patent 6,157,589
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 6,157,589
`
`
`
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`TABLE OF CONTENTS
`
`I. 
`
`V. 
`
`INTRODUCTION AND STATEMENT OF RELIEF REQUESTED (37
`C.F.R. §42.22(a)) ............................................................................................... 1 
`GROUNDS FOR STANDING (37 C.F.R. §42.104(a)) .................................... 1 
`II. 
`III.  MANDATORY NOTICES (37 C.F.R. §42.8(a)(1)) ......................................... 1 
`A. 
`Real Party-In-Interest (37 C.F.R. §42.8(b)(1)) ........................................ 1 
`B. 
`Identification of Related Matters (37 C.F.R. §42.8(b)(2)) ...................... 1 
`C. 
`Counsel and Service Information (37 C.F.R. §§42.8(b)(3) & (b)(4)) ..... 2 
`D. 
`Payment of fees (37 C.F.R. §42.103) ...................................................... 2 
`IV.  REQUEST FOR REVIEW ................................................................................ 2 
`A. 
`Claims To Be Reviewed .......................................................................... 2 
`B. 
`Each Of The Cited References Is Available As Prior Art ....................... 3 
`C. 
`Identification Of Challenge ..................................................................... 3 
`BACKGROUND ................................................................................................ 4 
`A.  Description of the ’589 Patent .................................................................. 4 
`B. 
`Prosecution History .................................................................................. 6 
`C. 
`Level of Ordinary Skill in Art ................................................................. 7 
`D. 
`State of the Art ......................................................................................... 7 
`VI.  CLAIM CONSTRUCTION ............................................................................. 10 
`VII.  THERE IS A REASONABLE LIKELIHOOD THAT CLAIMS 11 AND 12
`ARE UNPATENTABLE ................................................................................. 11 
`A.  Ground I - Obviousness of claims 11 and 12 based on Meritt (USPN
`6,243,797) .............................................................................................. 11 
`1. 
`Claim 11 ...................................................................................... 11 
`2. 
`Claim 12 ...................................................................................... 25 
`Ground II - Obviousness of claims 11 and 12 based on Merritt (USPN
`6,243,797) in view of Nagai .................................................................. 27 
`1. 
`Claim 11 ...................................................................................... 28 
`2. 
`Claim 12 ....................................................................................... 35 
`Ground III - Obviousness of claims 11 and 12 based on Nagai (USPN
`5,448,528) .............................................................................................. 37 
`
`B. 
`
`C. 
`
`i
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`Claim 11 ...................................................................................... 37 
`1. 
`Claim 12 ....................................................................................... 44 
`2. 
`VIII.  CONCLUSION ................................................................................................ 45 
`
`
`ii
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
`EXHIBIT LIST
`
`Description
`Exhibit No.
`KINGSTON-1001 U.S. Patent No. 6,157,589 (’589 Patent)
`KINGSTON-1002 File History of U.S. Patent No. 6,157,589
`KINGSTON-1003 Declaration of Dr. Subramanian
`KINGSTON-1004 Curriculum Vitae of Dr. Subramanian
`KINGSTON-1005 U.S. Patent No. 6,243,797 B1 (“Merritt”)
`KINGSTON-1006 U.S. Patent No. 5,448,528 (“Nagai”)
`KINGSTON-1007 JEDEC Standard 21-C Release 4
`Plaintiff Polaris Innovations Limited’s Preliminary
`Disclosure Of Asserted Claims And Infringement
`Contentions, Exhibit 1, Preliminary Infringement Claim
`Chart for U.S. Patent No. 6,157,589 (“589 Patent”)
`Polaris Innovations Ltd. v. Kingston Tech. Co., Inc., Case
`No. 8:16-cv-300-CJC (C.D. Cal. July 8, 2016)
`
`KINGSTON-1008
`
` 
`
`
`
`iii
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`I.
`
`INTRODUCTION AND STATEMENT OF RELIEF REQUESTED (37
`C.F.R. §42.22(A))
`Kingston Technology Company, Inc. (“Petitioner”) hereby petitions for
`
`institution of inter partes review of U.S. Patent No. 6,157,589 (the “’589
`
`Patent”) (Ex. 1001). The ’589 Patent issued on December 5, 2000. Polaris
`
`Innovations Limited (“Patent Owner”) is the assignee of record with the
`
`USPTO. Petitioner respectfully requests cancellation of claims 11 and 12 of the
`
`’589 Patent based on the grounds of unpatentability herein. The prior art and
`
`other evidence offered with this Petition establishes that all elements in the
`
`challenged claims of the ’589 Patent were well known as of the earliest alleged
`
`priority date, and that the claimed methods and systems recited in the ’589 Patent
`
`are obvious.
`
`II. GROUNDS FOR STANDING (37 C.F.R. §42.104(A))
`Petitioner certifies that the ’589 Patent is available for review under 35
`
`U.S.C. § 311(c) and that Petitioner is not estopped from requesting an inter
`
`partes review challenging claims 11 and 12 on the grounds identified herein.
`
`III. MANDATORY NOTICES (37 C.F.R. §42.8(A)(1))
`A. Real Party-In-Interest (37 C.F.R. §42.8(b)(1))
`Petitioner Kingston Technology Company, Inc., is the real party in interest.
`
`B.
`Identification of Related Matters (37 C.F.R. §42.8(b)(2))
`The following matter would be affected by a decision in this proceeding:
`
`1
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`Polaris Innovations Ltd. v. Kingston Tech. Co., Inc., Case No. 8:16-cv-300
`
`(C.D. Cal.), filed February 19, 2016. Patent Owner has asserted claims 11 and 12
`
`of the ’589 patent against Petitioner in this matter. Petitioner was served with the
`
`complaint in that litigation on February 25, 2016.
`
`C. Counsel and Service Information (37 C.F.R. §§42.8(b)(3) & (b)(4))
`Petitioner designates the following Lead and Back-up Counsel.
`
`Concurrently filed with this Petition is a Power of Attorney per 37 C.F.R. §
`
`42.10(b). Service via hand-delivery may be made at the postal mailing address
`
`below. Petitioner consents to electronic service by e-mail.
`
`Lead Counsel
`David Hoffman (Reg. No. 54,174)
`Fish & Richardson P.C.
`3200 RBC Plaza
`60 South Sixth Street
`Minneapolis, MN 55402
`Tel: (512) 472-8154
`Fax: (202) 783-2331
`IPR37307-0005IP1@fr.com
`
`
`Back-Up Counsel
`Martha Hopkins (Reg. No. 46,277)
`Law Offices of S. J. Christine Yang
`17220 Newhope Street
`Suites 101-102
`Fountain Valley, CA 92708
`Tel: (714) 641-4022
`Fax: (714) 641-2082
`IPR@sjclawpc.com
`
`
`D.
`Payment of fees (37 C.F.R. §42.103)
`Petitioner authorizes the Patent and Trademark Office to charge Deposit
`
`
`
`Account No. 06-1050 for the petition fee and for any other required fees.
`
`IV. REQUEST FOR REVIEW
`A. Claims To Be Reviewed
`Petitioner requests review of claims 11 and 12 of the ’589 patent.
`
`2
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`B.
`Each Of The Cited References Is Available As Prior Art
`Each of the references cited in this petition qualifies as prior art. All of the
`
`references have an effective filing date prior to the earliest potential effective filing
`
`date of the ’589 patent of June 30, 1998.
`
`● U.S. Patent No. 6,243,797 to Merritt (“Merritt” “or “’797 patent”) (Ex.1005)
`
`was filed on February 18, 1997 and issued on June 5, 2001. Accordingly,
`
`the Merritt is prior art under 35 U.S.C. §102(a), §102(b), and §102(e).
`
`● U.S. Patent No. 5,448,528 to Nagai (“Nagai” or “’528 patent”) (Ex. 1006)
`
`was filed September 19, 1994 and issued September 5, 1995. Accordingly,
`
`Nagai is prior art under 35 U.S.C. §102(a), §102(b), and §102(e).
`
`C.
`Identification Of Challenge
`The ’589 patent is unpatentable based on 35 U.S.C. §§103. In particular, the
`
`claims are invalid on the following grounds:
`
`1. Merritt (USPN 6,243,797) renders claims 11 and 12 of the ’589 patent
`
`obvious under §103.
`
`2. Merritt (USPN 6,243,797) in view of Nagai (USPN 5,448,528) renders
`
`claims 11 and 12 of the ’589 patent obvious under §103.
`
`3. Nagai (USPN 5,448,528) renders claims 11 and 12 of the ’589 patent
`
`obvious under §103.
`
`3
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`Petitioner evaluates the scope and content of the prior art and, any differences
`
`between the prior art and the claims, and the level of skill of a person of ordinary
`
`skill in the art in accordance with Graham v. John Deere Co., 383 U.S. 1 (1966)
`
`and KSR int’l C. v. Teleflex, Inc., 550 U.S. 398, 417 (2007) (“[A] court must ask
`
`whether the improvement is more than the predictable use of prior art elements
`
`according to their established functions”) (emphasis added).
`
`A detailed explanation of why claims 11 and 12 are invalid is provided
`
`below, including the supporting evidentiary declaration of Dr. Subramanian (Ex.
`
`1003).
`
`V. BACKGROUND
`A. Description of the ’589 Patent
`The ’589 Patent relates to a Dynamic Semiconductor Random Access
`
`Memory (“DRAM”) device and a method for initializing a DRAM device. Ex.
`
`1001, 2:7-14. The device and method purport to solve a problem in the prior art by
`
`providing a way for circuits to be “reliably held in a desired defined state” while
`
`the device is powering on. Id. at 1:22-35. This purported advancement is achieved
`
`by following a particular initialization sequence. Id. To perform the initialization
`
`sequence, the device contains an initialization circuit having a control circuit and
`
`an enable circuit. Id. at 2:15-36.
`
`4
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`As seen in Fig. 1 below, once the initialization circuit performs a switching-
`
`on operation and the internal voltage regulation and detection circuit 5 detects that
`
`the supply voltage at input 6 is stabilized, detection circuit 5 supplies a supply
`
`voltage stable signal (POWERON) to the enable circuit 9. Id. at 3:42-4:23. The
`
`enable circuit 9 receives the supply voltage stable signal (POWERON) at input 11
`
`and various command signals at input 10. Id. Once the enable circuit receives the
`
`supply voltage stable (POWERON) signal and the various command signals in the
`
`correct sequence, it outputs an enable signal (CHIPREADY) at output 12. Id. The
`
`enable signal (CHIPREADY) unlatches the control circuit 13. Id.
`
`
`
`Fig. 2, below, shows an exemplary version of enable circuit 9 in more detail.
`
`It contains “three bistable multivibrator stages 14, 15 and 16 each having a set
`
`input S, a reset input R, and also an output Q.” Id. at 4:24-58. The supply voltage
`
`stable signal (POWERON) as described in reference to Fig. 1 is applied to the
`
`5
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`enable circuit at input 11. Id. The command signals described above at input 10
`
`are shown in more detail here. Id. Input 10A receives a preparation command for
`
`word line activation, called PRE or PRECHARGE. Id. Input 10B receives a
`
`refresh command, called ARF or AUTOREFRESH. Id. Input 10C receives a
`
`loading configuration register command, called MRS or MODE-REGISTER-SET.
`
`Id. The enable signal (CHIPREADY) is output at output 12 after “a predetermined
`
`chronological initialization sequence of the command signals PRE, ARF and MRS
`
`and activation of the [supply voltage steady] POWERON signal.” Id.
`
`B.
`Prosecution History
`On June 30, 1999, the ’589 Patent was filed as Application No.
`
` 
`
`09/343,431 (“the ’431 Application”) entitled “Dynamic Semiconductor Memory
`
`Device and Method for Initializing a Dynamic Semiconductor Memory Device.”
`
`6
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`The ’431 Application claims priority to German Patent Application 198 29 287,
`
`filed June 30, 1998.
`
`As with the issued patent, the ’431 Application contained thirteen claims.
`
`After various non-substantive formalities, the examiner allowed the claims on July
`
`17, 2000. In the Notice of Allowability, the examiner indicated that the claims
`
`were allowed because the prior art failed to disclose the enable circuit as described
`
`in the claims. Ex. 1002 at 91.
`
`C. Level of Ordinary Skill in Art
`Petitioner asserts that the level of ordinary skill in the art is a person with a
`
`Masters’ of Science degree in Electrical Engineering and at least two years of
`
`experience working in the field of semiconductor memory design. Subramanian
`
`Decl. at ¶17.
`
`D.
`State of the Art
`DRAM utilizing an initialization circuit controlling a switching–on
`
`operation of the DRAM and its circuit components was well known in the art long
`
`before the priority date of the ’589 patent. As recognized in the ’589 patent itself,
`
`the JEDEC standard specified the optimum initialization sequence for the
`
`switching-on of the DRAM. See Ex. 1001 at 1:21-2:5; see also Ex. 1007, JEDEC
`
`21-C Standard at 115; Ex. 1003, Subramanian Decl. at ¶19.
`
`7
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`It was also well known from this prior art initialization sequence that a stable
`
`voltage needed to be maintained for a minimum of 200 microseconds before
`
`further operation by the DRAM. Ex. 1007, JEDEC 21-C Standard at 115; Ex.
`
`1003, Subramanian Decl. at ¶19. Moreover, as shown in the figures below,
`
`multiple patents disclosed a DRAM controller capable of issuing the commands
`
`specified in the initialization sequence, including a refresh signal sent both during
`
`and after voltage stabilization, a clock enable signal, and a mode register set signal,
`
`which when sent in the proper sequence could initialize the DRAM device and
`
`provide for its proper operation. See Ex. 1005 at Fig. 1 (disclosing a Control Logic
`
`28 capable of generating a CKE and SYSRESET* signal); Ex. 1006 at Fig. 1
`
`(disclosing a Mode Register Set (“MRS”) capable of programming certain DRAM
`
`parameters); Ex. 1003 Subramanian Decl. at ¶19.
`
`8
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`Merritt, Ex. 1005 at Fig. 1:
`
` 
`
`9
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`Nagai, Ex. 1006 at Fig. 1:
`
` 
`
`VI. CLAIM CONSTRUCTION
`Under 37 C.F.R. § 42.100(b), a claim in inter partes review is given the
`
`“broadest reasonable construction” in light of the specification. In re Cuozzo
`
`Speed Techs., LLC., 793 F.3d 1268, 1276 (Fed. Cir. 2015). Because the standard
`
`for claim construction at the Patent Office is different (i.e., broader) from that used
`
`in a U.S. district court litigation, see In re American Academy of Science Tech
`
`Center, 367 F.3d 1359, 1364, 1369 (Fed. Cir. 2004), Petitioner expressly reserves
`
`the right to argue a different claim construction in the district court proceeding for
`
`any term of the ’077 Patent, as appropriate.
`
`10
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`Petitioner submits, for purposes of this IPR only, that the broadest
`
`reasonable interpretation should govern the meaning of the claim terms.
`
`Moreover, Patent Owner has asserted in district court that the meaning of certain
`
`claim terms is broad enough to encompass certain functionalities. See generally
`
`Ex. 1008. While Petitioner disagrees with Patent Owner’s assertions, Petitioner
`
`submits that the breadth of these claims, under the broadest reasonable
`
`interpretation for purposes of IPR, must at least encompass the same functionalities
`
`identified by Patent Owner (as described in greater detail below).
`
`VII. THERE IS A REASONABLE LIKELIHOOD THAT CLAIMS 11 AND
`12 ARE UNPATENTABLE
`As described below, Merritt and Nagai, either alone or in combination with
`
`each other render claims 11 and 12 of the ’589 patent obvious under §103.
`
`A. Ground I - Obviousness of claims 11 and 12 based on Meritt
`(USPN 6,243,797)
`1. CLAIM 11
`a)
`An improved method for initializing a dynamic
`semiconductor memory device of a random access
`type via an initialization circuit controlling a
`switching-on operation of the dynamic semiconductor
`memory device and of its circuit components, the
`improvement which comprises:
`Patent Owner has asserted that the preamble is satisfied if a DRAM
`
`controller which controls the DRAM (including initialization) is present:
`
`To the extent that the preamble of Claim 11 is a limitation, the 589
`
`11
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
`Accused Products initialize a dynamic semiconductor memory device
`of a random access type (specifically DDR3 DRAM devices) via an
`initialization circuit in a DDR3 controller, controlling a switching-on
`operation of the DRAM and of its circuit components . . . All
`Kingston Accused 589 Products include one of: a Phison 3108 or
`3110 controller, or a Marvell 88SS9293 or 88SS1074 controller . . .
`Each such controller includes within it a DDR3 controller as an
`internal functional block. The DDR3 controller controls (including
`initialization) DDR3 DRAM that is external to the Phison or Marvell
`controller and internal to the 589 Accused Product.”).
`
`Ex. 1008 at 1-8 (emphasis added). Petitioner disagrees that the preamble
`
`should have this construction under the narrower claim construction standard in
`
`district court. However, given Patent Owner’s assertions and the broadest
`
`reasonable interpretation of this claim limitation in the IPR context, the preamble
`
`must be satisfied through the presence of a DRAM controller, that controls the
`
`switching-on operation of the DRAM and its circuit components.
`
`Merritt discloses a DRAM controller. See e.g. Ex. 1005 at Fig 1 (illustrating
`
`“Control Logic 28”); see also Ex. 1003, Subramanian Decl. at ¶28:
`
`12
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`Merritt discloses that at least Control Logic 28 functions to control the
`
`circuitry of the DRAM, by generating (for example) the SYSRESET signal as well
`
`as CLK, CL2, and CL3 signals. Ex. 1005 at Fig. 1, 4:5-8 (“Control logic 28
`
`controls the various circuitry of SDRAM 10 based on decoded commands such as
`
`during controlled reads or Writes from or to bank 0 memory array 22 and bank 1
`
`memory array 24.”); see also Ex. 1003, Subramanian Decl. at ¶29.
`
`Figure 1 of Merritt illustrates that the Control Logic 28 generates the
`
`SYSRESET signal:
`
`13
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`Merritt explains that by producing the SYSRESET signal and other signals,
`
`the Control Logic 28 is able to control various functions of the DRAM. For
`
`example, Merritt discloses that “when the system reset signal SYSRESET* is
`
`provided all of the data register circuits, including data register circuit 230, are
`
`cleared. Also, NOR gate 604 is disabled, causing its output to become a logic low
`
`level which resets the timing signal generator 210 in the manner that has been
`
`described.” Ex. 1005 at 14:37-41. Merritt further describes how the RESET*
`
`signal controls the functionality of the DRAM:
`
`The reset circuit 302 responds to an active low reset signal RESET* to
`initialize the circuits of the three-phase timing signal generator 210.
`Digressing, referring to FIG. 6, the reset signal RESET* is produced
`by a NOR gate 604 and becomes active low state whenever a system
`reset signal SYSRESET* is produced or when programmed latency is
`
`14
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
`changed, as indicated by the disabling of a NOR gate 602 by either
`one of its input signals CL2 or CL3 becoming a logic high level as
`will be described. The system reset signal SYSRESET* is provided at
`powerup at the start of a write operation or in response to precharging
`of both memory banks at the end of a read function.
`
`Ex. 1005 at 7:26-37. Moreover, it is inherent and required to have
`
`initialization circuitry that can control the switching-on operation of the DRAM, as
`
`without such circuitry, the DRAM could not turn on. See Ex. 1003, Subramanian
`
`Decl. at ¶30. Merritt further explains that “[p]ower-up and initialization functions
`
`of the SDRAM 10 are conducted in the conventional manner,” thus disclosing a
`
`DRAM controller that controls the initialization of the DRAM. See Ex. 1005 at
`
`4:22-24; see also Ex. 1003, Subramanian Decl. at ¶30.
`
`b)
`
`supplying, via the initialization circuit, a supply
`voltage stable signal once a supply voltage has been
`stabilized after the switching-on operation of the
`dynamic semiconductor memory device; and
`Patent Owner has asserted that a “supply voltage stable signal” within the
`
`meaning of this claim is present when an “Active Low synchronous Reset Signal,
`
`/RESET,” is generated:
`
`When Kingston (in testing and using the Kingston 589 Accused
`Products) or when other users of the Kingston 589 Accused Products
`use and turn the 589 Accused Products on, the Phison or Marvell
`controller chips supply a voltage stable signal (for example, the
`Active Low synchronous Reset signal, /RESET . . . The /RESET
`
`15
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
`signal must be maintained for 200μs with stable power . . . The
`/RESET signal is supplied by the controller chip to the DDR3 DRAM
`chip.
`
`Ex. 1008 at 9-13. Petitioner disagrees that this limitation should be so
`
`construed under the narrower claim construction standard in district court.
`
`However, given Patent Owner’s assertions and the broadest reasonable
`
`interpretation of this claim in the IPR context, a “supply voltage stable signal”
`
`within the meaning of this claim is satisfied where an “Active Low synchronous
`
`Reset Signal, /RESET,” is generated.
`
`Merritt discloses generating an “Active Low synchronous Reset Signal,
`
`/RESET,” sent to a DRAM. See Ex. 1005 at 7:26-28 (“The reset circuit 302
`
`responds to an active low reset signal RESET* to initialize the circuits of the three-
`
`phase timing signal generator 210.”); see also Ex. 1003, Subramanian Decl. at ¶33.
`
`Because Merritt discloses generating the RESET* signal, it discloses a “supply
`
`voltage stable signal” that is supplied once the “supply voltage has been stabilized
`
`after the switching-on operation of the dynamic semiconductor memory device,”
`
`under the BRI of this claim limitation.
`
`To the extent that Patent Owner’s assertions that holding a reset signal for
`
`200 microseconds is significant in some way to indicate stability of the supply
`
`voltage, it would have been obvious for one of ordinary skill to maintain Merritt’s
`
`RESET* signal until the supply voltage stabilized at least because the system
`
`16
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`would not function properly if the supply voltage was not stable. Ex. 1003,
`
`Subramanian Decl. at ¶34. Furthermore, doing so would have been well within the
`
`ordinary skill of the art, as evident from the JEDEC specification which is cited in
`
`the ’589 patent itself as describing DRAM techniques already known to those of
`
`ordinary skill of the art. See Ex. 1001 at 1:21-2:5 (“According to the JEDEC
`
`standard for SDRAM semiconductor memories, a recommended initialization
`
`sequence (so-called “POWERON SEQUENCE”) is provided as follows: . . . the
`
`maintenance of a stable supply voltage of a stable clock signal, and of stable NOP
`
`input conditions for a minimum time period of 200 ms”); see also Ex. 1003,
`
`Subramanian Decl. at ¶34; see also Ex. 1007, JEDEC 21-C Standard at 115:
`
`Moreover, Merritt discloses a second “supply voltage stable signal” apart
`
`from the RESET* signal discussed above. Ex. 1003, Subramanian Decl. at ¶¶36-
`
`38. Specifically, Merritt further discloses a signal generated by the Latency Control
`
`304. See Ex. 1005 at Fig 3:
`
` 
`
`17
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
`
`
`Merritt explains that the Latency Control 304 “delays the response of the
`
`timing signal generator for one cycle of the external clock following the
`
`application of the reset signal.” Ex. 1005 at 7:38-41. Merritt also explains that a
`
`one clock cycle delay after reset places the generation of the Latency Control
`
`signal well into the stable region of the PWRUP supply voltage. See Ex. 1005 at
`
`Fig 5 (emphasis added):
`
`18
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`See also Ex. 1003, Subramanian Decl. at ¶37. Accordingly, the signal
`
`generated from the Latency Control 304 that is disclosed in Merritt is also a
`
`“supply voltage stable signal once a supply voltage has been stabilized after the
`
`switching-on operation of the dynamic semiconductor memory device,” based on
`
`the broadest reasonable interpretation of the claims terms. Ex. 1003, Subramanian
`
`Decl. at ¶38.
`
`c)
`
`supplying, via an enable circuit of the initialization
`circuit, an enable signal, the initialization circuit
`receiving the supply voltage stable signal and further
`command signals externally applied to the dynamic
`semiconductor memory device, after an identification
`of a predetermined proper initialization sequence of
`the further command signals the enable signal being
`
`19
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`
`generated and effecting an unlatching of a control
`circuit provided for a proper operation of the
`dynamic semiconductor memory device.
`Patent Owner has asserted that this limitation can be satisfied where, after
`
`the initialization sequence described above, certain signals are provided to the
`
`DRAM device, specifically a Clock Enable Signal (CKE) as the claimed enable
`
`signal, and commands to a Mode Register Set as the claimed “further command
`
`signals applied to the dynamic semiconductor memory device”:
`
`After the Initialization Sequence, described above, the Phison and
`Marvell controller chips provide, via an enable circuit of the
`initialization circuit (circuitry within the DDR Controller block of the
`Phison or Marvel controller), an enable signal (for example, the Clock
`Enable signal, CKE) . . . The Phison and Marvell controller chips in
`the Kingston 589 Accused Products provide further command signals
`externally applied to the DDR3 DRAM devices, after the
`identification of the predetermined proper initialization sequence (for
`example, the Mode Register Set (“MRS”) and/or ZQ Calibration
`(“ZQCL”) commands.
`
`Ex. 1008 at 14-15. Patent Owner further asserts that “effecting an
`
`unlatching of a control circuit provided for a proper operation of the dynamic
`
`semiconductor memory device” is satisfied through the use of a CKE signal,
`
`without ever specifically identifying a latch that is unlatched by the CKE. See Ex.
`
`1008 at 19 (The CKE signal effects an unlatching of a control circuit provided for a
`
`20
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
` 
`proper operation of the DDR3 DRAM device . . . .”). Petitioner disagrees that this
`
`limitation should be so construed under the narrower claim construction standard
`
`in district court. However, given Patent Owner’s assertions and the broadest
`
`reasonable interpretation of this claim limitation in the IPR context, the claimed
`
`“enable signal,” “further command signals” and “unlatching” elements should be
`
`construed to be satisfied in this proceeding where Clock Enable signals and Mode
`
`Register Set signals are used in DRAM.
`
`Merritt discloses an “enable signal.” Specifically, Merritt teaches that the
`
`initialization circuit of Fig. 3 is configured “to produce enabling signals En1, En2
`
`and En3, in a known sequence, defining the three-phase timing signals.” Ex. 1005
`
`at 7:66-8:2; see also Ex. 1003, Subramanian Decl. at ¶42; Ex. 1005 at Fig 3:
`
` 
`
`Additionally, Merritt discloses a clock enable signal:
`
`A system clock (CLK) signal is provided through a CLK input pin and
`a clock enable signal (CKE) is provided through a CKE input pin to
`SDRAM 10. The CLK signal is activated and deactivated based on
`the state of the CKE signal. All the input and output signals of
`
`21
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
`SDRAM 10, with the exception of the CKE input signal during power
`down and self refresh modes, are synchronized to the active going
`edge (the positive going edge in the embodiment illustrated in FIG. 1)
`of the CLK signal.
`
`Ex. 1005 at 3:54-62; see also Ex. 1003, Subramanian Decl. at ¶41. Since the
`
`CKE disclosed by Merritt is an “enable signal” under the BRI of this claim
`
`limitation, Merritt discloses an “enable signal.”
`
`Additionally, Merritt discloses “further command signals” because it
`
`discloses a Mode Register 40 along with a variety of mode register settings that are
`
` 
`
`received as commands to the DRAM:
`
`22
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
`Programmability of operating parameters of the synchronous dynamic
`random access memory, such as burst length, burst type, read latency,
`operating mode and a write burst mode, is accomplished through the
`use of a mode register 40 associated with control logic 28 (FIG. 1).
`The user selects the mode register 40 command to select operating
`parameters, such as burst length or latency, for the semiconductor
`SDRAM, as is known in the art. The mode register 40 latches the
`state of one or more of the address input signals A0-A9, or data
`signals DQ0-DQ7, upon receipt of a write-CAS*-before-RAS*
`(WCBR) programming cycle. In the exemplary embodiment, latency
`control outputs CL2 and CL3 provided by the mode register 40 are
`used to control the required circuits of the SDRAM. Moreover, the
`data output multiplexing circuits provide an inherent clock latency of
`one and are programmable to provide a clock latency of two or a
`clock latency of three. This basic implementation requires very little
`additional circuitry to the standard SDRAM.
`
`Ex. 1005 at 5:61-6:12; see also Ex. 1003, Subramanian Decl. at ¶43. Given
`
`that Mode Register Set commands are “further command signals” under the BRI of
`
`this claim limitation, Merritt discloses “further command signals.”
`
`Additionally, the DRAM memory device of Merritt also receives numerous
`
`other commands at the Command Decoder 26:
`
`A chip select (CS*) input pin inputs a CS* signal which enables,
`when low, and disables, when high a command decoder 26.
`Command decoder 26 is included in control logic 28. Command
`decoder 26 receives control signals including a row address strobe
`
`23
`
`

`
` 
`
`Petition for Inter Partes Review of U.S. Patent No. 6,157,589
`
`(RAS*) signal on a RAS* pin, column address strobe (CAS*) signal
`on a CAS* pin, and a write enable (WE*) signal on a WE* pin.
`Command decoder 26 decodes the RAS*, CAS*, and WE* signals to
`place control logic 28 in a particular command operation sequence.
`Control logic 28 controls the various circuitry of SDRAM 10 based on
`decoded commands such as during controlled reads or writes from or
`to bank 0 memory array 22 and bank 1 memory array 24. A bank
`address (BA) signal is provided on a BA input pin to define which
`bank memory array should be operated on by certain commands
`issued by control logic 28.
`
`Ex. 1005 at 3:63-4:11. Such signals received by Command Decoder are
`
`additional examples of “further command signals” disclosed by Merritt. See Ex.
`
`1003, Subramanian Decl. at ¶44.
`
`Moreover, Patent Owner asserts that the use of a CKE signal satisfies the
`
`“unlatching” requirement of this claim limitation. See Ex. 1008 at 19 (“The CKE
`
`signal effects an unlatching of a control circuit provided for a proper operation”).
`
`Thus, because Merritt discloses the use of a CKE signal, Merritt also discloses the
`
`claimed unlatching. Moreover, Merritt explicitly discloses unlatching:
`
`The first external or system clock pulse CLK, following the reset
`operation, sets the NOR latch 406, providing a logic 1 level at its
`input. This clock pulse, through inverter 420, also disables
`transistor 416 to isolate latch 414 from