Exhibit 1: Preliminary Infringement Claim Chart for U.S. Patent No. 6,157,589 (“589 Patent”)
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`Claim Construction: This chart is prepared without the benefit of the Court’s claim constructions. The parties have not proposed
`claim constructions prior to this disclosure. Accordingly, Polaris reserves the right to supplement or amend this chart to(cid:1)address any
`issues arising from any subsequent claim construction proceedings.
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`Preliminary Contentions: These contentions are by their nature preliminary. Discovery is ongoing and, as of the date of these
`contentions, Kingston has not fully responded to Polaris’s discovery requests nor provided deposition testimony or expert opinions.
`Thus, this chart is based on the limited information Kingston has produced as well as on publicly available evidence, and based upon
`information and reasonable belief in light of such evidence. Accordingly, once Polaris has had the benefit of full and complete
`discovery in this matter, Polaris may supplement and/or amend this chart to take account of the new information that becomes
`available.
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`Doctrine of Equivalents: Discovery is ongoing and as noted above Kingston has not provided full and complete discovery in this
`matter; Kingston has not provided non-infringement contentions; and the Court has not yet construed disputed claim terms. Moreover,
`Kingston has failed to provide particularized non-infringement allegations for most limitations of the asserted claims in its Amended
`Answer. Accordingly, except to the extent specifically noted, Polaris contends that each element of each asserted claim is literally
`met. Polaris reserves its right to respond if Kingston provides non-infringement contentions. Such responses by Polaris may include
`responsive Doctrine of Equivalents contentions.
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`589 Accused Products: Kingston SSDs with Phison or Marvell controllers (Representative Product is HyperX Predator
`SM2280S3/120G):1
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`1 Kingston has not produced technical information regarding the SandForce controllers used in certain of its SSD products.
`Accordingly, Polaris has not included such products in these infringement contentions for the 589 Patent. Polaris reserves its right to
`amend these contentions to address such products if and when sufficient technical information regarding the SandForce controllers is
`produced. Kingston SSD products using SandForce controllers include the following: HYPERX Fury (SHFS37A/120G
`SHFS37A/240G SHFS37A/480G); KC300 Series: SKC300S37A/60G, 120G, 180G, 240G, 480G; KC380 Series: SKC380S3/60G
`SKC380S3/120G SKC380S3/240G SKC380S3/480G; V300 Series: SV300S37A/60G, 120G, 240G, 480G, SV300S3D7/60G, 120G,
`240G, 480G, SV300S3N7A/60G, 120G, 240G, 480G, SV300S3B7A/60G, 120G, 240G, 480G; ms200 Series (SandForce SF2241):
`SMS200S3/30G, 60G, 120G, 240G, 480G; E100 Series (SandForce SF 2582): SE100S37A/100G SE100S37A/200G
`SE100S37A/400G.
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`KINGSTON 1008
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`U.S. Patent No. 6,157,589
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`Claim Language
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`Infringement by Kingston 589 Accused Products
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`11. An improved method for initializing a
`dynamic semiconductor memory device of a
`random access type via an initialization circuit
`controlling a switching-on operation of the
`dynamic semiconductor memory device and of
`its circuit components, the improvement which
`comprises:
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`To the extent that the preamble of Claim 11 is a limitation, the 589 Accused
`Products initialize a dynamic semiconductor memory device of a random access
`type (specifically DDR3 DRAM devices) via an initialization circuit in a DDR3
`controller, controlling a switching-on operation of the DRAM and of its circuit
`components, with the improvements described below:
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`All Kingston Accused 589 Products include one of: a Phison 3108 or 3110
`controller, or a Marvell 88SS9293 or 88SS1074 controller:
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`•(cid:1) HYPERX Predator/SHPM2280S3 Products (Phison 3108):
`SHPM2280S3/120G, 240G (physical inspection of sample, see photograph
`below)
`•(cid:1) HYPERX Predator/SHPM2280S3G2 Products (Phison 3110):
`SHPM2280S3G2/120G (physical inspection of sample, see photograph
`below)
`•(cid:1) HYPERX Savage (Phison 3110): SHSS37A/120G, 240G, 480G, 960G,
`SHSS3B7A/120G, 240G, 480G, 960G. See KIN0037865-866 at 866 (Data
`sheet)
`•(cid:1) KC310 Series (Phison 3110): SCK310S37A/960G, SKC310S3B7A/960G.
`See KIN0037867-868 at 868 (Data Sheet)
`•(cid:1) KC400 Series (Phison 3110): SKC400S37/128G, 256G, 512G, 1T. See
`KIN0037869-870 at 870 (Data Sheet)
`•(cid:1) M.2 SATA Series (Phison 3108): SM2280S3/120G, 240G. See, e.g.,
`KIN0000836 (Test Report for SM2280S3, listing Phison 3108 as controller)
`(confidential)
`•(cid:1) S200 Series (Phison 3108): SS200S3/30G. See KIN0037873-874 at 874
`(Data Sheet).
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`•(cid:1) UV300 Series (Phison PS3110): SUV300S37A/120G, 240G, 480G. See
`KIN0037875-876 at 876 (Data Sheet).
`•(cid:1) V310 Series (Phison 3108): SV310S37A/960G, SV310SB37A/960G,
`SV310S3D7/960G, SV310S3N7A/960G. See KIN0037877-878 at 878
`(Data Sheet).
`•(cid:1) HYPERX Predator/SHPM2280P2 Products (Marvell 88SS9293):
`SHPM2280P2/240G, 480G, SHPM2280P2H/240G, 480G. See
`KIN0037863-64 at 864 (Data Sheet)
`•(cid:1) UV400 Series (Marvell 88SS1074): SUV400S37/120G, 240G, 480G,
`960G. See PK00006105-106 at 106 (Data Sheet)
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`Each such controller includes within it a DDR3 controller as an internal functional
`block. The DDR3 controller controls (including initialization) DDR3 DRAM that is
`external to the Phison or Marvell controller and internal to the 589 Accused Product.
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`A photo of the representative product, SM2280S3/120G, below, illustrates the
`Phison 3108 controller and a Nanya DDR3 DRAM chip (NT5CC128M16FP-D1)
`external to the Phison 3108 controller and within (on) the SM2280S3/120G SSD:
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`See also photo of HyperX Predator (SHPM2280P2/120) (with label, and with label
`removed) (depicting Marvell 88SS9293 controller and Kingston D2516EC
`4BXGBB DDR3 DRAM) (see PK00010365 [Data sheet for Kingston 2516EC
`4BXGBB DDR3 DRAM)]:
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`See also photo of HyperX Predator (SHPM2280P2G2/120G) below, showing
`Phison 3110 controller and Nanya DDR3 DRAM:
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`When Kingston (in testing and using the Kingston 589 Accused Products)2 or when
`other users of the Kingston 589 Accused Products use and turn the 589 Accused
`Products on, the Phison or Marvell controller chips supply a voltage stable signal
`(for example, the Active Low synchronous Reset signal, /RESET, see, e.g., Nanya
`data sheet, PK00005950-6084 at PK00005957 [page 8 of data sheet]) once a supply
`signal has been stabilized (for example, at the time labeled Tb, see Nanya data sheet,
`PK00005950-6084, at PK00005962 (page 13 of data sheet, Fig. 3) (annotation
`added):
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`[a] supplying, via the initialization circuit, a
`supply voltage stable signal once a supply
`voltage has been stabilized after the switching-
`on operation of the dynamic semiconductor
`memory device; and
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`2 Kingston documents reflecting testing of the 589 Accused Products include KIN0000799-866.
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`The /RESET signal must be maintained for 200µs with stable power. See Step 1 of
`the RESET and Initialization Procedure on page 11 (PK00005960) of the Nanya
`data sheet, PK00005950-6084 (red box and underline annotation added):
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`See also, Reset Procedure state and Initialization state that follow the Power ON
`state in the Simplified State Diagram of Nanya data sheet (PK00005950-6084) at
`PK00005959 (page 10 of data sheet), Fig.2 (red circle annotations added):
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`The /RESET signal is supplied by the controller chip to the DDR3 DRAM chip.
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`See also, Nanya data sheet, PK00005950-6084 at PK00005956-57 (pages 7- 8 of
`data sheet) (showing /RESET as an input to the Nanya DDR3 DRAM):
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`supplying, via an enable circuit of the
`initialization circuit, an enable signal, the
`initialization circuit receiving the supply
`voltage stable signal and further command
`signals externally applied to the dynamic
`semiconductor memory device, after an
`identification of a predetermined proper
`initialization sequence of the further command
`signals the enable signal being generated and
`effecting an unlatching of a control circuit
`provided for a proper operation of the dynamic
`semiconductor memory device.
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`After the Initialization Sequence, described above, the Phison and Marvell
`controller chips provide, via an enable circuit of the initialization circuit (circuitry
`within the DDR Controller block of the Phison or Marvel controller), an enable
`signal (for example, the Clock Enable signal, CKE). See Nanya data sheet,
`PK00005950-6084 at 5956 (page 7 of data sheet), Table 3, and Step 2 of the RESET
`and Initialization Procedure, id. at 5960 (page 11 of data sheet) (annotations added):
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`The Phison and Marvell controller chips in the Kingston 589 Accused Products
`provide further command signals externally applied to the DDR3 DRAM devices,
`after the identification of the predetermined proper initialization sequence (for
`example, the Mode Register Set (“MRS”) and/or ZQ Calibration (“ZQCL”)
`commands. See Steps 6-10 of the RESET and Initialization Procedure, in the Nanya
`data sheet, PK00005950-6084 at 5960-61 (pages 11-12 of data sheet) (annotation
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`added):
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`See also Nanya data sheet, PK00005950-6084 at 5959 (page 10 of data sheet), Fig.
`2 (“Simplified State Diagram”), showing “ZQ Calibration” states and “Mode
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`Register Set” states occurring after the Initialization state (annotations added):
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`The Enable signal (CKE) is generated by the Phison and Marvell controller chips.
`See, e.g., KIN000665-706 at 683-684 (pages 19-20 of data sheet).
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`See also, Nanya data sheet, PK00005950-6084 at 5956 (page 7 of data sheet)
`(showing CKE as an input to the Nanya DDR3 DRAM) (annotations added):
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`The CKE signal effects an unlatching of a control circuit provided for a proper
`operation of the DDR3 DRAM device (see, e.g., Nanya data sheet, PK00005950-
`6084 at 5960-61 (pages 11-12 of data sheet) (RESET and Initialization Procedure)
`at steps 10 (“Issue ZQCL command to start[] ZQ calibration”), 11 (“Wait for both
`TDLLK and TZQinit completed”), and 12 (“The DDR3(L) SDRAM is now ready for
`normal operation.”).
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`See, also, PK00009560-599 at 580-599 [TechInsights Report at pages 16-35 (Test
`Results)](showing operation of Nanya DDR3 DRAM from power up through
`normal operation)
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`Kingston denies in paragraph 24 of its Amended Answer, Dkt. 75, that its products
`provide an initialization sequence of external commands before providing an enable
`signal and that CKE is supplied before the MRS signal. However, Claim 11 does not
`require that the enable signal not be provided prior to the claimed initialization
`sequence of the externally applied further command signals being identified.
`Rather, the claims simply require that the claimed enable signal be supplied after the
`claimed initialization sequence (whether or not it had been supplied earlier). In the
`589 Accused Products, the enable signal CKE performs several different functions.
`•(cid:1) First, CKE must be deasserted (pulled low) any time before /RESET is de-
`asserted. See Nanya data sheet, PK00005950-6084 at 5960 (page 11 of data
`sheet), Step 1 of Power-up Initialization sequence (“CKE is pulled “Low”
`anytime before /RESET being de-asserted (min. time 10ns”). The
`subsequent assertion of CKE permits internal state initialization to proceed.
`See id. at Step 2 (“After /RESET is de-asserted, wait for another 500 us until
`CKE become active. During this time, the DRAM will start internal state
`initialization; this will be done independently of eternal clocks.”) This
`includes the sending of the MRS and ZQCL commands (further command
`signals externally applied to the dynamic semiconductor memory device).
`•(cid:1) Second, after initialization, and after the further command signals are
`externally applied to the dynamic semiconductor memory device, the CKE
`signal must be asserted for proper operation of the dynamic semiconductor
`memory device (i.e., read and write accesses). See, e.g., Nanya data sheet,
`PK00005950-6084 at 5956 (page 7 of data sheet) (Table 3, Input/Output
`Functional Description, description of CKE):
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`Thus, CKE is supplied (asserted) before, during, and after the initialization sequence
`of the externally applied further command signals being identified. This is shown in
`the very figure that Kingston relies upon. See Nanya data sheet, PK00005950-6084
`at 5962 (page 13 of data sheet), Fig. 3 (red box shows the time during which the
`CKE is asserted, blue box shows when the MRS and ZQCL commands are sent,
`green box shows when ordinary operation commands (such as read and write
`comments) are sent. The CKE signal for ordinary operations is asserted after the
`MRS and ZQCL commands.
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`To the extent that that the claim requires that the enable signal not be applied before
`the further command signal, the limitation is met under the Doctrine of Equivalents.
`CKE is and must be asserted when commands are issued after the further external
`commands during normal operation (for example, during reads and writes). If CKE
`is not asserted when those commands are issued, the commands will be ignored.
`Thus, even though CKE is also asserted during the initialization procedure, it
`performs substantially the same function as the claimed enable signal (unlatching a
`control circuit of the dynamic semiconductor memory device) in substantially the
`same way (activating internal clock signals and device input buffers and output
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`drivers) and achieves substantially the same result (permits proper operation of the
`dynamic semiconductor memory device).
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`Although Kingston has not identified the manufacturer or part numbers of the
`DDR3 DRAM devices used in the other Phison 3108 and 3110-based accused
`products, the Phison 3108 and 3110 controllers, as well as the Marvell 88SS7273
`and 88SS1074 controllers, will operate similarly with respect to this limitation when
`interfacing with DDR3 DRAM devices from manufacturers other than Nanya
`because the RESET and Initialization Procedure will be the same for these other
`DDR3 DRAM devices. JEDEC DDR3 SDRM Standard, JESD79-3F,
`KIN00003432-3657 at, e.g., KIN0003458 (describing CKE function), KIN0003462
`(depicting Simplified State Diagram), and KIN0003464 (describing the Power-up
`Initialization Sequence of the RESET and Initialization Procedure).
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`Kingston admits that all Kingston memory products, including the DDR3 DRAMS
`used in the 589 Accused Products, comply with relevant JEDEC standards. See
`PK00007564-568 (http://www.kingston.com/us/memory/server/industry-standard)
`at 565 (“All Kingston memory is fully JEDEC compliant, an important specification
`used by leading semiconductor manufacturers”); KIN0028598-8643 at KIN0028626
`(“ValueRAM memory is our value-priced line of industry-standard, generic
`memory. Our ValueRAM is designed to industry JEDEC specifications . . . .”);
`KIN0028628 (“Kingston ValueRAM is built to industry standard specifications
`outlined by J.E.D.E.C., . . . J.E.D.E.C. provides the specifications for Pin Count,
`Form Factor, Speed Power, and Memory Technology Types.”); KIN0023810-854 at
`KIN0023827 (“Kingston’s ValueRAM product line is designed to JEDEC industry
`standard specifications.”).
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`12. The method according to claim 11, which
`comprises providing at least one of a
`preparation command signal for word line
`activation, a refresh command signal, and a
`loading configuration register command signal
`as the further command signals.
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`See Claim 11 Contentions, above. The Phison and Marvell controllers provide at
`least one of: (1) preparation command signal for word line activation; (2) a refresh
`command signal; and (3) a loading configuration register commend signal as the
`further command signals. Specifically, the MRS command discussed above as a
`further command signals acts as both a preparation signal and as a loading
`configuration register command signal. See, e.g., Nanya data sheet, PK00005950-
`6084 at 5963 (data sheet page 14) (Mode Register Set (MRS) command used to load
`configurations (various functions, features, and modes) to the DDR3 DRAM):
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`Although Kingston has not identified the manufacturer or part numbers of the
`DDR3 DRAM devices used in the other Phison and Marvell controllers in the 579
`Accused Products will operate similarly with respect to this limitation when
`interfacing with DDR3 DRAM devices from manufacturers other than Nanya
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`because the RESET and Initialization Procedure will be the same for these other
`DDR3 DRAM devices. See JEDEC DDR3 SDRM Standard, JESD79-3F,
`KIN00003432-3657 at, e.g., KIN0003458 (describing CKE function), KIN0003462
`(depicting Simplified State Diagram), and KIN0003464 (describing the Power-up
`Initialization Sequence of the RESET and Initialization Procedure).
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`Kingston admits that all Kingston memory products, including the DDR3 DRAMS
`used in the 579 Accused Products, comply with relevant JEDEC standards. See
`PK00007564-568 (http://www.kingston.com/us/memory/server/industry-standard)
`at 565 (“All Kingston memory is fully JEDEC compliant, an important specification
`used by leading semiconductor manufacturers”); KIN0028598-8643 at KIN0028626
`(“ValueRAM memory is our value-priced line of industry-standard, generic
`memory. Our ValueRAM is designed to industry JEDEC specifications . . . .”);
`KIN0028628 (“Kingston ValueRAM is built to industry standard specifications
`outlined by J.E.D.E.C., . . . J.E.D.E.C. provides the specifications for Pin Count,
`Form Factor, Speed Power, and Memory Technology Types.”); KIN0023810-854 at
`KIN0023827 (“Kingston’s ValueRAM product line is designed to JEDEC industry
`standard specifications.”).
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