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`FILE HISTORY
`us 6, 157,589
`
`PATENT:
`6,157,589
`INVENTORS: Krause, Gunnar
`
`TITLE:
`
`Dynamic semiconductor memory device
`and method for initializing a dynamic
`semiconductor memory device
`
`APPLICATION US1999343431A
`NO:
`FILED:
`ISSUED:
`
`30 JUN 1999
`05 DEC 2000
`
`COMPILED:
`
`16 MAR 2016
`
`3
`
`

`

`PATENT NUMBER
`. 615'75"8'9· . j
`
`,~11111•1
`
`6157589
`
`'i
`·.1
`
`U.S. UTILITY PATENT APPLICATION
`PATENT DATE
`
`ARTUNIT JBJ
`
`EXAMINER
`
`/e__
`Vitt
`FILED WITH: D DISK (CRF) D FICHE
`
`. · (Attached in pocket on right inside flap)
`
`B1ESTCOPY
`
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`PREPARED AND. APPROVED FOR ISSUE
`
`-
`
`ISSUING CLA~ATION
`. ·/ ..
`
`.CROSS_ REFERENCE(S)
`
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`SUSCLASS (ONE SUBCLASS PER BLOCK)
`
`0 Coniinu'ed on Issue Slip Inside File Jacket
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`CLASS/ I SUBCLASS
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`INTERNATIONAL CLASSIFICATION
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`Gr
`
`0 ·-·
`TERMINAL
`D DISCLAIMER
`
`(date)
`
`0 a) The term of this patent
`subsequent to
`·
`has been disclaimed ..
`0 b) The term of th.is. patent shall·
`not extend .P.ev.Ond the expiration. date
`of U.S Patent. ·No. - - - - - . - -
`
`0 c) The terminal _months of
`this patent have ·been disclaimed.
`
`UE BATCH NUMBER
`
`..
`WARNiNG:
`The information disclosed herein may be restricled. Unauthorized disclosure may be prohibited by the United States Code'ritle 35, Sections 122, 181 and 368.
`Possession outside the ·u.s. Patent & Trademark Ottlce Is restricted to authorized.employees and contractors only.
`·
`
`Form PT0·436A
`(Rev. 6198)
`
`·.::..
`
`ISSUE FEE \N FILE
`
`(LABEL AREA)
`.F " . a·, Orawings(.:__shts)sat_ .
`arm
`... ·
`.
`
`4
`
`

`

`6,157,589
`
`DYNAMIC SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR
`INTIALIZING A DYNAMIC SEMICONDUCTOR MEMORY DEVICE
`
`Transaction History
`
`Transaction Description
`Date
`06-30-1999 Workflow - Drawings Finished
`06-30-1999 Workflow - Drawings Matched with File at Contractor
`06-30-1999 Workflow - Drawings Received at Contractor
`06-30-1999
`Information Disclosure Statement (IDS) Filed
`06-30-1999
`Information Disclosure Statement (IDS) Filed
`07-08-1999
`Initial Exam Team nn
`IFW Scan & P ACR Auto Security Review
`07-21-1999
`07-27~1999 Notice Mailed--Application Incomplete--Filing Date Assigned
`09-30-1999 Change in Power of Attorney (May Include Associate POA)
`09-30-1999 Request for Foreign Priority (Priority Papers May Be Included)
`10-06-1999 Application Is Now Complete
`10-07-1999 Application Dispatched from OIPE
`11-30-1999 Transfer Inquiry
`12-27-1999
`Information Disclosure Statement (IDS) Filed
`12-27-1999
`Information Disclosure Statement (IDS) Filed
`02-03-2000 Transfer Inquiry
`02-22-2000 Case Docketed to Examiner in GAU
`07-17-2000 Mail Notice of Allowance
`07-17-2000 Notice of Allowance Data Verification Completed
`08-31-2000 Workflow - File Sent to Contractor
`10-03-2000
`Issue Fee Payment Verified
`10-20-2000 Workflow - Complete WF Records for Drawings
`10-24-2000 Application Is Considered Ready for Issue
`11-16-2000
`Issue Notification Mailed
`12-05-2000 Recordation of Patent Grant Mailed
`02-25-2016 File Marked Found
`03-03-2016 File Marked Found
`03-08-2016 Correspondence Address Change
`
`5
`
`

`

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`CONTENTS.
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`ISS~TE ~U~ STAPLE AREA (for additional cross references)
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`:--. --.---------~
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`IONO.
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`DATE
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`POSITiON
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`,~
`
`FEE DETERMINATION
`
`0.1.P:E. CLASSIFIER
`
`FORMALITY REVIEW
`
`INDEX OF CLAIMS
`N ............... ; ................. Non-elected
`"' ................................. Rejected
`.
`................................. Allowed
`I
`................................. Interference
`(Through numeral) ... Canceled ·
`A .................. ., .............. Appeal
`................................. Restricted
`0 ... : ............................. Objected
`
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`if 8
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`127 .
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`73
`74
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`76 .,
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`10(
`
`!
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`'
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`If more than 150 claims or 1 O actions
`staple additional sheet here
`
`(LEFT l~SIDE)
`
`7
`
`

`

`·sEARCHEo··
`
`SEARCH NOTES
`(INCLUDING SEARCH STRATEGY)
`
`Date
`7/1t/~
`
`·Exmr ..
`
`c_9H
`
`·Date
`
`Exmr.
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`INTERFERENCE SEARCHED I
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`Date
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`

`

`United States Patent [191
`Krause
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll lllll lllll lllll llllll Ill lllll llll
`US006157589A
`6,157,589
`[JJJ Patent Number:
`Occ. S,2000
`[45) Date of Patent:
`
`154] DYNAMIC SEMICO NDUCTOR MEMORY
`DEVICE A ND METH OJ) FOR IN ITIALIZLNC
`A DYNAMIC SEMLCONDUCTOR MEMORY
`DEVICE
`
`FOREIGN PATENT DOCU MENTS
`
`0 797 7fJ7 t\2 9/1997 Europcao Pal. Off ..
`9-106668 4/1997
`.Japan .
`
`[75]
`
`lovcntor: G un nar Krause, Munich, Germany
`
`[73] Assignee: Siemens Aktiengesellschaft, Munich,
`Germany
`
`[2lj Appl. No.: 09/343, 431
`
`[22] Filed:
`
`Jun . 30, 1999
`
`[30]
`Foreign Application Pr iority Da ta
`Jun. 30, 1998 I DEi Gem1any ........................... 198 29 287
`Int. Cl.7
`[5lj
`... . .•.•••...•.•.... . .......••..•.•.... GllC 8/00
`[52] U.S. C l . ............................................. 365/226; 365/228
`365/226, 227,
`[58) Field of Search ............
`365/228
`
`f56j
`
`References C ited
`
`U.S. PATENT DOC UMENTS
`
`5,307,3 19
`5,841.724
`5,894,446
`
`4/ 1994 Kohkctsu c1 al. .
`l l/1998 Ebel c1 al. .............................. 365/226
`4/ 1999
`llou ..
`. ......................... 365/222
`
`Primary Examiner-Vu A Le
`Allorney, Age111, or Firm-Herbert L. Lerner; Laurcoce A
`Greenber; Werner II. Siemer
`
`[57]
`
`ABSTRACT
`
`A dynamic scmicooductor memory device of a random
`access type has an initialization circu.it 1ha1 comrols the
`switching-on operation of the scmicoaductor memory
`device and of ils circuil components. Tbe initialization
`circuit supplies a supply voltage s1able signal once the
`supply voltage has been stabilized after 1bc switching-on of
`Lbc semiconductor memory device. 1De i11itialization circuit
`has an enable circuit that receives 1he supply voltage stable
`signal and funher command signals externally applied 10 the
`semiconductor memory device. The enable circuit supplies
`an enable signal after a predetermined proper initializa1ion
`sequence of tbc command sigoals applied lo tbe semicon(cid:173)
`ductor memory device is identified. The enable signal clJects
`tbe unlarching o( a control circui1 provided for lhe proper
`operation of 1be semiconductor memory device.
`
`13 Claims, 3 Dmwlng Sheets
`
`12
`CH IPR EADY
`
`19
`
`&
`
`18
`
`10A
`
`PRE
`
`108
`
`ARF
`
`14
`
`Q
`
`15
`
`Q
`
`s
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`R
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`
`10C
`
`16
`
`MRS ~-+-------1 5
`
`Q t-------'
`
`t-------1 R
`
`11
`
`POWER O N
`
`\
`
`9
`
`9
`
`

`

`U.S. Patent
`
`Dec. 5, 2000
`
`Sheet 1 of' 3
`
`6,157,589
`
`Fig 1
`
`2\
`
`Input Circuit ,. ---1
`
`',..
`
`(3
`
`F
`Command-
`DECODER
`
`.
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`
`Control Circuit for
`Memory Blocks
`
`---..
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`'-13
`
`CHIPREA DY
`
`Enable Circuit
`
`/
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`gl
`
`12/
`
`71
`
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`POWERON I
`11
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`~8
`
`6\
`
`Internal Voltage
`Regulation and
`Detection
`
`I
`)
`5
`
`10
`
`

`

`U.S. Patent
`
`Dec.S,2000
`
`Sheet 2 of' 3
`
`6,157,589
`
`18
`
`10A
`
`PRE
`
`108
`
`ARF
`
`10C
`
`Q
`
`Q
`
`14
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`15
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`
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`9
`
`- - - - - - - ; R
`
`11
`
`POWER ON
`
`SIGNAL
`
`Fig2
`
`- - - - - - - - - - . . - - - - - - - - - - - - -HIGH
`POWER ON ~------- ___________________ . LOW
`
`PRE
`
`_@ ___ ____ _
`
`ARF _________ _@_
`
`-~------ ----
`_<£) _____ _
`
`MRS
`
`CHI PR EADY
`
`I
`I
`I
`I
`--- -- --- ------L,~-r-~r-
`- - ------- --- --- -"tL- -J-~.~----
`@ -..._.
`~--------__...;~----'--~
`
`Fig 3
`
`Time
`
`11
`
`

`

`U.S. Patent
`
`Dec. 5, 2000
`
`Sheet 3 of 3
`
`6,157,589
`
`_____ J
`
`18
`
`19
`
`12
`
`CHIPREADY
`
`Fig 4
`
`12
`
`

`

`6,157,589
`
`1
`DYNAM IC SEMICONDUCTOR MEMORY
`DEVICE AN D METHOD FOR INITIALIZ ING
`A DYNAMIC SEMJCONDUCTOR ME MORY
`DEVICE
`
`OACKGROUND OF THE INVENTION
`
`Field o f the Invention
`The invention relates to a dynamic semiconductor
`memory device of the random access type (DRAM/
`SDRAM) baving an initialization circuit whicb controls a
`switching-on operation of the semiconductor memo ry
`device and of its circuit components. TI1c initialization
`circuit supplies a supply voltage stable signal (POWERON)
`once a supply voltage bas been stabilized after the 15
`switching-on of the semiconductor memory device. The
`invention also relates to a method for initializing such a
`dynamic semiconductor memory device, and aL'IO to the use
`of an enable circuit, that supplies an enable signal, for
`controlling the switching-on operation of the dynamic semi- 20
`conductor memory device.
`In the case of SD RAM semiconductor memories accord-
`ing to the .IEDEC standard, it is necessary to ensure during
`the switch-on operation (''POWERUP") that the internal
`control circuits provided for the proper operation of the 25
`semiconductor memory device are reliably beld in a defined
`desired state, in order to prevent undesirable activation of
`output transistors that would cause, on the data lines, a short
`circuit (so-called ''bus contention" or "data contention") or
`uncontrolled activation of internal current loads. '!be solu- 30
`tion to the problem turns out to be difficult oo account of a
`fundamental unpredictability of tbe time characteristic of the
`supply voltage and of the voltage level or levels at the
`external control inputs during the switch-on operation of the
`semiconductor memory. According to the specifications of 35
`the manufacturer an SDRAM component should ignore all
`commands which are present chronologically before a
`defined initialization sequence. lbe sequence consists of
`predetermined commands that mus1 be applied in a defined
`chronological order. However, a series of functions and 40
`commands whicb are allowed during proper operation of the
`component are desired or allowed chronologically only after
`the initialization sequence. According to the JEDEC stan(cid:173)
`dard for SDRAM semiconductor memories, a recommended
`initialization sequence (so-calle d " POWERON- 45
`SEQUENCE") is provided as follows:
`a. the application of a supply voltage and a start pulse in
`o rder to maintain an NOP condition at the inputs of the
`component;
`b. the maintenance of a stable supply voltage of a stable
`clock signal, and o[ stable NOP input conditions for a
`minimum time period of 200 us;
`c. tbe preparation command for word line activation
`(PRECHARGE) for all the memory banks of the 55
`device;
`4. the activation o f eight or more refresh commands
`(AUTOREFRESH); and
`5. the activation of a loading configuration register com(cid:173)
`mand (MODE-REGIST ER-SET) for initializing the
`mode register.
`After the identification of such a defined initialization
`sequence, the memory module is normally in a so-called
`IDLE state, tbat is to say it is precharged and prepared for
`proper operation. In tbe case of the SDRAM semiconductor 65
`memory modules that have been disclosed to date, all the
`control circuits of the component have been unlatched only
`
`2
`with the POWERON signal. 'Jbe signal POWERON is
`active if the internal supply voltages have reached the
`necessary values that arc necessary for the proper operation
`of the component. '!be module is then in a position to
`recognize and execute instructions.
`SUMMARY OF "11-IE INVENTION
`It is accordingly an object of the invention to provide a
`dynamic semiconductor memory device and a method for
`initializing a dynamic semiconductor memory device wrucb
`tO overcome the above-mentioned disadvantages of the prior
`art methods and devices of this general type, which is as
`simple as possible in structural terms and which effectively
`prevents the risk of a sbort circuit of the data lines and/or of
`uncontro lled activation of internal current loads.
`With the foregoing and other objects in view there is
`provided, in accordance with the invention, a dynamic
`semiconductor memory device of a random access type,
`containing an initialization circuit controlling a switching(cid:173)
`on operation and supplying a supply voltage stable signal
`o nce a supply vo ltage has been stabilized after the
`switching-on operation. TI1e initialization circttit bas a con-
`trol circuit for cootrolliog operations and an enable circuit
`receiving the s upply vo ltage stable signal and externally
`applied further command signals. lbe enable circuit o utput-
`ting an enable signal after a predetermined proper initial(cid:173)
`ization sequence of tbe externally applied further command
`signals are identified and 1be enable signal e[ectiog an
`unlatching of the control circuit.
`The invention provides for tbe initialization circuit to
`bave an enable circuit, wbich receives the supply voltage
`stable signal and the externally applied further command
`s ignals. The enable circuit generates the enable signal after
`the identification of the predetermined proper initialization
`sequence of the command signals is achieved. The enable
`signal effects the unlatching of the control circuit provided
`for the proper operation of the semiconductor memory
`device.
`Following the principle of the invention, the enable signal
`(CHIPREADY) is generated and becomes active in depen(cid:173)
`dence on further internal signals and the initialization
`sequence and then unlatches predetermined circuits. ']be
`predetermined circuits remain latched until the end of the
`predetermined initialization sequence. By way of example,
`commands are decoded but not executed and the output
`drivers arc held at bigh impedance.
`According to the preferred application in SDRAM
`memory devices according to the JEDEC standard, it is
`providccl that the command signals, externally applied to the
`semiconductor memory device, of lhe initialization
`50 sequence arc to be identified by the enable circuit. The
`command signals include a preparation command signal for
`word line ac1ivatioo ( PRECI IARGE), and/or a refresh com(cid:173)
`mand signal (AUTOREFRESI-1), and/or a loading configu-
`ration register command signal (MODE-REGISTER-SET).
`According to an advantageous structural refinement of the
`initialization circuit according to the invention, it is provided
`that the enable circuit has at least o ne bistable multivibrator
`stage with a set input wbich receives the command signal
`(PRECl-LARGE, AUTOREFRESH, MODE-REG ISTER-
`60 SET). The bistable multivibrator also has a reset input to
`which the supply vo ltage stable signal ( POWERON), a
`signal derived therefrom, or a linked signal is applied. 'Ille
`bistable multivibrator further has an omput at which the
`enable signal (CHIPREADY) is outputted.
`In particular, the enable circuit bas a plurality of bistable
`multivibrator stages respectively receiving the command
`s ignals.
`
`13
`
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`

`6,157,589
`
`3
`In an expedient refinement of the invention, it is provided
`that the output of at least one of the bistable multivibrator
`stages is passed to a reset input of a further multivibrator
`stage. la this case, it may furthermore be provided that, in
`one or the bistable multivibrator stages, the supply voltage
`stable signal (POWERON) and the signal output Crom the
`output of the further multivibrator stage are passed, after
`having been logicaUy combined by a gate, to the reset input
`of the multivibrator stage.
`Other features which are considered as characteristic for
`the invention are set forth in the appended claims.
`Although the invention is illustrated and described herein
`as embodied in a dynamic semiconductor memory device
`and a method for initializing a dynamic semiconductor
`memory device, it is nevertheless not intended to be limited
`to the details shown, since various modifications and struc(cid:173)
`tural changes may be made therein without departing from
`the spirit of the invention and within the scope and range of
`equivalents o[ the claims.
`The construction and method of operation of the
`invention, however, together with additional objects and
`advantages thereof will be best understood from the follow(cid:173)
`ing description of specific embodiments when read in con(cid:173)
`nection with the accompanying drawings.
`
`B RIEF DESCRI PTION OF T l IE DRAWINGS
`
`FIG. 1 is a diagrammatic, block diagram of components
`of an initialization circuit which controls a switching-on
`operation of a semiconductor memory and its circuit com(cid:173)
`ponents according to the invention;
`FIG. 2 is circuit diagram of an enable circuit that supplies
`an enable signal (CI-IJP READY);
`FIG. 3 is a time sequence diagram [or elucidating a
`method of operation of the circuit according to FIG. 2; and
`FIG. 4 is a circuit diagram of the enable circuit according
`to an exemplary embodiment of the invention.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`In all the figures of the drawing, sub-features and integral
`parts that correspond to one another bear the same reference
`symbol in each case. Referring now to the figures of the
`drawing in detail and first, particularly, to FIG. 1 thereof,
`there arc shown circuit components, important for under(cid:173)
`standjng the invention, of an SORAM memory device
`operating according to the JEDEC standard. The circuit
`components include an initialization circuit controlling a
`switching-on operation of the SDRAM. memory device and
`its circuit components. The initialization circuit has an input
`circuit 1, to whose input 2 command and clock signals that
`are externally applied in reference to the semiconductor
`memory arc provided. The command and clock signals are
`amplified and conditioned before being received by a com(cid:173)
`mand decoder 3 connected downstream of the input circuit
`I and at whose output 4, inter alia, the command signals
`PRE or PRECllARGE (preparation command for word line
`activation), ARF or AUTOREFRESH (refresh command)
`and MRS or MODE-REGIST ER-SET (loading configura(cid:173)
`tion register command) are output. 1be initialization circuit
`further has a circuit 5 for internal voltage regulation and/or
`detection, at whose input 6 the external supply voltages that
`arc externally applied to the semiconductor memory exter(cid:173)
`nally arc fed in. The circuit 5 bas a first output 7 outpuning
`a POWERON signal and a second output 8 supplying
`stabilized internal supply voltages. The method of operation
`
`tO
`
`4
`and the structure of the circuits l , 3 and 5 are sufficiently
`known to the person skilled in tbe art a ad therefore do not
`need to be explained in any more detail. What is in1portant
`for under$tanding the invention is the fact that the circuit 5
`supplies an active POWERON signal if, afaer the POW(cid:173)
`ERUP phase of the SDRAM memory, the internal supply
`voltages present at tbe output 8 have reached the values
`necessary for proper operation of the component.
`According to the invention, the initialization circuit fur(cid:173)
`thermore bas an enable circuit 9 connected downstream of
`the circuits 3 and 5. The command signals PRE, ARF and
`MRS arc applied to an input 10 o[ the enable circuit 9 and
`!he POWER ON signal is applied to an input 1 L of the enable
`circuit 9. An enable signal C IIIPREADY is supplied at an
`15 output 12 of the enable circujt 9 after the identification of a
`predetermined proper initialization sequence of the com(cid:173)
`mand signal• applied to the semiconductor memory device
`is achieved. The enable signal effects unlatching of control
`circuits l 3 provided for proper operation of the semicon-
`20 ductor memory device. The internal control circuits 13 serve
`inter alia for sequence control for one or more of the
`memory blocks of the SDRAM memory and are known as
`such.
`FIG. 2 shows a preferred exemplary embodiment of the
`25 enable circuit 9 according to the invention. The enable
`circuit 9 contains three bistable mullivibrator stages 14, 15
`and 16 each having a set input S, a reset input R, and also
`an output Q. An AND gate 17 connected upstream of the
`reset input R of the multivibrator stage 15 and an AND gate
`30 18 connected downstream of aU tbc outputs Q of tbe
`multivibrator stages 14, 15, 16 arc further provided. Tbc
`enable circuit further has an inverter 19 connected down(cid:173)
`stream of the AND gate 18. The enable signal CIIIPREADY
`being output at the output 12 of the inverter 19 and the
`35 enable signal CHIPREADY is active HIG H, that is to say
`activated when its voltage level is at logic HIGH. The
`command signals PRE, ARF, MRS applied to lhe respective
`set inputs S of the bistable multivibrator stages 14, LS, 16 arc
`each active LOW, that is to say these signals are active when
`40 their voltage level is al logic LOW, while the POWERON
`signal is again active HIGH. The POWERON signal is
`applied directly to the reset inputs R in the case of the
`multivibrator stages 14 and 16 and is firstly applied to one
`input of the AND gate 17 in the case o f the multivibrator
`45 stage 15, the signal output from the output Q of the multi(cid:173)
`vibrator stage 14 is applied to the other input of the AND
`gate 17, the output of the AND gate 17 is connected to the
`reset input of the multivibrator stage 15.
`The method of operation of the enable circuit 9 illustrated
`50 in FIG. 2 is such that activation of the enable signal
`Cl II PR EADY at is the output 12 to logic I IIGH is generated
`only when a predetermined chronological initialization
`sequence or the command signals PRE, ARF and MRS and
`activation of the POWER ON signal to the logic level I-IJGH
`55 are detected. Only then are the control circuits 13 unlatched
`oo account of the activation of the enable signal
`CI IIPREADY; the control circuits 13 remaining latched
`prior to this.
`Io the schematic time sequence diagram according to FIG.
`60 3, exemplary command sequences during the switching-on
`operation of the semiconductor memory device are illus(cid:173)
`trated in order 10 elucidate the method of operation or the
`enable circuit 9. In the case situation A, the signal PRE(cid:173)
`CHARGE is activated to active LOW too early relative to
`65 the activation of tbe POWERON signal, with the result that,
`the enable signal ClllPREADY is not yet activated to logic
`HIG H since the proper initialization sequence requires a
`
`14
`
`

`

`6,157,589
`
`tO
`
`JO
`
`5
`wailing lime before 1he first command. The signal swing of
`the command PRECHARGE according 10 case s ituation A is
`thus correctly ignored. In case situ a lion B, 1he chronological
`order of 1he acLiva1ioo of 1he signal AUTOREFRESI-1 10
`logic LOW is incorrec1 since 1he proper initializa1ion
`sequence prescribes a previous PRECI 11\RGE comma ad
`before 1be AUTO REFRESH comma ad. The signal swing of
`Lhe AUTO REFRESH signal 10 logic LOW according 10 case
`si1ua1ion 13 is therefore likewise ignored, and 1he enable
`signal does 001 go 10 logic lllGI-1 . In case si1uaLion C, a
`correc1 chronological o rder of lhe commands
`PRECHARGE, AUTOREFRESl-1, MODE-REG !STER(cid:173)
`SET is prcsenl conforming 10 Lhe JEDEC standard, in a
`logically consistenl manner, since 1he POWERON signal is
`also a1 logic HIG H, an enable signal C lllPREADY at logic 15
`HJGH is now supplied. Illustrated using clashed lines,
`another funber conceivable inilializa1ion sequence thal is
`allowed and therefore triggers an enable signal is repre(cid:173)
`sen1ed by 1he symbol D; activation of lhe command MODE(cid:173)
`REGISTER-SET 10 logic LOW is allowed at any time afler 20
`Lhe ac1ivaLioo of 1be POWERON signal.
`FIG. 4 shows funher details of a preferred exemplary
`embodimenl of lhe enable circuil 9 according 10 1be inveo-
`1ion. In this exemplary embodimeol, each of 1he bistable
`mullivibrators 14, IS, 16 is constructed from in each case
`two NAND gates 14A, 14B, 1SA, 17, 16A, 16B and also an
`invener 14C, lSC and l 6C, which are conoeeled 10 ooc
`another in the manner illustrated. The NANO gate 17 is
`provided with lhree inpuls in 1be bislable multivibralor 15.
`I claim:
`1. A dynamic semiconductor memory device of a random
`acces.s 1ype, comprising:
`an initializa1ion circuit conlrolling a switching-on opera(cid:173)
`tion and supplying a supply voltage s1able signal once
`a supply voltage has been slabilized after the switching- 35
`on operation, said initialization circuit haviag a control
`circuit for conlrolling operations and an enable circuit
`receiving the supply voltage stable signal and exlcr-
`~~r~~ita~~:~~IJ~~lhae: ::~·~~gnst:~;r ~i~r:;:I~~~ 40
`mined proper inilializalioo sequence of 1bc externally
`applied funhcr command signal s being iden1ified and
`the enable signal effccling an uolatching of said conlrol
`circuit.
`2. The semiconduclor memory device according 10 cla.im 45
`1, wherein the externally applied further t'Ommand signals
`forming the prede1crmined proper initialization sequence 10
`be identified by said enable circuil includes al leasl one of a
`preparation command signal for word line activa1ion, a
`refresh command signal, and a loading configuration regis1er 50
`command signal.
`3. The semicooduc1or memory device according to claim
`1, wherein said enable circuil has al least one bistable
`multivibrator stage having a set input receiving the exter(cid:173)
`nally applied furlher command signals, a reset input receiv- 55
`ing one of the supply voltage stable signal, a signal derived
`from the supply voltage stable signal and a linked signal, and
`an outpul ou1pu11ing said enable signal.
`4. '!be semiconduclor memory device according to claim
`3, wherein said at least one bisiablc mult.ivibrator stage is a 60
`plurlily of bistable multivibralor slages respectively receiv(cid:173)
`ing ooc of the externally applied funher command signals.
`S. The semiconduc1or memory device according 10 claim
`4, wherein said ou1pu1 of one of said plurali1y of bistable
`multivibrator stages is passed to said rcse1 inpul of another 65
`of said plurality of bis1able multivibrator stages.
`
`6
`6. The semiconduclor memory device according 10 claim
`4, including an AND gale receiving lhe supply voltage slable
`signal and a signal ou1pu1 from said outpul of ooc of said
`pluralily of bistable multivibrator stages, said AND gate
`ou1puning an outpul signal received at sai.d rC$el input of
`another of said plurali1y of bis1able multivibrator s1ages.
`7. The semiconduc1or memory device according to claim
`4, wherein said plurality of bistable mul1ivibrator stages are
`each formed of ao RS llip-llop constructed from one of al
`least 1wo NOR and at least 1wo NANO gates.
`8. The semiconduc1or memory device according 10 claim
`l , wherein 1he identification of an initiali7.ation sequence
`1ha1 is identified as 1he predetermined proper initializa1ion
`sequence by said enable circuit and generates the enable
`signal constitutes a command sequence conforming 10 a
`J EDEC standard.
`9. The semiconduclor memory device according 10 claim
`l , wherein said conirol circuil has outpul drivers remaining
`lalched during the switching-on o peration unlil said enable
`signal is generated by said enable circuit.
`10. The semiconduc1or memory device according 10 claim
`1, wherein lhe predetermined proper ioirializa1ion sequence
`includes one of the following chronologically successive
`25 command sequences:
`a) firs1ly PRE, secondly ARF, 1hirdly M RS;
`b) firs1ly PRE, secondly MRS, 1hirdly ARF; and
`c) firslly MRS, secondly PRE, or thirdly ARF;
`where,
`PRE=the prepara1ion command signal for word line
`acljvation,
`ARF-the refresh command signal, and
`MRS~1he loading coofigura1ioo rcgisler command signal.
`11. Ao improved melbod for initializing a dynamic semi-
`conductor memory device of a random access type via an
`inirialization circuit controHing a switching-on operation of
`1he dynamic semiconductor memory device and of iLS circui1
`componeoLS, lhe improvemenl which comprises:
`supplying, via lhe ioitializalion circuil, a supply vollagc
`slable signal once a supply voltage has been s1abilized
`afler 1be swi1ching-on operation of 1he dynamic se01i(cid:173)
`conduc1or memory device; and
`supplying, via an enable circuit of lbe initialization
`circuit, an enable signal~ tbc initialization circuit receiv(cid:173)
`ing 1he supply voltage s1ablc signal aod funber com(cid:173)
`mand signals externally applied 10 the dynamic semi(cid:173)
`conductor memory device, after an identification of a
`predelermined proper initialization sequence of 1he
`further command signals the enable signal being gen(cid:173)
`erated and effec1ing an unlatching o[ a conlrol circuil
`provided for a proper operation of the dynamic semi(cid:173)
`conductor memory device.
`12. Tue me1bod according 10 claim 11, wbicb comprises
`provid.ing al leasl one of a preparation command signal for
`word line activa1ioo, a refresh command signal, and a
`loading configuration regis1er command signal as the further
`command signals.
`13. Tue meLbod according 10 claim 11, which comprises
`mainlaining a lalched condilion of output drivers of lhc
`dynamic semiconductor memory device during 1bc
`swi1ching-on operation until 1he enable signal is genera1ed
`by 1he enable circuit.
`
`15
`
`

`

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