`
`https://www.jedec.org/standards-documents/dictionary/terms/clock-enab...
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`In certain synchronous memory devices, a logic level input that enables the clock input and allows it to fulfill its defined
`function.
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`References
`
`JESD21-C, 1/97
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`2/17/2017 11:09 AM
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`Polaris Innovations Ltd. Exhibit 2001
`Kingston Tech. Comp. v. Polaris Innov. Ltd.
`IPR2017-00238 Page 2001-1
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