US0071 l67l0Bl
`
`(12)
`
`United States Patent
`
`Jin et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,116,710 B1
`Oct. 3, 2006
`
`(54) SERIAL CONCATENATION OF
`INTERLEAVED CONVOLUTIONAL CODES
`FORMING TURB()_L[KE CODES
`
`5,881,093 A
`6,014,411 A *
`6,023,783 A
`6,031,874 A
`
`3/1999 Wang et a1.
`1/2000 Wang ....................... .. 375/259
`2/2000 D1VSala.r et al.
`2/2000 Chennakeshu et al.
`
`(75)
`
`Inventors: Hui Jin, Glen Gardner, NJ (US);
`Aamod Khandekar, Pasadena, CA
`_
`(US)3 Rabe” J- M°E1'°°°= Pasadena:
`CA (US)
`
`:
`6’396’423 B1 ,,
`,
`,
`6,437,714 B1*
`2001/0025358 A1
`
`32:15
`5/:002 L
`g
`............. .. 341/95
`aumen et al.
`._
`8/2002 Kim et al.
`.................. .. 341/81
`9/2001 Eidson etal.
`
`OTHER pUBL1CAT1QNS
`
`Wiberg et al., “Codes and Iteratie Decoding on General Graphs”,
`:yiI?S<>t:::Itil:3n0I;iIf):r:t1:IitE§)1rie:11i<f\(/}:1§tz;i3:56
`LDPC C0de'S,, Di
`.
`.
`.
`.
`.
`,
`gital Video Broadcasting (DVB) User guidelines
`for the second generation system for Broadcasting,
`Interactive
`Services, News Gathering and other broadband satellite applications
`(DVB-S2) ETSI TR 102 376 v1.1.1. (2005-02) Technical Report.
`pp. 64.
`Benedetto et al., “Bandwidth eflicient parallel concatenated coding
`schemes,” Electronics Letters 3l(24):2067-2069 (Nov. 23, 1995).
`Benedetto et al., “Soft-output decoding algorithms in iterative
`Ec:udi1SIi1E0I(1)ETt]gt§) Piggfsés R:111):I,[Tf‘12e_c1()2I:‘1IE)1:nI:?1:t§(1):1:n:ln((l:313:?
`nia Institute of Technology Jet Propulsion Laboratory, Joseph H.
`Y , Ed.,
`. 63-87 F b. 15, 1996 .
`“en
`pp
`( e
`e
`)
`(Contmued)
`
`.
`Primar
`y Exammer—Dac V. Ha
`(74) Attorney, Agent, or Firm—Fish & Richardson P.C.
`
`(57)
`
`ABSTRACT
`
`A serial concatenated coder includes an outer coder and an
`inner coder. The outer coder irregularly repeats bits in a data
`block according to a degree profile and scrambles the
`repeated bits. The scrambled and repeated bits are input to
`an inner coder, which has a rate substantially close to one.
`
`33 Claims, 5 Drawing Sheets
`
`(73) Assignee: California Institute of Technology,
`Pasadena, CA (US)
`
`( >1: ) Notice:
`
`Subject to any diisglaiineé, the tierin531"this
`patent is exten e or a juste un er 35
`U'S'C' 15403) by 735 days’
`
`.
`(21) APP1~ N°~~ 09/861402
`.
`F11ed3
`
`(22)
`
`May 189 2001
`
`(51)
`
`Related U-S- APP1iCati011 Data
`(60) Provisional application No. 60/205,095, filed on May
`18’ 2000'
`Int. Cl.
`(2006.01)
`H04B 1/66
`(52) U.S. Cl.
`.................... .. 375/240; 375/262; 375/265;
`.
`.
`.
`375/341’ 341/51’ 341/102’ 714/752
`(58) Field of Classification Search .............. .. 375/259,
`375/262, 265, 285, 296, 341, 346, 348; 714/746,
`714/752, 755, 756, 786, 792, 794, 795, 796;
`
`341/51’ 52’ 56} 102’ 103
`,
`,
`See apphcanon file for Complete Search hlstory
`References Cited
`U.S. PATENT DOCUMENTS
`
`(56)
`
`5,392,299 A
`5,751,739 A *
`
`2/1995 Rhines et a1.
`5/1998 Seshadri et a1.
`
`.......... .. 714/746
`
`OUTER
`
`n
`
`v
`
`k u
`
`k
`
`u
`
`200\‘
`
`202
`
`204
`
`206
`
`Apple 1201
`Apple 1201
`
`

`
`US 7,116,710 B1
`Page 2
`
`OTHER PUBLICATIONS
`
`Benedetto et al., “Serial Concatenation of Interleaved Codes:
`Performace Analysis, Design, and Iterative Decoding,” The Tele-
`communications and Data Acquisition (TDA) Progress Report
`42-126 for NASA and California Institute of Technology Jet Pro-
`pulsion Laboratory, Jospeh H. Yuen, Ed., pp. 1-26 (Aug. 15, 1996).
`Benedetto et al., “A Soft-Input Soft-Output Maximum A Posteriori
`(MAP) Module to Decode Parallel and Serial Concatenated Codes,”
`The Telecommunications and Data Acquisition (TDA) Progress
`Report 42-127 for NASA and California Institute of Technology Jet
`Propulsion Laboratory. Jospeh H. Yuen, Ed., pp. 1-20 (Nov. 15,
`1996).
`Benedetto et al., “Parallel Concatenated Trellis Coded Modulation,”
`ICC ’96, IEEE, pp. 974-978, (Jun. 1996).
`Benedetto, S. et al., “A Soft-Input Soft-Output APP Module for
`Iterative Decoding of Concatenated Codes.” IEEE Communications
`Letters 1(1):22-24 (Jan. 1997).
`Benedetto et al., “Serial Concatenation of interleaved codes: per-
`formance analysis, design, and iterative decoding,” Proceedings
`from the IEEE 1997 International Symposium on Information
`Theory (ISIT), Ulm, Germany, p. 106, Jun. 29-Jul. 4, 1997.
`Benedetto et al., “Serial Concatenated Trellis Coded Modulation
`with Iterative Decoding,” Proceedings from IEEE 1997 Interna-
`tional Symposium on Information Theory (ISIT), Ulm, Germany, p.
`8, Jun. 29-Jul. 4, 1997.
`Benedetto et al., “Design of Serially Concatenated Interleaved
`Codes,” ICC 97, Montreal, Canada, pp. 710-714, (Jun. 1997).
`Berrou et al., “Near Sharmon Limit Error-Correcting Coding and
`Decoding: Turbo Codes,” ICC pp. 1064-1070 (1993).
`Digital Video Broadcasting (DVB) User guidelines for the second
`generation system for Broadcasting, Interactive Services, News
`Gathering and other broadband satellite applications (DVB-S2)
`ETSI TR 102 376 V1.1.1. (Feb. 2005) Technical Report, pp. 1-104
`(Feb. 15, 2005).
`Divsalar et al., “Coding Theorems for ‘Turbo-Like’ Codes,” Pro-
`ceedings of the 361‘ Annual Allerton Conference on Communica-
`tion, Control, and Computing, Sep. 23-25 1998, Allerton House,
`Monticello, Illinois, pp. 201-210 (1998).
`Divsalar, D. et al., “Multiple Turbo Codes for Deep-Space Com-
`munications,” The Telecommunications and Data Acquisition
`
`(TDA) Progress Report 42-121 for NASA and California Institute of
`Technology Jet Propulsion Laboratory, Jospeh H. Yuen, Ed., pp.
`60-77 (May 15, 1995).
`Divsalar, D. et al., “On the Design of Turbo Codes,” The Telecom-
`munications and Data Acquisition (TDA) Progress Report 42-123
`for NASA and California Institute of Technology Jet Propulsion
`Laboratory, Jospeh H. Yuen, Ed., pp. 99-131 (Nov. 15, 1995).
`Divsalar, D. et al., “Low-rate turbo codes for Deep Space Commu-
`nications,” Proceedings from the 1995 IEEE International Sympo-
`sium on Information Theory, Sep. 17-22, 1995, Whistler, British
`Columbia, Canada, p. 35.
`Divsalar, D. et al., “Turbo Codes for PCS Applications,” ICC 95,
`IEEE, Seattle, WA, pp. 54-59 (Jun. 1995).
`Divsalar, D. et al., “Multiple Turbo Codes,” MILCOM 95, San
`Diego, CA pp. 279-285 (Nov. 5-6, 1995).
`Divsalar et al., “Effective free distance of turbo codes,” Electronics
`Letters 32(5): 445-446 (Feb. 29, 1996).
`Divsalar, D. et al., “Hybrid concatenated codes and Iterative Decod-
`ing,” Proceedings from the IEEE 1997 International Symposium on
`Information Theory (ISIT), Ulm, Germany, p. 10 (Jun. 29-Jul. 4,
`1997).
`Divsalar, D. et al., “Serial Turbo Trellis Coded Modulation with
`Rate-1 Ir1ner Code,” Proceedings from the IEEE 2000 International
`Symposium on Information Theory (ISIT), Italy, pp. 1-14 (Jun.
`2000).
`Jin et al., “Irregular Repeat - Accumulate Codes,” 2nd International
`Symposium on Turbo Codes & Related Topics, Sep. 4-7, 2000,
`Brest, France, 25 slides, (presented on Sep. 4, 2000).
`Jin et al., “Irregular Repeat-Accumulate Codes,” 2nd International
`Symposium on Turbo Codes & Related Topics, Sep. 4-7, 2000,
`Brest, France, pp. 1-8 (2000).
`Richardson, et al., “Design of capacity approaching irregular low
`density parity check codes,” IEEE Trans,
`Inform. Theory 47:
`619-637 (Feb. 2001).
`Richardson, T. and R. Urbanke, “Eflicient encoding of low-density
`parity check codes,” IEEE Trans. Inform. Theory 47: 638-656 (Feb.
`2001).
`
`* cited by examiner
`
`

`
`U.S. Patent
`
`Oct. 3,2006
`
`Sheet 1 of 5
`
`US 7,116,710 B1
`
`FIG.1 (PriorArt)
`
`C\l
`LI.J
`
`2CC
`
`D
`l.LJ
`
`5.3
`
`

`
`U.S. Patent
`
`Oct. 3,2006
`
`Sheet 2 of 5
`
`US 7,116,710 B1
`
`C3
`(.3
`<
`
`:
`
`V‘
`
`3
`I
`
`'-\l
`
`CB
`I
`
`2(
`
`DE_
`
`:
`
`x
`
`x
`
`

`
`U.S. Patent
`
`Oct. 3,2006
`
`Sheet 3 of 5
`
`US 7,116,710 B1
`
`Variable Node
`
`Check Node
`
`Fraction of nodes
`degree i
`
`degree a
`
`.
`
`\
`
`\
`
`I m
`
`I
`
`U
`
`ml
`
`Igl‘
`
`‘I.l.Illu’
`
`\ulII'
`
`203
`
`20O0
`
`\T
`
`/.I,.
`
`x.
`
`I
`
`\
`
`\
`
`\
`
`_
`
`//
`1.1
`
`lnl..l|.lIu.\‘ Q_\
`
`_
`
`I,\\
`
`I
`
`.’alIIIuIIuI-‘\
`
`COO
`
`‘lll1:
`
`FIG‘. 3
`
`

`
`U.S. Patent
`
`Oct. 3,2006
`
`Sheet 4 of 5
`
`US 7,116,710 B1
`
`
`
`oo.
`
`..
`
`.e'a‘#'
`,5-1,‘.
`
`.
`
`FIG. 5A
`
`304
`
`U
`
`----- -~ 0
`
`
`
`FIG. 5B
`
`

`
`U.S. Patent
`
`Oct. 3,2006
`
`Sheet 5 of 5
`
`US 7,116,710 B1
`
`...GE
`
`

`
`US 7,116,710 B1
`
`1
`SERIAL CONCATENATION OF
`INTERLEAVED CONVOLUTIONAL CODES
`FORMING TURBO-LIKE CODES
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application claims priority to U.S. Provisional Appli-
`cation Ser. No. 60/205,095, filed on May 18, 2000, and to
`U.S. application Ser. No. 09/922,852, filed on Aug. 18, 2000
`and entitled Interleaved Serial Concatenation Forming
`Turbo-Like Codes.
`
`GOVERNMENT LICENSE RIGHTS
`
`The U.S. Government has a paid-up license in this inven-
`tion and the right in limited circumstances to require the
`patent owner to license others on reasonable terms as
`provided for by the terms of Grant No. CCR-9804793
`awarded by the National Science Foundation.
`BACKGROUND
`
`2
`
`The repeated and scrambled bits are input to an inner
`coder that has a rate substantially close to one. The inner
`coder may include one or more accumulators that perform
`recursive modulo two addition operations on the input bit
`stream.
`
`The encoded data output from the inner coder may be
`transmitted on a charmel and decoded in linear time at a
`
`destination using iterative decoding techniques. The decod-
`ing techniques may be based on a Tanner graph represen-
`tation of the code.
`
`10
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`15
`
`20
`
`FIG. 1 is a schematic diagram of a prior “turbo code”
`system.
`FIG. 2 is a schematic diagram of a coder according to an
`embodiment.
`
`FIG. 3 is a Tarmer graph for an irregular repeat and
`accumulate (IRA) coder.
`FIG. 4 is a schematic diagram of an IRA coder according
`to an embodiment.
`
`Properties of a channel affect the amount of data that can
`be handled by the channel. The so-called “Shannon limit”
`defines the theoretical limit of the amount of data that a
`
`25
`
`channel can carry.
`Different techniques have been used to increase the data
`rate that can be handled by a channel. “Near Shannon Limit
`Error-Correcting Coding and Decoding: Turbo Codes,” by
`Berrou et al. ICC, pp 1064—1070, (1993), described a new
`“turbo code” technique that has revolutionized the field of
`error correcting codes. Turbo codes have sufficient random-
`ness to allow reliable communication over the channel at a
`
`they still retain
`high data rate near capacity. However,
`sufi‘icient structure to allow practical encoding and decoding
`algorithms. Still, the technique for encoding and decoding
`turbo codes can be relatively complex.
`A standard turbo coder 100 is shown in FIG. 1. A block
`
`of k information bits is input directly to a first coder 102. A
`k bit interleaver 106 also receives the k bits and interleaves
`them prior to applying them to a second coder 104. The
`second coder produces an output that has more bits than its
`input, that is, it is a coder with rate that is less than 1. The
`coders 102, 104 are typically recursive convolutional coders.
`Three different items are sent over the charmel 150: the
`
`original k bits, first encoded bits 110, and second encoded
`bits 112. At the decoding end, two decoders are used: a first
`constituent decoder 160 and a second constituent decoder
`
`162. Each receives both the original k bits, and one of the
`encoded portions 110, 112. Each decoder sends likelihood
`estimates of the decoded bits to the other decoders. The
`estimates are used to decode the uncoded information bits as
`corrupted by the noisy charmel.
`SUMMARY
`
`A coding system according to an embodiment is config-
`ured to receive a portion of a signal to be encoded, for
`example, a data block including a fixed number of bits. The
`coding system includes an outer coder, which repeats and
`scrambles bits in the data block. The data block is appor-
`tioned into two or more sub-blocks, and bits in dififerent
`sub-blocks are repeated 21 dilferent number of times accord-
`ing to a selected degree profile. The outer coder may include
`a repeater with a variable rate and an interleaver. Alterna-
`tively, the outer coder may be a low-density generator matrix
`(LDGM) coder.
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`FIG. 5A illustrates a message from a variable node to a
`check 11ode on the Tanner graph of FIG. 3.
`FIG. 5B illustrates a message from a check node to a
`variable node on the Tarmer graph of FIG. 3.
`FIG. 6 is a schematic diagram of a coder according to an
`alternate embodiment.
`
`FIG. 7 is a schematic diagram of a coder according to
`another alternate embodiment.
`
`DETAILED DESCRIPTION
`
`FIG. 2 illustrates a coder 200 according to an embodi-
`ment. The coder 200 may include an outer coder 202, an
`interleaver 204, and inner coder 206. The coder may be used
`to format blocks of data for transmission, introducing redun-
`dancy into the stream of data to protect the data from loss
`due to transmission errors. The encoded data may then be
`decoded at a destination in linear time at rates that may
`approach the channel capacity.
`The outer coder 202 receives the uncoded data. The data
`may be partitioned into blocks of fixed size, say k bits. The
`outer coder may be an (n,k) binary linear block coder, where
`n>k. The coder accepts as input a block u of k data bits and
`produces an output block v of n data bits. The mathematical
`relationship between u and v is v:TOu, where To is an n><k
`matrix, and the rate of the coder is k/n.
`The rate of the coder may be irregular, that is, the value
`of To is not constant, and may dilfer for sub-blocks of bits
`in the data block. In an embodiment, the outer coder 202 is
`a repeater that repeats the k bits in a block a number of times
`q to produce a block with n bits, where n:qk. Since the
`repeater has an irregular output, different bits in the block
`may be repeated a different number of times. For example,
`a fraction of the bits in the block may be repeated two times,
`a fraction of bits may be repeated three times, and the
`remainder of bits may be repeated four times. These frac-
`tions define a degree sequence, or degree profile, of the code.
`The inner coder 206 may be a linear rate-1 coder, which
`means that the n-bit output block x can be written as x:T,w,
`where T, is a nonsingular r1><n matrix. The inner coder 210
`can have a rate that is close to 1, e.g., within 50%, more
`preferably 10% and perhaps even more preferably within
`1% of 1.
`
`In an embodiment, the inner coder 206 is an accumulator,
`which produces outputs that are the modulo two (mod-2)
`partial sums of its inputs. The accumulator may be a
`
`

`
`US 7,116,710 B1
`
`3
`truncated rate-1 recursive convolutional coder with the
`
`transfer function 1/(1+D). Such an accumulator may be
`considered a block coder whose input block [x1, .
`.
`. ,xn] and
`output block [y1,
`.
`.
`.
`, yn] are related by the formula
`Y1:X1
`
`4
`
`to each of the check nodes 304 is zero. To see this, set xO:0.
`Then if the values of the bits on the ra edges coming out the
`permutation box are (V1,
`.
`.
`.
`, vm),
`then we have the
`recursive formula
`
`Y2 :x1”
`
`.V3:x1
`
`.Vn:x1
`
`where “G3” denotes mod-2, or exclusive-OR O(OR), addi-
`tion. An advantage of this system is that only mod-2 addition
`is necessary for the accumulator. The accumulator may be
`embodied using only XOR gates, which may simplify the
`design.
`The bits output from the outer coder 202 are scrambled
`before they are input to the inner coder 206. This scrambling
`may be performed by the interleaver 204, which performs a
`pseudo-random permutation of an input block v, yielding an
`output block w having the same length as v.
`The serial concatenation of the interleaved irregular
`repeat code and the accumulate code produces an irregular
`repeat and accumulate (IRA) code. An IRA code is a linear
`code, and as such, may be represented as a set of parity
`checks. The set of parity checks may be represented in a
`bipartite graph, called the Tarmer graph, of the code. FIG. 3
`shows a Tarmer graph 300 of an IRA code with parameters
`(fl,
`.
`.
`.
`,
`f}; a), where fl.§0, Zl.fl.:1 and “a” is a positive
`integer. The Tanner graph includes two kinds of nodes:
`variable nodes
`(open circles) and check nodes
`(filled
`circles). There are k variable nodes 302 on the left, called
`information nodes. There are r variable nodes 306 on the
`right, called parity nodes. There are r:(kEl.ifl.)/a check nodes
`304 connected between the information nodes and the parity
`nodes. Each information node 302 is connected to a number
`of check nodes 304. The fraction of information nodes
`
`For example, in the
`connected to exactly i check nodes is
`Tanner graph 300, each of the f2 information nodes are
`connected to two check nodes, corresponding to a repeat of
`q:2, and each of the f3 information nodes are connected to
`three check nodes, corresponding to q:3.
`Each check node 304 is connected to exactly “a” infor-
`mation nodes 302. In FIG. 3, a:3. These connections can be
`made in many ways, as indicated by the arbitrary permuta-
`tion of the ra edges joining information nodes 302 and check
`nodes 304 in permutation block 310. These connections
`correspond to the scrambling performed by the interleaver
`204.
`
`In an alternate embodiment, the outer coder 202 may be
`a low-density generator matrix (LDGM) coder that performs
`an irregular repeat of the k bits in the block, as shown in FIG.
`4. As the name implies, an LDGM code has a sparse
`(low-density) generator matrix. The IRA code produced by
`the coder 400 is a serial concatenation of the LDGM code
`
`and the accumulator code. The interleaver 204 in FIG. 2 may
`be excluded due to the randomness already present in the
`structure of the LDGM code.
`
`If the permutation performed in permutation block 310 is
`fixed, the Tarmer graph represents a binary linear block code
`with k information bits (111,
`.
`.
`. ,uk) andr parity bits (xl, .
`.
`.
`,
`x,.), as follows. F,ach of the information bits is associated
`with one of the infonnation nodes 302, and each of the parity
`bits is associated with one of the parity nodes 306. The value
`of a parity bit is determined uniquely by the condition that
`the mod-2 sum of the values of the variable nodes connected
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`/1
`
`[:1
`X1 = 961-1 + Z V(j—l)/1+1"
`
`, r. This is in effect the encoding algorithm.
`.
`.
`.
`for j:1, 2,
`Two types of IRA codes are represented in FIG. 3, a
`nonsystematic version and a systematic version. The non-
`systematic version is an (r,k) code, in which the codeword
`corresponding to the information bits (ul, .
`.
`.
`, uk) is (xl, .
`.
`.
`,
`x,). The systematic version is a (k+r, k) code, in which the
`codeword is (111,
`.
`.
`. ,uk;x1, .
`.
`.
`, x,).
`The rate of the nonsystematic code is
`
`Rm _
`
`61
`
`i
`
`The rate of the systematic code is
`
`G
`
`Rm =
`
`a+Zifi-
`
`For example, regular repeat and accumulate (RA) codes
`can be considered nonsystematic IRA codes with a:1 and
`exactly one
`equal to 1, say fq:1 , and the rest zero, in which
`case Rwy: simplifies to R:1/q.
`The IRA code may be represented using an alternate
`notation. Let Kl. be the fraction of edges between the infor-
`mation nodes 302 and the check nodes 304 that are adjacent
`to an information node of degree i, and let pl. be the fraction
`of such edges that are adjacent to a check node of degree i+2
`(i.e., one that is adjacent to i information nodes). These edge
`fractions may be used to represent the IRA code rather than
`the corresponding node fractions. Define }t(x):Zl.}»l.xi‘1 and
`p(x):Zl.pZ.xi‘1 to be the generating functions of these
`sequences. The pair (K, p) is called a degree distribution. For
`L(X):ZifiXis
`
`L(x):j0"}»(z)dz/I01}»(z)dz
`
`The rate of the systematic IRA code given by the degree
`distribution is given by
`
`ZPj/f 71
`Rate: 1+ J
`_
`J
`Z_/\j//
`
`“Belief propa gation” on the Tanner Graph realization may
`be used to decode IRA codes. Roughly speaking, the belief
`
`

`
`US 7,116,710 B1
`
`5
`propagation decoding technique allows the messages passed
`on an edge to represent posterior densities on the bit asso-
`ciated with the Variable node. A probability density on a bit
`is a pair of non-negatiVe real numbers p(0), p(1) satisfying
`p(0)+p(1):1, where p(0) denotes the probability of the bit
`being 0, p(1) the probability of it being 1. Such a pair can be
`represented by its log likelihood ratio, m:log(p(0)/p(1)).
`The outgoing message from a Variable node u to a check
`node V represents information about u, and a message from
`a check node u to a Variable node V represents information
`about u, as shown in FIGS. 5A and 5B, respectively.
`The outgoing message from a node u to a node V depends
`on the incoming messages from all neighbors w of u except
`V. If u is a Variable message node, this outgoing message is
`
`Watv
`m(u —> v) = Z m(w —> 14) +m0(14)
`
`where mO(u) is the log-likelihood message associated with u.
`If u is a check node, the corresponding formula is
`
`m(I4 —> v)
`2
`
`tank
`
`mliw —> 14)
`2
`
`= Q tank
`
`Before decoding, the messages m(w—>u) and II1(11—>V) are
`initialized to be zero, and mO(u) is initialized to be the
`log-likelihood ratio based on the channel receiVed informa-
`tion. If the charmel is memoryless, i.e., each channel output
`only relies on its input, and y is the output of the channel
`code bit u,
`then mO(i):log(p(u:0|y)/p(u:1|y)). After this
`initialization,
`the decoding process may run in a fully
`parallel and local manner. In each iteration, eVery Variable/
`check node receiVes messages from its neighbors, and sends
`back updated messages. Decoding is terminated after a fixed
`number of iterations or detecting that all the constraints are
`satisfied. Upon termination, the decoder outputs a decoded
`sequence based on the messages m(u):Zwm(w—>u).
`Thus, on Various channels, iteratiVe decoding only dilfers
`in the initial messages mO(u). For example, consider three
`memoryless charmel models: a binary erasure channel
`(BEC); a binary symmetric charmel (BSC); and an additiVe
`white Gaussian noise (AGWN) charmel.
`In the BEC, there are two inputs and three outputs. When
`0 is transmitted,
`the receiVer can receiVe either 0 or an
`erasure E. An erasure E output means that the receiVer does
`not know how to demodulate the output. Similarly, when 1
`is transmitted, the receiVer can receiVe either 1 or E. Thus,
`for the BEC, yE{0, E, 1}, and
`
`111004) =
`
`+00
`0
`—oo
`
`ify=O
`ify=E
`ify=l
`
`In the BSC, there are two possible inputs (0,1) and two
`possible outputs (0, 1). The BSC is characterized by a set of
`
`6
`conditional probabilities relating all possible outputs to
`possible inputs. Thus, for the BSC yE{0, 1},
`
`711004) =
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`and
`
`In the AWGN, the discrete-time input symbols X take
`their Values in a finite alphabet while channel output sym-
`bols Y can take any Values along the real line. There is
`assumed to be no distortion or other effects other than the
`addition of white Gaussian noise. In an AWGN with a
`
`Binary Phase Shift Keying (BPSK) signaling which maps 0
`to the symbol with amplitude «E5 and 1 to the symbol with
`amplitude —\/Es, output yER, then
`mo(“)fil.V‘/E/No
`
`where NO/2 is the noise power spectral density.
`The selection of a degree profile for use in a particular
`transmission charmel is a design parameter, which may be
`affected by Various attributes of the charmel. The criteria for
`selecting a particular degree profile may include,
`for
`example,
`the type of channel and the data rate on the
`channel. For example, Table 1 shows degree profiles that
`haVe been found to produce good results for an AWGN
`channel model.
`
`a
`
`L2
`L3
`L5
`L6
`M0
`M1
`M2
`M3
`M4
`M6
`A27
`A28
`Rate
`OGA
`0*
`(Eb/N0) * (dB)
`S.L. (dB)
`
`TABLE 1
`
`2
`
`0.139025
`0.2221555
`
`0.638820
`
`3
`
`0.078194
`0.128085
`0.160813
`0.036178
`
`0.108828
`0.487902
`
`0.333364
`1.1840
`1.1981
`0.190
`—0.4953
`
`0.333223
`1.2415
`1.2607
`-0.250
`—0.4958
`
`4
`
`0.054485
`0.104315
`
`0.126755
`0.229816
`0.016484
`
`0.450302
`0.017842
`0.333218
`1.2615
`1.2780
`-0.371
`—0.4958
`
`Table 1 shows degree profiles yielding codes of rate
`approximately 1/3 for the AWGN charmel and with a:2, 3, 4.
`For each sequence,
`the Gaussian approximation noise
`threshold, the actual sum-product decoding threshold and
`the corresponding energy per bit (Eb)-noise power (N0) ratio
`in dB are giVen. Also listed is the Shannon limit (S.L.).
`As the parameter “a” is
`increased,
`the performance
`improVes. For example, for a:4, the best code found has an
`iteratiVe decoding threshold of Eb/NO:—0.371 dB, which is
`only 0.12 dB aboVe the Shannon limit.
`The accumulator component of the coder may be replaced
`by a “double accumulator” 600 as shown in FIG. 6. The
`double accumulator can be Viewed as a truncated rate 1
`
`conVolutional coder with transfer function 1/(1+D+D2).
`AltematiVely, a pair of accumulators may be the added, as
`shown in FIG. 7. There are three component codes:
`the
`“outer” code 700, the “middle” code 702, and the “inner”
`
`

`
`US 7,116,710 B1
`
`7
`code 704. The outer code is an irregular repetition code, and
`the middle and inner codes are both accumulators.
`
`IRA codes may be implemented in a variety of channels,
`including memoryless channels, such as the BEC, BSC, and
`AWGN, as well as channels having non-binary input, non-
`symmetric and fading charmels, and/or channels with
`memory.
`A number of embodiments have been described. Never-
`
`theless, it will be understood that various modifications may
`be made without departing from the spirit and scope of the
`invention. Accordingly, other embodiments are within the
`scope of the following claims.
`The invention claimed is:
`
`1. A method of encoding a signal, comprising:
`obtaining a block of data in the signal to be encoded;
`partitioning said data block into a plurality of sub-blocks,
`each sub-block including a plurality of data elements;
`first encoding the data block to from a first encoded data
`block, said first encoding including repeating the data
`elements in different sub-blocks a different number of
`times;
`interleaving the repeated data elements
`encoded data block; and
`second encoding said first encoded data block using an
`encoder that has a rate close to one.
`
`in the first
`
`2. The method of claim 1, wherein said second encoding
`is via a rate 1 linear transformation.
`
`3. The method of claim 1, wherein said first encoding is
`carried out by a first coder with a variable rate less than one,
`and said second encoding is carried out by a second coder
`with a rate substantially close to one.
`4. The method of claim 3, wherein the second coder
`comprises an accumulator.
`5. The method of claim 4, wherein the data elements
`comprises bits.
`6. The method of claim 5, wherein the first coder com-
`prises a repeater operable to repeat different sub-blocks a
`different number of times in response to a selected degree
`profile.
`7. The method of claim 4, wherein the first coder com-
`prises a low-density generator matrix coder and the second
`coder comprises an accumulator.
`8. The method of claim 1, wherein the second encoding
`uses a transfer function of 1/(1+D).
`9. The method of claim 1, wherein the second encoding
`uses a transfer function of 1/(1+D+D2).
`10. The method of claim 1, wherein said second encoding
`utilizes two accumulators.
`
`11. A method of encoding a signal, comprising:
`receiving a block of data in the signal to be encoded, the
`data block including a plurality of bits;
`first encoding the data block such that each bit in the data
`block is repeated and two or more of said plurality of
`bits are repeated a different number of times in order to
`form a first encoded data block; and
`second encoding the first encoded data block in such a
`way that bits in the first encoded data block are accu-
`mulated.
`12. The method of claim 11, wherein the said second
`encoding is via a rate 1 linear transformation.
`13. The method of claim 11, wherein the first encoding is
`via a low-density generator matrix transformation.
`14. The method of claim 11, wherein the signal to be
`encoded comprises a plurality of data blocks of fixed size.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`8
`
`15. A coder comprising:
`a first coder having an input configured to receive a stream
`of bits, said first coder operative to repeat said stream
`of bits irregularly and scramble the repeated bits; and
`a second coder operative to further encode bits output
`from the first coder at a rate within 10% of one.
`16. The coder of claim 15, wherein the stream of bits
`includes a data block, and wherein the first coder is operative
`to apportion said data block into a plurality of sub-blocks
`and to repeat bits in each sub-block a number of times,
`wherein bits in different sub-blocks are repeated a different
`number of times.
`17. The coder of claim 16, wherein the second coder
`comprises a recursive convolutional encoder with a transfer
`function of 1/(1+D).
`18. The coder of claim 16, wherein the second coder
`comprises a recursive convolutional encoder with a transfer
`function of 1/(1+D+D2).
`19. "he coder of claim 15, wherein the first coder com-
`prises a repeater having a variable rate and an interleaver.
`20. "he coder of claim 15, wherein the first coder com-
`prises a low-density generator matrix coder.
`21. The coder of claim 15, wherein the second coder
`comprises a rate 1 linear encoder.
`22. The coder of claim 21, wherein the second coder
`comprises an accumulator.
`23. The coder of claim 22, wherein the second coder
`further comprises a second accumulator.
`24. The coder of claim 15, wherein the second coder
`comprises a coder operative to further encode bits output
`from the first coder at a rate within 1% of one.
`
`25. A coding system comprising:
`a first coder having an input configured to receive a stream
`of bits, said first coder operative to repeat said stream
`of bits irregularly and scramble the repeated bits;
`a second coder operative to further encode bits output
`from the first coder at a rate within 10% of one in order
`to form an encoded data stream; and
`a decoder operative to receive the encoded data stream
`and decode the encoded data stream using an iterative
`decoding technique.
`26. The coding system of claim 25, wherein the first coder
`comprises a repeater operative to receive a data block
`including a plurality of bits from said stream of bits and to
`repeat bits in the data block a different number of times
`according to a selected degree profile.
`27. The coding system of claim 26, wherein the first coder
`comprises an interleaver.
`28. The coding system of claim 25, wherein the first coder
`comprises a low-density generator matrix coder.
`29. "he coding system of claim 25, wherein the second
`coder comprises a rate 1 accumulator.
`30. "he coding system of claim 25, wherein the decoder
`is operative to decode the encoded data stream using a
`posterior decoding techniques.
`31. "he coding system of claim 25, wherein the decoder
`is operative to decode the encoded data stream based on a
`Tanner graph representation.
`32. "he coding system of claim 25, wherein the decoder
`is operative to decode the encoded data stream in linear time.
`33. "he coding system of claim 25, wherein the second
`coder comprises a coder operative to further encode bits
`output from the first coder at a rate within 1% of one.
`*
`*
`*
`*
`*
`
`

`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`CERTIFICATE OF CORRECTION
`
`PATENT NO.
`APPLICATION NO.
`
`: 7,116,710 B1
`: 09/861102
`
`DATED
`INVENTOR(S)
`
`: October 3, 2006
`: Hui Jin, Aamod Khandekar and Robert J. McE1iece
`
`It is certified that error appears in the above—identified patent and that said Letters Patent is
`hereby corrected as shown below:
`
`At column 1, line 8, please amend the paragraph as follows:
`
`This application claims Q priority [[to]] o_f U.S. Provisional
`
`Application Ser. No. 60/205,095, filed on May 18, 2000, and [[to]]
`
`is a continuation-in-part of U.S. application Ser. No. 09/922,852, filed on Aug.
`
`18, 2000 and entitled Interleaved Serial Concatenation Forming Turbo-Like
`
`Codes.
`
`Signed and Sealed this
`
`Twenty—second Day of July, 2008
`
`MWQDA
`
`JON W. DUDAS
`Director ofthe United States Patent and Trademark Oflice