(12) United States Patent
`Nara
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,377,617 B1
`Apr. 23, 2002
`
`US006377617B1
`
`(54) REAL-TIME SIGNAL ANALYZER
`
`(75) Inventor: Akira Nara, Tokyo (JP)
`
`(73) Assignee: Sony/Tektronix Corporation, Tokyo
`(JP)
`
`( * ) Notice:
`
`(21) Appl. No.:
`(22) PCT Filed?
`(86) PCT NO‘:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`USC 154(b) by 0 days.
`09/319,426
`Dec- 9! 1997
`PCT/JP97/04511
`
`§ 371 Date:
`
`Jun. 4, 1999
`
`§ 102(e) Date: Jun. 4, 1999
`_
`(87) PCT Pub’ NO" “logs/26298
`PCT Pub, Date; Jun, 18, 1998
`_
`_
`_
`_
`_
`Forelgn Apphcatlon Pnonty Data
`(30)
`Dec. 11, 1996
`(JP) ........................................... .. 8-346519
`(51) Int Cl 7
`H0413 3 / 4 6
`................................................ ..
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`.
`'
`(52) U..S. Cl. ...................................... .. 375/224, 375/346
`Fleld Of Search ............... .............. ..
`375/
`231802’
`704/203 702/97 3i4/76’21_ 5645/76 4155/1/90 1’
`’
`’
`'
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`‘£34 455
`’
`’
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,576,978 A 11/1996 Kiiayoshi .................. .. 702/77
`5,697,078 A * 12/1997 Peterson et al. ....... .. 455/190.1
`5,760,308 A * 6/1998 Beall 618.1. ................. .. 73/644
`5,764,763 A * 6/1998 Jensen et al. ................ .. 380/6
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`
`0 285 238
`
`10/1988
`
`* Cited by examiner
`
`Primary Examiner—Chi Pham
`Assistant Examiner—Emmanuel Bayard .
`(74) Attorney, Agent, or Ftrm—Sm1th-H1ll and Bedell
`
`(57)
`
`ABSTRACT
`
`This invention relates to a neW type real time signal analyzer
`that has both merits of a conventional real time FFT analyzer
`and a conventional vector signal analyzer and clears both
`demerits of them. This apparatus has a FFT processor 14 for
`FFT processing time domain data in real time, a FIFO
`memory 22 for delaying the time domain data before the
`FFT process, and a double port memory 24 for storing FFT
`processed frequency data from the FFT processor 14 and
`delayed time domain data read out from the FIFO memory
`The delay time of the
`memory
`is Set up
`according to the process time of the FFT processor 14 that
`alloWs to secure time correspondence betWeen the delayed
`time domain data and the frequency domain data. Therefore
`it respectively provides the data of the time domain and the
`freqlilency (131E211; inhreal time at the same time that are
`sync romze eac ot er.
`
`5,479,440 A * 12/1995 Esfahani ................... .. 375/346
`
`9 Claims, 2 Drawing Sheets
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`22
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`FIFO
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`>
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`10
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`12
`/
`
`—> ADC > DDC
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`F F T
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`24
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`20
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`> CPU
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`DOUBLE
`PORT
`M E M ROY
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`14
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`18
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`TRIGGER
`
`Apple 1066
`U.S. Pat. 8,504,746
`
`

`
`U.S. Patent
`
`Apr. 23, 2002
`
`Sheet 1 0f 2
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`US 6,377,617 B1
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`22
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`24
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`20
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`1O
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`12
`/
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`F'FO
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`' DOUBLE
`PORT
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`> CPU
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`——+ ADC > DDC
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`F FT
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`MEMROY
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`14
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`18
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`TRIGGER
`
`/24
`FIFO'1
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`26
`/
`F|FO2
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`32
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`MEMORY
`BANK
`1
`> WE RE <—O—> WE RE <—T—> WE RE
`
`FF
`
`EF
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`—>-Q
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`1‘
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`/14
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`F F T
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`_
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`> WE IRE
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`0
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`M
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`28
`/
`F|F03
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`34
`/
`MEMORY
`BANK
`2
`> WE RE < H WE RE
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`‘ FF
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`EF
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`r
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`CONTROL
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`A
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`\
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`30
`AV /
`
`FIG.2
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`

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`U.S. Patent
`
`Apr. 23, 2002
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`Sheet 2 0f 2
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`US 6,377,617 B1
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`10
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`12
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`14
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`16
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`20
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`—> ADC ~ DDC > FFT
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`MEMORY > CPU
`M
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`TRIGGER
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`\12;
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`FIG.3
`PRIOR ART
`
`10
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`12
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`16
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`17
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`20
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`—> ADC > DDC
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`MEMORY > DSP > CPU
`1
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`TRIGGER
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`\1s
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`FIG.4
`PRIOR ART
`
`

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`US 6,377,617 B1
`
`1
`REAL-TIME SIGNAL ANALYZER
`
`TECHNICAL FIELD
`
`The present invention relates to a signal analyzer that can
`analyZe a signal in real time, more particularly to a neW type
`real time signal analyZer that has both merits of a conven
`tional real time FFT analyZer and a conventional vector
`signal analyZer and clears both demerits of them.
`
`BACKGROUND ART
`
`10
`
`A real time FFT analyZer is a measurement apparatus that
`continuously transform a signal under test by FFT process in
`real time Without dead time in order to extract and analyZe
`the spectrum domain component from the signal.
`FIG. 3 shoWs a schematic block diagram of such a
`conventional FFT analyZer that provides real time process.
`An analog to digital converter (ADC) 10 converts a signal
`under test into a digital signal and a digital doWn converter
`(DDC) 12 decimates the digital signal for substantial fre
`quency conversion. A FFT processor 14 transforms the
`resultant time domain digital data, for example, 1024 points
`of the time domain data as one frame, into frequency domain
`digital data according to the FFT process. The DDC 12 has
`a sequential data buffer (not shoWn) in the output portion
`that stores the one frame data sequentially and continuously.
`The FFT processor 14 can complete the FFT process of the
`previous frame during the storage of the neW data into the
`data buffer that alloWs real time data analysis. Amemory 16
`stores the output data of the FFT processor 14 sequentially.
`A trigger circuit 18 can set up a trigger condition to the
`data in the memory 16. If the trigger condition is satis?ed,
`the trigger circuit 18 output a trigger signal to read out the
`data that quali?es the trigger condition. A CPU 20 Wholly
`controls the real time analyZer. The data read out from the
`memory 16 are sent to a display circuit (not shoWn) to
`display them on a screen (not shoWn). This real time FFT
`analyZer can extract spectrum (frequency component) in real
`time Without dead time and could catch an event occurrence
`that meets an arbitrary trigger condition.
`FIG. 4 shoWs a schematic block diagram of an example of
`a conventional vector signal analyZer. Elements correspond
`ing to that of FIG. 3 have the same reference symbols. A
`memory 16 stores output data of a DDC 12 and the stored
`data are transferred to a digital signal processor (DSP) 17 to
`execute analytic processes such as a FFT process. The vector
`signal analyZer of this type is suitable for demodulating
`various modulated vector signals and provides a ?exible
`signal analysis because it executes the various analytic
`processes after storing the time domain data in the memory
`16.
`The real time FFT analyZer of FIG. 3, hoWever, must
`transform the frequency domain data in the memory by the
`inverse FFT process in order to reproduce the time domain
`data for analyZing the digital modulated signal in time
`domain displays such as “eye pattern” or “constellation”.
`Besides, a FFT process multiplied by a WindoW function
`makes it impossible to completely reproduce the original
`time domain signal.
`One the other hand, it is difficult for the vector signal
`analyZer of FIG. 4 to produce the frequency domain data in
`real time because the data in the memory are the time
`domain data. Therefore it is difficult to catch a transient
`?uctuation of the frequency spectrum.
`As described, the real time FFT analyZer and the vector
`signal analyZer are used in different Ways and the merits and
`the demerits of them counter each other.
`
`2
`Therefore What is desired is to provide a real time signal
`analyZer that has both merits of the conventional real time
`FFT analyZer and the conventional vector signal analyZer
`and clears both demerits of them.
`
`DISCLOSURE OF INVENTION
`
`A real time signal analyZer according to the present
`invention has a FFT processor that transform time domain
`data by FFT process in real time, a delay means for delaying
`the time domain data, a memory means for storing frequency
`domain data transformed by the FFT process from the FFT
`processor, and a memory means for storing delayed time
`domain data read out from the delay means.
`Delay time of the delay means is set up according to the
`process time of the FFT processor, then time correspondence
`betWeen the delayed time domain data and the frequency
`domain data is secured. Therefore it generates the time
`domain data and the frequency domain data in real time
`respectively but having the time correspondence each other.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`FIG. 1 is a schematic block diagram shoWing a preferred
`example embodying the invention.
`FIG. 2 shoWs detail operation of a preferred example
`embodying the invention.
`FIG. 3 is a schematic block diagram of an example of a
`conventional real time FFT analyZer.
`FIG. 4 is a schematic block diagram of an example of a
`conventional vector signal analyZer.
`
`BEST MODE FOR CARRYING OUT THE
`INVENTION
`
`FIG. 1 shoWs a schematic block diagram of a preferred
`example embodying the invention. An analog to digital
`converter (ADC) 10 converts a signal under test into digital
`data and a digital doWn converter (DDC) 12 decimates the
`data for frequency conversion. At this time, 1024 points, for
`example, of the time domain data are produced as one frame
`data in real time. This data length of one frame is just an
`example and an arbitrary value may be selected according to
`speci?cation of data display or an analytic function.
`A FFT processor 14 transforms the time domain data by
`FFT process and, at this time, multiplies it by a WindoW
`function if necessary. On the other hand, the time domain
`data, or the output of the DDC 12, are also provided to a ?rst
`in ?rst out memory (FIFO) 22. The FIFO 22 is a delay means
`for delaying the time domain data With corresponding to the
`time required to transform the time domain data by the FFT
`process. The output data of the FFT processor 14 is fre
`quency domain data shoWing spectrum component of the
`signal under test, and this frequency domain data is stored in
`a double port memory 24 through the ?rst port. The delayed
`time domain data from the FIFO 22 is stored in the double
`port memory 24 through the second port. The delayed time
`domain data and the frequency domain data stored in the
`double port memory 24 are provided to a display circuit (not
`shoWn) and a display screen (not shoWn) under the control
`of a CPU 20 and displayed in appropriate styles. The display
`circuit and the display screen may be a CRT, a liquid crystal
`display or any other proper devices. Besides, a printer or a
`plotter is connected to be out the analyZed data on a paper.
`It is not indispensable for the present invention to use the
`double port memory 24 as described above. The delayed
`time domain data and the frequency domain data could be
`stored in different memories. The key of the present inven
`
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`US 6,377,617 B1
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`3
`tion is not the memory construction but the simultaneous
`availability of the time domain data and the frequency
`domain data that are synchroniZed. This alloWs the CPU 20
`an arbitrary analysis of the time domain data and the
`frequency domain data that have time correspondence each
`other. The present invention also provides reliable catches of
`transient and incidental signal ?uctuations etc. because the
`time domain data and the frequency domain data are
`acquired Without time crack, or dead time. Besides, because
`the time correspondence betWeen the time domain data and
`the frequency domain data is secured, it is easy to compare
`them and Watch hoW they change by transient change or
`incidental ?uctuation With, for example, displaying their
`Waveforms on the screen. It should be remarkable that the
`comparison and observation described above used to be
`Wholly impossible for the conventional real time FFT ana
`lyZer or vector signal analyZer.
`FIG. 2 shoWs a detailed block diagram of an eXample
`embodying the invention. FIG. 2 shoWs ?oWs of control
`signals, but ?oWs of a signal under test and the processed
`data are abbreviated. As for the data ?oWs in the process of
`the signal under test, please refer to FIG. 1.
`The digital doWn converter (DDC) 12 of FIG. 1 provides
`a Write enable signal to Write enable terminals
`of the
`FFT processor 14 and a FIFO1 (24) When it provides the
`time domain data to the FFT processor 14 and the FIFO1
`(24). Then the FFT processor 14 and the FIFO1 (24) receive
`the time domain data sequentially. The FFT processor 14
`outputs a read enable signal after the FFT process. The read
`enable signal is provided to a read enable terminal (RE) of
`the FIFO1 (24), a Write enable terminal
`of a FIFO2
`(26) and a Write enable terminal
`of a FIFO3 (28). Then
`the FFT processor 14 provides the FFT processed frequency
`data to the FIFO3 (28) While the delayed time domain data
`read out from the FIFO1 (24) is send to the FIFO2 (26).
`Wherein it is desirable to make the capacities of the memory
`FIFO1 (24), FIFO2 (26) and FIFO3 (28) equal to the data
`volume of the one frame, for eXample, 1024 points.
`If the FIFO2 (26) and the FIFO3 (28) ?ll With the data,
`they generate full ?ag signals
`that are provided to a
`control circuit 30. And if the FIFO2 (26) and the FIFO3 (28)
`empty the data, they generate empty ?ag signals
`that
`are provided to the control circuit 30. If the control circuit
`30 receives the full ?ag signal, it generates a data available
`signal (AV). The AV signal is provided to read enable
`terminals (RE) of the FIFO2 (26) and the FIFO3 (28), and
`Write enable terminals of a memory bank 1 (32) and a
`memory bank 2 (34). Therefore the data are read out from
`the FIFO2 (26) and the FIFO3 (28), the memory bank 1 (32)
`stores the delayed time domain data, and the memory bank
`2 (34) stores the frequency domain data. The memories 32
`and 34 can consist of the independent memories as shoWn in
`FIG. 2 or be different memory areas of a double port
`memory as shoWn in FIG. 1.
`The FIFO2 (26) and the FIFO3 (28) have different clock
`frequencies betWeen the data inputs and the data outputs.
`That is, the clock frequency of the read out is set loWer than
`that of the Write. This alloWs proper data storage into a loWer
`clocked memory. For eXample, the clock frequency of the
`data from the FFT processor 14 to the FIFO3 (28) may be
`40 MHZ While the clock frequency of the output data from
`the FIFO3 (28) may be 14 MHZ. OtherWise, the FIFO2 (26)
`and the FIFO3 (28) are not necessary if the clock frequency
`conversion is not necessary.
`Although the invention has been shoWn and described
`With using preferred embodiments, it Would be understand
`
`4
`for the skilled in the art that the present invention is not
`limited in the above embodiments and has many other
`modi?cations according the principle.
`A real time signal analyZer according to the present
`invention can provide simultaneous real time generation of
`the time domain and frequency domain data that are time
`correspondent and simultaneous. Therefore a neW type real
`time signal analyZer can be realiZed that has both merits of
`a conventional real time FFT analyZer and a conventional
`vector signal analyZer and clears both demerits of them.
`
`INDUSTRIAL APPLICABILITY
`
`15
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`45
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`55
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`65
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`As described above, a real time signal analyZer according
`to the present invention can provide simultaneous real time
`generation of the time domain data and the frequency
`domain data and store them. This alloWs to identify a
`frequency domain data that has time correspondence to a
`speci?c time domain data, While to identify a time domain
`data that has time correspondence to a speci?c frequency
`domain data. Therefore it provides a neW type signal analy
`sis that used to be impossible, that is, real time analysis of
`time domain and frequency domain that have time corre
`spondence each other.
`What is claimed is:
`1. A real time signal analyZer comprising:
`a FFT processor for FFT processing time domain data in
`real time;
`a delay means for delaying the time domain data;
`a frequency domain data memory means for storing
`frequency domain data from the FFT processor that has
`FFT processed; and
`a time domain data memory means for storing delayed
`time domain data read out from the delay means;
`Wherein the delay time of the delay means is set up
`according to the process time of the FFT processor.
`2. A real time signal analyZer according to claim 1,
`Wherein the frequency domain data memory means and the
`time domain data memory means start the storage of the
`delayed time domain data and the frequency domain data,
`respectively, at the substantial same time.
`3. Areal time signal analyZer according to claim 1 further
`comprising:
`an analog to digital converter for receiving an analog
`signal and producing the time domain data.
`4. Areal time signal analyZer according to claim 3 further
`comprising:
`a frequency converter for converting the frequency of the
`output data of the analog to digital converter by deci
`mating the data according to a variable decimation
`factor.
`5. Areal time signal analyZer according to claim 1 further
`comprising:
`a ?rst clock frequency converter provided betWeen the
`delay means and the time domain data memory means;
`and
`a second clock frequency converter provided betWeen the
`FFT processor and the frequency domain data memory
`means;
`Wherein the input data speeds of the ?rst and second clock
`frequency converters are sloWer than the output data
`speeds of that.
`6. A real time signal analyZer according to claim 5,
`Wherein the ?rst and second clock frequency converters are
`FIFO memories.
`
`

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`US 6,377,617 B1
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`5
`7. A real time signal analyzer comprising:
`an analog to digital converter for converting an input
`analog signal into digital data;
`a frequency converter for converting output data of the
`analog to digital converter by decimation process
`according to a variable decimation factor;
`a FFT processor for FFT processing time domain data
`from the frequency converter;
`a delay means for delaying the time domain data,
`a ?rst clock frequency converter for storing the time
`domain data from the delay means according to the
`process completion of the FFT processor;
`a second clock frequency converter for storing frequency
`domain data from the FFT processor according to the
`process completion of the FFT processor;
`
`10
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`6
`a time domain data memory means for receiving the time
`domain data from the ?rst clock frequency converter;
`and
`a frequency domain data memory means for receiving the
`frequency domain data from the second clock fre
`quency converter;
`Wherein the delay time of the delay means is set up
`according to the process time of the FFT processor.
`8. A real time signal analyZer according to claim 7
`Wherein the frequency converter has a data buffer memory
`for storing the time domain data after the frequency con
`version.
`9. A real time signal analyZer according to claim 1,
`Wherein the delay means is a FIFO memory.
`
`*
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