Chapter 8
`
`such as mice and other pointing devices, as well as specialized devices such as
`data—acquisition units and controllers.
`
`For example, a data acquisition unit might send periodic sensor readings to a
`PC. The controller chip’s I/ O pins could connect to analog—to»digital cone
`verters that convert sensor readings to digital signals. A host PC could use
`the USB link to request the latest readings periodically. Or the PC might
`send signals to control relays, motors, or other devices that the chips I/ O
`pins control.
`
`Instead of just repeating what’s in the chips data sheet, I’ll focus on whats
`important to know before you start working with the chip. I’ll also explain
`anything that I found difficult or confusing to understand from the data
`sheet alone. When it’s time to use the chip, check the data sheet for details.
`
`Features and Limits
`
`One compelling reason for choosing the 363743 for a project is inexpensive
`chips. Typical prices for the chip are a few dollars each in small quantities.
`And the chip contains an internal oscillator that eliminates the need to pro-
`vide an external timing reference.
`
`The chip is available in both through~hole (DIP) and surface~mount
`(SOIC) packages. If you have experience with assemblyelanguage programr
`ming (or are willing to learn), the assembly~code instructions aren’t too hard
`to master. The chip has 8 Kilobytes of program memory. With optimiza»
`tion, the code required to support USB communications can fit in l Kilo»
`byte, leaving 7 Kilobytes for other functions.
`
`The essential tool for developing is the Developer’s Kit, which includes a
`development board, assembler, and debugging application. You’ll probably
`also want the CY3649 Hi-Lo PROM Programmer with the adapter base
`and matrix card for the enCoRes, all available from Cypress.
`
`The ’63743 isn’t suitable for every projecr. The chip is low speed, which
`means that you can’t use bulk or isochronous transfers and the fastest maxi”
`mum latency for interrupt transfers is 8 bytes per 10 milliseconds. Unlike
`some early controllers, the ’63743 does support Interrupt OUT transfers. It
`
`182
`
`USB Complete
`
`,Appie 1062 (Part 2. of 3)
`yU.S. Pat. No. 9,189,437
`
`Apple 1062 (Part 2 of 3)
`U.S. Pat. No. 9,189,437
`
`

`

`Inside a USB Controller: the Cypress enCoRe
`
`
`
`
`INTERNAL
`OSCILLATOR
`
`XTAL
`OSCILLATOR
`
`WAKE'UP
`TIMER
`
`RAM
`256 BYTES
`
`12-BIT
`TIMER
`
`CAPTURE
`TIMERs
`
`SP1
`
`
`
`
`
`RIsc
`
`
`
`
`
`
`
`
`
`
`
`
`EPROM
`g
`L
`6K/8K 3::::>+fCORE
`<3
`:>
`
`
`BROWN OUT
`AT
`
`
`
`
`
`
`
`
`PO.O—PO.7 VREG
`
`RESET
`
`
`WATCH
`DOG
`TIMER
`
`LOW
`VOLTAGE
`RESET
`
`INTERRUPT
`CONTROLLER ‘3‘
`
`use
`ENGINE
`
`PORT I
`GPIO
`
`PORT O
`GPIO
`
`A
`
`
`-——————~
`
`3.3V
`
`REGULATOR
`
`PI.O-PI.7
`
`Figure 8-2: The Chips in Cypress’ enCoFie series have the essentials for USB
`communications and general port l/O.
`
`you can get by with less memory or 1/0, the series has chips with 6K of pro—
`gram memory and twelve I/O pins.
`
`Inside the Chip
`
`Figure 8—2 shows the chip’s architecture. The CPU is an 8—bit RISC
`(reduced instruction set computer). It can access program memory, RAM,
`general—purpose l/O ports, and of course, a USB port. The USB port is
`actually an auto—switching port that supports both USB and the PS/Z inter—
`face for mice and other pointing devices. This feature is handy for designing
`devices that can plug into either port type. A variety of interrupt and reset
`sources can interrupt the CPU.
`
`The frequency of the internal 6—Megahertz oscillator is accurate to within
`1.5%, as required, for low—speed USB. If an application requires a more pre—
`cise clock source, the chip can instead use an external oscillator.
`
`USB Complete
`
`183
`
`

`

`Chapter 8
`
`Figure 8—3 shows the pinouts of the ’63743 and the ’63723, Which has four
`fewer I/O pins.
`
`Memory
`
`The on~chip memory of the 363743 consists of 8 kilobytes (OOOOh to
`lFFFh) of OTP PROM for program storage and 256 bytes ofRAM (00h to
`FFh) fer temporary data storage. There are also 34 byte—Wide l/O registers,
`each with a defined purpose.
`
`The organization of the program memory is similar to that of other micro»
`controllers. Program execution begins at 00h. Addresses 00h and 01h con~
`tain a jump to the address Where the main program code begins. Addresses
`02h through 17h are interrupt vectors that hold the addresses to jump to
`when one of the chips eleven interrupts occurs. Here is an example inter»
`rupt—vecror table in firmware:
`
`ORG 00h
`
`jmp
`
`reset
`
`; device reSet
`
`jmp bue_reset
`jmp
`error
`jmp
`lmswtimer
`jmp
`endpointO
`
`; USB reset interrupt
`;
`lZS—microsecond interrupt
`~.
`11024—millisecond interrupt
`~.
`Endpoint
`O interrupt
`
`
`
`
`P®.®_l V 74
`
`
`
`
`
`7
`P01
`25
`
`
`P®.2
`
`P®.3
`
`
`P1.®
`
`
`
`
`P®.3:4
`
`P1.®:5
`
`vss“6
`
`VPP
`VREG
`
`XTALiN/P2.1
`
`7
`8
`
`9
`
`
`
`
`
`16 "Pe.6
`
`15_P®.7
`
`
`
`
`14
`
`13
`
`P1.1
`
`D+/SCLK
`
`l2EDe/SDATA
`11_vcc
`
`
`
`P®.e:1 U l8:lP®.4
`
`
`
`P®,i"2
`17
`P05
`
`P0.2'“ 3
`
`3
`4
`5
`
`
`P1.2“ 6
`
`
`
`P1.4|:7
`
`Pi.6"8
`
`vssEQ
`
`VPPEIQ
`
`VREGTll
`
`
`
`
`P04
`P®.5
`
`
`
`
`
`
`
`22TP®.6
`
`21"P@.7
`2®:]Pi.i_
`
`19 :lPl.3
`
`
`18
`
`P15
`
`1
`
`-P1.7
`
`16:D+/SCLK
`
`l5:lD—/SDATA
`
`14—vcc
`
`
`13
`
`XTALOUT
`
`l®:><T/\LOUT XTALIN/P2.1:l2
`
`CY7C63722/23
`
`'cv7cas742/43
`
`Figure 8—3: The enCoRe series includes chips with 12 and 16 1/0 pins.
`
`184
`
`USB Complete
`
`

`

`Inside a USB Controller: the Cypress enCoRe
`
`jmp
`jmp
`jmp
`
`endpointl
`endpoint2
`spi
`
`capture_a
`jmp
`capture_b
`jmp
`jmp gpio
`
`l interrupt
`; Endpoint
`; Endpoint 2 interrupt
`; SP1 interrupt
`
`; Capture timer A interrupt
`; Capture timer B interrupt
`; GPIO interrupt
`
`jmp wakeup
`
`; Wake—up interrupt
`
`Each interrupt vector jumps to the location specified by a label. Unused
`interrupts should never occur, but the firmware should include jumps even
`for these interrupts. A typical interrupt—service routine (ISR) for an unused
`interrupt would just return the firmware to the calling location with regis—
`ters unchanged.
`
`The interrupt vectors are stored in order of priority, with the highest priority
`at 000211. Program memory from 0018b to IFDFh is available for storing
`the rest of the code.
`
`The 256 bytes of RAM must hold two data stacks and 8 bytes each of buffer
`data for Endpoints 0, 1, and 2 (if all are used), as well as any other tempo—
`rary data (Figure 8—4). The endpoint buffers use addresses E8h through
`FFh.
`
`The stacks are last in, first out (LIFO) structures for short—term storage of
`addresses and register contents. The RAM has two pointers for accessing the
`two stacks. The Program Stack Pointer (P8P) begins at 0011 on reset and
`grows up, while the Data Stack Pointer (USP) may be set by firmware to
`E8h or lower and grows down. The firmware needs to be sure that the stacks
`don’t grow so large that they bump into each other in the middle. To reserve
`general~purpose RAM for other uses, such as storage for variables, set the
`DSP to an address lower than E8h. This frees the locations from that
`
`address through E7h for other uses without having to worry that one of the
`stacks will overwrite them.
`
`The Program Stack Pointer
`
`The Program Stack Pointer (P5P) holds the address the code will jump to on
`returning from a call to a subroutine or interrupt—service routine. For inter;
`rupts, the PSP also stores the states of the zero and carry flags. The firmware
`
`USB Complete
`
`185
`
`

`

`Chapter 8
`
`EFH
`
`F8H
`
`FQH
`
`
`
`ENDPOINT Q
`
`
`ENDPOINT 1
`
`
`
`
`
`
`ml
`
`ENDPOINT 2
`
`
`USER VARIABLES
`
`AFTER RESET, FIRMWARE MUST
`
`SET THE DA“A STACK POINTER
`TO A VALUE LESS THAN E8H
`(TO ENABLE USING ALL
`
`3 USB ENDPOINTS).
`
`THE DATA STACK GROWS DOWN
`
`l /
`
`{\
`
`TH E PROGRAM STACK POINTER
`THE PROGRAM STACK GRows UP
`
`
`18 oOH ON RESET.
`49
`-
`
`Figure 8-4: The enCoRe’s RAM contains the USB endpoint buffers, the
`program and data stacks, and whatever variables the firmware requires.
`
`doesn’t have to do anything to manage the PSP. It’s all done automatically by
`the hardware and the CALL, RET, and RETI instructions.
`
`On reset, the PSP points to 00h. The PSP can handle multiple, nested sub‘
`routines and interrupts. Each routine returns to the instruction after the last
`instruction that executed before the call.
`
`For example, if the PSP is pointing to 00h when an instruction in program
`memory calls a subroutine, the CALL instruction will cause the PSP to save
`the address of the following instruction in addresses 00h and 01h. The
`CALL also increments the PSP by two bytes (to 02h in the example) so it’s
`ready to store another location if needed. The RET instruction that returns
`from the routine places the value pointed to by the PSP in the program
`counter and decrements the PSP by two. Program execution then continues
`where it left off before the routine was called.
`
`186
`
`USB Complete
`
`

`

`Inside a USB Controller: the Cypress enCoRe
`
`The same thing happens in interrupt—service routines, except that the values
`of the zero and carry flags are also saved and restored.
`
`The Data Stack Pointer
`
`The Data Stack Pointer (DSP) holds data stored by PUSH instructions. For
`example, PUSH A stores the contents of the accumulator on the data stack.
`The DSP decrements one byte before storing a byte. A POP instruction
`removes the most recently stored byte and increments the DSP.
`
`The default value of DSP on reset is not where it should remain. Unless the
`
`chip isn’t using USB at all, the firmware must set the DSP to a new value
`before doing any PUSH instructions. On reset, the DSP is 00h. From here,
`the first PUSH instruction would cause the DSP to decrement to the top of
`RAM (FFh), which is byte 7 in Endpoint 0’s buffer. For this reason, before
`pushing any bytes,
`the firmware should set the DSP pointer to E8h or
`lower:
`
`
`; Store the 389’s new beginning address
`;
`in the accumulator.
`mov A, 70h
`
`
`; Swap the contents of the accumulator with the DSP.
`swap A, dsp
`
`Use a lower value if you want to reserve more bytes for firmware use, or a
`higher value the firmware needs fewer bytes.
`
`USB Communications
`
`The firmware monitors and controls the serial interface engine (STE) by
`accessing registers. There are nine registers whose functions relate directly to
`USB communications: an address register, three endpoint mode registers,
`three endpoint counter registers, a status and control register, and an inter—
`rupt—enable register.
`
`Device Address
`
`The USB Device Address Register holds the 7—bit address assigned by the
`host during enumeration. The firmware must detect
`the Set_Address
`
`USB Complete
`
`187
`
`

`

`Chapter 8
`
`request, send a handshake in response to the request, and store the received
`address in this register. Bit 7 must be set to 1 to enable the serial interface
`engine to respond to USB traffic.
`
`Modes
`
`The USB Endpoint 0 Mode Register contains information about the last
`received data packet at Endpoint 0. Both the SIE and firmware can change
`the registers contents.
`
`Three PID bits indicate the type of the transactions token packet: Setup,
`IN, or OUT During the data phase ofa Setup transaction, the STE sets the
`Setup bit to 1. To prevent incoming data from being overwritten, the chip
`doesn’t allow firmware to write to any USB buffer while the Setup bit is l.
`Firmware can’t change this bit until all of the transactions data bytes have
`been received.
`
`The ACK bit is set when a transaction completes with ACK.
`
`Four Mode bits determine how the STE will respond to Setup, TN, and
`OUT transactions. Depending on the type of transaction, the firmware can
`request the SIE to return ACK, NAK, Stall, a 0—byte data packet, or nothing
`at all. In some cases, the STE changes the mode after a transaction’s ACK.
`For example, when the mode is Ach OUT, after returning an ACK in
`response to receiving OUT data, the SIE sets the mode to Nak OUT. This
`gives the firmware time to retrieve the data that was ACKed. After retrieving
`the data, the firmware can change the mode bits back to Ack OUT to enable
`accepting new data at the endpoint.
`
`For me, understanding the use of these mode bits was the most confusing
`part in using these chips. Cypress provides four pages of documentation
`about how the chip responds in every circumstance. I found it useful to
`group the modes according to what type of endpoint would use them, and
`in what situations. Table 8—3 shows the modes used by Endpoint 0. Each of
`these modes accepts Setup transactions, as control endpoints must.
`
`The complements to Endpoint 0’s mode register are the USB Endpoint 1
`Mode Register and USB Endpoint 2 Mode Register. These have the same
`
`188
`
`USB Complete
`
`

`

`Table 8~3: Modes used by Endpoint O in the USB Endpoint 0 Mode Register.
`
`Endpoint 0 must accept Setup transactions.
`Encod-
`
`Mode
`Responseto
`after
`Transaction
`
`ACK
`IN
`
`
`Setup
`same
`
`NAK
` Nak In/Out
`No transfer is in progress;
`
`waiting for a Setup transaction.
`
`same
`
`Control Read transfer, status
`Status Out Only
`stage. Return ACK on receiving
`a 0—byte data packet with the
`
`correct data toggle.
`
`Inside a USB Controller: the Cypress enCoRe
`
`Typical Use
`
`ing
`
`accept
`
`accept
`
`831116
`No transfer is in progress;
`waiting for a Setup transaction.
`same
`
`No transfer is in progress;
`ignore
`ignore
`waiting for a Setup transaction.
`same
`Stall
`Control Write transfer, status
`
`
` same
` data
`
`
`
`
`
`
`
`Stall In/Out
`
`Ignore In/Out
`
`
`Status In Only
`
`Ack Out ~
`Nak In
`
`Nak In ~
`Status Out
`
`
`
`
`
` 0100
`
`0—byte
`data
`stage. For an IN transaction,
`
`return a 0—byte data packet.
`S £11116
`NAK
` Nak Out —
`Control Write transfer, status
`
`Status In
`
`0—byte
`data
`stage. For an IN transaction,
`
`return a O—byte data packet.
`Nak
`Control Write transaction, data
`accept
`101 I
`stage.
`In/Out
`Control Read transfer, data or
`
`accept
`
`I
`
`l 10
`
`accept
`
`receiving a ()—byte data packet
`with the correct data toggle.
`Ack In ~
`Control Read transfer, data or
`Status Out
`status stage. For an IN
`transaction, return data. For an
`OUT transaction, return ACK on
`
`l
`
`|
`
`l
`
`l
`
`accept
`
` check Nak In
`
`— Status
`Out
`
`
`
`status stage. For an IN
`transaction, return NAK. For an
`OUT transaction, return ACK on
`
`receiving a 0—byte data packet
`
`with the correct data toggle.
`
`mode and ACK hits as Endpoint 0’s mode register. They don’t have the PID
`bits because these endpoints support either IN or OUT transactions only.
`These registers also each have a Stall bit.
`
`USB Complete
`
`189
`
`

`

`Chapter 8
`
`Endpoints l and 2 use different mode settings than Endpoint 0 because
`they never respond to Setup packets, while Endpoint 0 must do so. Table
`84 shows the modes used by Endpoints ] and 2. The table also shows how
`firmware can use the Stall bit to cause the STE to return. Stall in Ack In and
`
`Ack Out modes.
`
`Endpoint Status and Control
`
`Each of the three endpoints also has a USB Endpoint Counter Register
`that contains information about the data packet that is next to transmit, is
`being transmitted, or has just transmitted. Each contains a four—bit count, a
`data—toggle bit, and a data~valid bit.
`
`The four Byte Count bits hold the number of data bytes in a transaction.
`For IN transactions, the value indicates how many bytes will be sent from
`the endpoints buffer in the next transaction, not including the CRC bytes.
`Valid values are 0 through 8. For Setup and OUT transactions, the value
`indicates how many data bytes were received in the last transaction, plus the
`two CRC bytes. Valid values are 2 through 10. Setup and OUT counts are
`locked until the firmware reads the register.
`
`For Setup and OUT transactions, the Data Valid bit is 1 it the received
`CRC value was correct.
`
`The Data 0/ 1 Toggle bit indicates the data packets data toggle state, For lN
`transactions, firmware sets the value. For Setup and OUT transactions, the
`STE sets the bit to match the received data»toggle state.
`
`USB Status and Control
`
`The USB Status and Control register has two bits used in USB communi—
`cations, four bits that USB or PS/2 communications may use, and one bit
`for PS/Z communications only.
`
`The SlE sets the USB Bus Activity bit to 1 on detecting any USB activity or
`in other words, a non—idle bus. The firmware can use this bit along with the
`l~millisecond interrupt—service routine to decide whether the chip should
`
`190
`
`USB Complete
`
`

`

`Inside a USB Controller: the Cypress enCoRe
`
`Table 8—4: Modes used by Endpoints 1 and 2 in their USB Endpoint Mode
`
`Registers. Endpoints 1 and 2 don’t accept Setup transactions
`
`Typical Use
`
`
`Mode
`Encod- Response to
`
`after
`ing
`Transaction
`ACK
`OUT
`Setup
`IN
`
`
`
`
`
`
`
`Disable
`ignore
`The endpoint is disabled.
`—
`ignore
`ignore
`
`Nak Out
`
`ignore
`ignore NAK
`—
`An OUT endpointisn’tready to
`receive data.
`
`1000
`
`1001
`
`Ack Out
`(Stalle)
`W1
`Ack Out
`(Stallzl)
`
`ignore
`
`ignore
`ignore ACK
`Nak
`An OUT endpoint is ready to
`
`Out
`receive data.
`.
`.
`An OUT endpomt is halted.
`
`
`
`
`
`
`
`
`
`
`ignore
`
`stall
`
`—
`
`
`,._l
`W
`
`Nak In
`1100
`ignore NAK
`ignore
`—
`An IN endpoint has no data to
`send.
`
`
`Ack In (Stall—:0)
`
`l 10]
`
`ignore
`
`.J.
`data
`
`ignore Nak In An IN endpoint has data to send.
`
`Ack In (Stallzl)
`
`ignore
`
`stall
`
`ignore
`
`~
`
`An IN endpoint is halted.
`
`enter the Suspend state. If the bit remains 0 For more than three millisecr
`ends, the chip must enter the Suspend state.
`
`The VREG Enable bit can enable 33V at the chips VREG output. This
`output is intended for pulling up the USB’s pull—up resistor to D— on the
`bus. Because VREG is under firmware control, code can remove and restore
`
`the output voltage to simulate device removal and attachment. VREG’S out-
`put impedance is about 200 ohms, so the resistors value should be 1.3K to
`meet the l .5K specification.
`
`The USB Reset , PS/Z Activity Interrupt Mode bit selects whether to inter
`
`rupt on a USB reset or on PS/2 activity.
`
`Three Control bits enable firmware to set the USB or PS/2 lines to specific
`states,
`including USB’S J, K, and SEO states. If the host has previously
`enabled a device’s Remote—Wakeup ability with a Setheature request, the
`firmware can use the ForcerK state to send a Resume signal to tell the host
`that the device wants to communicate. Chapter 19 has more on resume sig—
`
`naling.
`
`USB Complete
`
`191
`
`

`

`Chapter 8
`
`The PS/Z Pullup Enable bit can enable internal pull—up resistors on the
`SCLK and SDATA lines used in PS/Z communications.
`
`The Port 2 Data Register holds the states of four read—only bit values at an
`auxiliary input port (Port 2).
`'lwo bits are the states of D+ and D— when
`using USB, or the states of SCLK and SDATA when using PS/Zr The other
`two bits can sometimes serve as general—purpose inputs. If the pull—up on
`USB’s D~ uses an external voltage source or if the device doesn’t support
`USB, the VREG output can be disabled and the pin can serve as a gen
`eral—purpose input whose state is read at P20. When the internal clock is
`enabled, there is no timing reference at XTALIN, and this pin can serve as a
`generalvpurpose input whose state is read at Bit P21.
`
`The final USBrrelated register is the USB Endpoint Interrupt Enable Reg-
`ister, which enables interrupts for Endpoints 0, 1, and 2. I cover this register
`in more detail below, under Interrupt Processing,
`
`Other I/O
`
`the enCoRe has built—in support for three
`In addition to the USB port,
`other [/0 interfaces. Firmware can use the general—purpose ports for any
`purpose. Some of the general~purpose bits can function as an SP1 synchro~
`nous serial interface. And the USB interface is switchable between USB and
`
`a l’S/ 2 interface.
`
`General-purpose l/O
`
`For interfacing to circuits besides the USB port, the chip has 16 versatile
`l/O pins on two 8—bit ports. Each can function as an input or output.
`Inputs can have pull~ups or not, and CMOS or TTL thresholds. Outputs
`can be CMOS with selectable driver strength or open drain. Each input can
`trigger an interrupt. A data register and two mode registers for each port
`control the configuration of each pin.
`
`192
`
`USB Complete
`
`

`

`inside a USB Controller: the Cypress enCoRe
`
`VCC
`
`m9
`
`SPI BYPASS
`(PO,5‘PO.7 ONLY)
`
`
`DATA OUT
`REGISTER
`
`CONTROL
`
`14K
`
`
`
`
`
`“DO ‘—‘_U
`
`
`
`
`
`
`
`
`
`INTERNAL
`DATA BUS
`
` PORT WRITE
`
`
`CMOS/TTL
`THRESHOLD
`
`SELECT
`
`
`
`INTERRUPT POLARITY BIT
`
`PORT R
`
`
`
`
`
`
`INEEETEPT —~;>TO INTERRUPT CONTROLLER
`
`INTERRUPT ENABLE BIT
`
`IS ON FOR RESISTIVE OUTPUT (LOW SOURCE CURRENT).
`01
`03 IS ON FOR STRONG SOURCE CURRENT.
`O2
`IS ON FOR LOW, MEDIUM, OR HIGH SINK CURRENT.
`
`Figure 8—5: Two GPlO register bits for each pin determine whether the pin is an
`input or output and the amount of source and sink current an output is capable
`of.
`
`The Circuits Inside
`
`Figure 86 shows the circuits inside each port pin. Table 8—5 shows the
`effects of combinations of settings.
`
`To configure a bit as an input, the firmware writes O to the matching bits in
`the Mode 0 and Mode 1 registers. For TTL input thresholds, write 1 to the
`Data bit; for CMOS, write 0. A TTL low input must be 0.8V or less, and a
`TTL high input must be 2.0V or greater. CMOS input thresholds are cen-
`tered at around half the power—supply voltage. For low—tovhigh transitions,
`the thresholds are 40% and 60% of the supply voltage. For high—to—low
`transitions, the thresholds are slightly lower. This adds hysteresis to keep
`inputs from oscillating on noisy or slowly changing inputs.
`
`USB Complete
`
`193
`
`

`

`Chapter 8
`
`Table 8~5z Two Mode bits and a Data bit determine the configuration and state of
`each general-purpose I/O bit.
`
`Register
`Data
`
`Output Drive Strength
`
`input Threshold
`
`Output
`Mode 0 Mode1 State
` uen’ied
`high impdncae i H CMOS
`
`0
`O
`undefined
`high impedance
`TTL
`medium (8 mA) sink current CMOS
`
` 0
`
`CMOS
`strong (2111A) source
`1
`current
`
`1 l
`
`CMOS
`low (2 mA) sink current
`
`(open drain on)
`resistive (14K pull—up,
`low source current)
`
`CMOS
`
`
`
`
`
`
`
`
`l
`
`(l
`
`0
`
`0
`
`l
`
` 1
`
` 1
`
`l
`
`0
`
`high (50 mA) sink current
`
`CMOS
`
`1
`
`l
`
`1
`
`strong (2 mA) source current CMOS
`
`The other modes control the strength of the source and sink currents for
`outputs. Any output pin can sink up to 50 milliamperesj but only one pin
`can do so at a time. The combined sink current For all pins shouldnit exceed
`70 milliamperes. For source current, the combined maximum is 30 milliarn~
`peres. Use current—limiting resistors to limit the output current.
`
`Interrupts
`
`A transition on a GPIQ pin can cause an interrupt. Additional register hits
`configure the pins interrupt capability. 'Writing 1 to a pin’s bit in the GPIO
`Interrupt Enable Register enables a transition on the pin to trigger a GNU
`interrupt. The GPIO bit in the Global Interrupt Enable Register must be
`set to l as well. A pin’s hit in the GPIO Interrupt Polarity Register deter»
`mines whether a rising (l) or falling (0) edge triggers the interrupt.
`
`All of the GPlO pins share an interrupt, so the firmware may need to deter—
`mine which pin caused the interrupt. It can do so by reading the port. The
`interrupt latency, or time it takes for the CPU to enter the interruptwservice
`routine, is under 3 microseconds, so an interrupt signal should be greater
`than 3 microseconds wide if the interruptecrvicc routine needs to detect
`which pin caused the interrupt.
`
`194
`
`USB Complete
`
`

`

`Inside a USB Controller: the Cypress enCoRe
`
`SPI Port
`
`The enCoRe includes hardware support for an SP1 (Serial Peripheral Inter—
`face) port. SP1 is a synchronous serial interface suitable for short—range com»
`munications, often on the same circuit board, though cables of ten feet or so
`shouldn’t be a problem in most environments. Compared to USB, SP1
`doesn’t require nearly as much support in hardware or code, so it’s used by
`many simple and inexpensive chips.
`
`Chips with SP1 interfaces include serial EEPROMS and analog—to-digital
`converters. The enCoRe’s Development System includes a couple of SP1
`peripherals that can connect to the chip. Motorola introduced SP1, so the
`681-101 and other Motorola microcontrollers have SP1 interfaces. A
`
`peripheral that needs more processing power than the enCoRe could use an
`enCoRe to manage USB communications and use the SP1 interface to pass
`information between the enCoRe and another microcontroller.
`
`An SP1 bus has one master and one or more slaves. As with USB’S host, the
`
`master initiates all SP1 traffic. The enCoRe’s SP] can Function as a master or
`
`slave. The number of wires varies with the application. In addition to a
`common ground, an SP1 interface has MlSO (master in, slave out), MOSI
`(master out, slave in), and SCK (serial clock) lines. When there is more than
`
`one slave connected, each must also have an *SS (slave select) line. if there is
`
`just one slave, *SS can often be tied low at the slave to select it permanently.
`
`On a master, MOSI, SCK, and any *SS pins are outputs and MISO is an
`input. On a slave, MISO is an output and MOSl, SCK, and *SS are inputs.
`
`On the enCoRe, the SP1 interface uses GPIO pins. Four pins have assigned
`functions: M081 is P05, M1SO is P06, and SCK is P07. On a slave, *SS is
`
`P04. On a master, the *SS outputs can be any spare GPIO pins.
`
`The hardware handles the clocking and sending and receiving of the SP1
`data bits. A communication consists of the master writing one or more bytes
`to a slave, followed by an optional reply. For example, to write a byte to
`serial EEPROM,
`the master sends a write instruction, Followed by an
`address and data. The slave sends nothing. To read a byte from EEPROM,
`
`USB Complete
`
`195
`
`

`

`Chapter 8
`
`the master sends a read instruction followed by an address. and the slave
`
`sends the data in reply.
`
`Writing to the SP1 Data Register fills a transmit buffer, which causes the
`data to load into a shift register for transmitting. Received SP] data is loaded
`into a receive buffer, where the firmware can retrieve it by reading the SPI
`
`Data Register.
`
`The enCoRe’s interface is flexible enough to communicate with just about
`any SP1 chip. An SPI Control Register enables the firmware to select mas»
`ter or slave mode, a clock frequency from 62.5 Kbits/sec. to 2 Mbits/sec.,
`and a clock polarity and phase. The clock polarity and phase select
`the
`clock’s idle state (0 or 1) and whether data is written and read on rising or
`falling clock edges. Some SP1 chips support only master or slave or a single
`clock phase and polarity.
`
`Two additional bits in the SP1 Control Register indicate when the transmit
`buffer is full and when an 8~bit transfer is complete. Completing a transfer
`also triggers an SP1 interrupt so the firmware can get ready for another
`transfer.
`
`The PSI2 Interface
`
`Although this book is about USB, I shouldn’t entirely neglect the enCoRe’s
`PS/Z option. The term PS/Z can refer to the mouse, keyboard, or paralw
`lei—port interface IBM included years ago in its model PS/2 computer. in
`this case, were talking about the mouse interface, which became a favored
`alternative to the serial (RS~232) and bus interfaces that were the options
`
`until USB came along.
`
`A PS/ 2 mouse uses a synchronous serial interface that has a single data line
`and a clock line. The interface also has +5V and ground lines. The device
`provides the clock for communications in both directions. The device sends
`mouse data synchronized to the clock pulses. The data format uses ll bits: :1
`Start bit of 0, eight data bits sent least significant bit first, an odd parity bit,
`and a Stop bit of 1. The host reads the data on the clocks falling edge. As
`with a USB mouse, the data contains information about button presses and
`the amount and direction of mouse movement.
`
`196
`
`USB Complete
`
`

`

`Inside a USB Controller: the Cypress enCoRe
`
`A long low on the data line tells the device that the hosr wants to send. a
`command and generates a P5/2 interrupt in the device.
`
`Having an interface that supports both USB and PS/2 makes it easy to
`design a pointing device that can use either. The device will need firmware
`to support both. For PS/Z, the firmware is responsible for writing each clock
`pulse and data bit by setting Control bits in the USP) Status and Control
`Register. Of course, a design can also use only USB, only PS/2, or even nei—
`ther.
`
`Other Chip Capabilities
`
`The enCoRe has many other capabilities worthy of mention. Timer func—
`tions enable performing periodic tasks and measuring intervals. Many event
`types can trigger interrupts. And several registers enable monitoring and
`controlling the CPU and managing power.
`
`Timer Functions
`
`The chips have hardware support for a variety of timing functions, includ—
`ing generating interrupts for periodic tasks and measuring intervals.
`
`Performing Periodic Tasks
`
`For tasks to be done periodically, there are three options: the l—millisecond,
`128—microsecond, and Wake—up timer interrupts. The Wake—up interrupt
`provides less precise, but longer, timing intervals than the other two timers.
`If the chip is in the Suspend state, this interrupt will wake it. But firmware
`can also use this interrupt to perform periodic tasks when the chip isn’t sus—
`pended.
`
`The timing interval of the Wake—up interrupt is the chips tWAKE period
`multiplied by the value indicated by three Wake~up Timer Adjust bits in the
`Clock Configuration Register. The available values are the eight powers of
`2 from 1 through 128. The tWAKE value varies with the supply voltage and
`temperature, and can range from 1
`to 5 milliseconds. So for example, if
`tWAKE is 128, the interval may be anywhere from 128 to 640 milliseconds.
`
`USB Complete
`
`197
`
`

`

`Chapter 8
`
`To select an interval more precisely, the firmware can enable the Wake‘up
`timer, use the chips Free—running timer to measure the interval, and select
`the Wake—up Timer Adjust value that most closely matches the desired inter—
`val.
`
`With any of these timers, to time a longer interval, the firmware can main«
`tain a counter in the interrupt—service routine. The routine increments the
`counter on each interrupt until the desired number of intervals has elapsed.
`
`Measuring Intervals
`
`The enCoRe has a free—running timer that provides a way to measure inter—
`vals and, timer capture registers that enable measuring the time between
`events at 1/0 pins.
`
`The 12—bit freevrunning timer increments once per microsecond, The timer
`rolls over on a count of FFFh, enabling firmware to measure periods up to
`4.096 milliseconds (or longer by cascading counts). The count is stored in
`two registers. The firmware can read just one register at a time, yet it will
`want to know the states of all 12 hits at the same time. To make this possi~
`ble, reading the Timer LSB (least significant byte) Register also leads the
`'timer’s upper four bits into a temporary register. Reading the Timer MSB
`(most significant byte) Register reads the temporary register. 80 sequential
`reads of these two registers gives the count at the time ofithe first read.
`
`The chip can also measure intervals betWeen events at the GPIO pins Port
`0.0 (Capture A) and Port 0.1 (Capture B). Six registers configure the timers
`and hold the results, which can correspond to the times of rising and falling
`edges at each pin.
`
`The Capture Timers Configuration Register has three functions. Four bits
`enable interrupts on the rising and falling edges of Capture A and B. One
`bit selects whether to save the time of the first edge or the most recent edge.
`Three bits select a prescale value that determines which 8 of. the Free—run»
`ning timer’s 12 bits are saved on an interrupt. Using lower bits gives better
`precision but shorter range, while higher bits give longer range but less pre—
`crsron.
`
`198
`
`USB Complete
`
`

`

`inside a USB Controller: the Cypress enCoRe
`
`The Capture Timers Status Register indicates whether a rising or falling
`edge has occurred on Capture A or B. The four Capture Timer Data Regis—
`ters hold the timer counts for rising and falling edges at the two port pins.
`The difference between the counts stored at two events equals the time in
`microseconds between them.
`
`interrupt Processing
`
`The firmware uses two registers to control which interrupts are enabled, plus
`two additional registers to enable individual GPIO interrupts. The USB
`Endpoint Interrupt Enable Register has three bits that enable interrupts
`for Endpoints O, 1, and 2. The Global Interrupt Enable Register enables
`the other interrupt sources: Wake up, General-purpose l/O, Capture Timer
`A, Capture Timer B, SP],
`1 .024—millisecond timer, 128—microsecond timer,
`and USB Reset or PS/Z Activity. Writing 1 to an interrupt’s bit enables the
`interrupt, while writing 0 masks, or disables, the interrupt.
`
`Interrupt Service Routines
`
`When an interrupt occurs, the chips hardware disables all interrupts, clears
`the Global Interrupt Enable bit and jumps to the interrupts assigned inter—
`rupt-vector location in program memory. This location typically contains a
`jump to an interrupt-service routine. The interruptrservice routine is
`responsible for carrying out whatever needs to be done in response to the
`interrupt’s event and for ensuring that all registers are in the expected states
`on exiting the routine.
`
`On entering an interruptvservice routine, the hardware automatically stores
`the Program Counter’s value and the states of the Carry and Zero flags. On
`exiting the routine,
`t