MICO(\): A Knowledge Based SinglE!
`Board Computer Designe,r
`
`William p, Birmingham
`Daniel P. Siewiorek
`
`Department of Electrical
`and Computer Engineering
`Carnegie-Mellon
`University
`Pennsylvania 15213
`Pittsburgh,
`
`Abstract
`For some time there has been interest in automatically
`produced much of the pioneering work in transforming
`a high
`implementing designs described in a high level representation.
`level design description,
`at the Instruction
`Set Processor (ISP)
`This paper presents a workbench that allows a designer to
`level, through to physical realization
`in either integrated
`circuits
`or
`describe a single board computer at the hardware requirements
`boards [2]. While the M ICON project is not directly related to
`level and have a design produced automatically.
`CMU.DA, a co-operative
`relationship
`has been developed. An
`The designs
`produced by the system, M ICON, compare favorably to
`example of higher level design support is the SARA [3] system,
`commercial designs. In comparison to manual techniques,
`which is concerned with architectural aspects
`of system design.
`the
`design time has been drastically
`reduced; a series of three
`For the synthesis of hardware from high level descriptions,
`the
`commercial desi�Jnswas reproduced
`in a few hours. MICON lIses
`International Business
`Machines (IBM) 3081 project has
`knowledge based engineering approaches
`in its implementation
`generated some interesting
`tools and methodologies [10].
`and is written in the OPS 5 production system language.
`Examples of various knowledge engineering systems
`can be
`found in [5]. In addition,
`examples of work done at C-MU can be
`found in [7] [6]. A somewhat related project [11] selects from a
`1. !nt rodllction
`library of commercially
`available
`single board computers one that
`To help improve the efficiency
`of the designer, thete has
`most closely matches the requirements described by a user.
`been an effort to provide design methodoiogies
`that help to
`Projects underway at Rutgers [8] and MIT [1] are also concerned
`abstract away tedious details and to perform as m�ny ot the
`with the application
`of expert systems to design problems.
`mundane aspects of design as possible, The project dl�scrib�)d
`in
`However, these projects are primarily
`concerned with changing or
`this paper, MICON (Micro,
`processor gQ1.lfigurer),
`provides the
`diagnosing existing systems, not synthesizing
`new designs.
`designer with a wori(bench that takes a very high ievel design
`description,
`at the hardware requirements
`level, and produces a
`nefwork interconnection
`list.
`3. Task Domain
`There is little software support and few algorithms to help a
`The task domain for this project is the construction
`of single
`designer who wor\c;s at the hardware requirements level.
`board computers, Single board computers use micro·processors
`Apparently,
`traditional
`design automation approaches are not well
`as the primary computational
`engine. They also contain some
`suited for design at this level. Also, since designs are specified
`at a
`local memory, input/output
`(1/0) devices, and often an interface
`high level, the number of candidate designs can become very
`to a common bussing scheme. Since these computers must, by
`large, To overcome these problems, MICON has applied a
`definition,
`fit on a single board a premium is placed on board real
`know/edge based engineering approach to design.
`estate.
`Before developing MICON, a model of the task domain was
`There are a large number of different
`micro processors on
`derived. Based on this model, a knowledge based production
`the market. While the machines are similar in many respects, it
`system was written that duplicates
`many of the key aspects of the
`would be difficult
`to develop the expertise to design with each of
`model. Section 2 briefly presents some related work. Section
`them in a reasonable time period, For this reason, the "micro·
`3 discusses the model, while Section 4 presents its
`processor space" was pared down to a manageable size. Several
`implementation. An introduction
`to the production system
`criteria
`were used in evaluating
`the candidate micro· processors:
`paradigm and a rationale explaining why the system was
`implemented as a production system is given in Section 5. Section
`Availability
`of a local expert on the processor.
`For reasons discussed later (see Section 5), it
`6 compares MICON generated designs against commercial
`designs. Section 7 offers some concluding remarks.
`is critical
`that an expert designer familiar with
`the processor be available.
`Number of support chips in the processor family.
`The processor mllst have a family of
`established
`peripheral
`chips. The
`growth of
`micro-processor
`systems is closely linked
`to
`the availability
`and functionality
`of peripherals
`compatible with it. While it is true that most
`processors may lise peripherals
`outside of its
`family, it takes several glue chips to convert
`between different
`protocols;
`for a single board
`
`2. Related Work
`Much of the work done in this project is related to the parent
`project DErvI ETER which is concerned with aspects of design
`above the register transfer
`level [9]. The CMU-OA pr<?ject has
`.
`This work was funded ;n part by the SRC and by Siemens A,G. The views
`presented here are solely those of the au thor ana do not necl'-ssarily
`represent
`those of the funding agencies.
`
`© 1984 IEEE
`0738·100Xl84/0000/0565$1.00
`
`Paper 34.2
`565
`
`21st Design Automation Conference
`
`Page 1 of 7
`
`FORD 1106
`
`

`
`and their inter·rehtionships
`are
`subtasks
`The specific
`computer this should be avoided since the
`illustrated
`in Figure 1. The order shown in the diagram is very
`board space.
`extra chips consume limited
`in one step is built upon in later
`determined
`information
`important;
`of the processor.
`Usefulness
`used in memory
`the type of controller
`steps. For instance,
`used to determine
`the
`There are two features
`design
`device subsystem
`Oil tlie peripheral
`has an effect
`selection
`First is the
`of the processor.
`usefulness
`since both may share some parts.
`for a processor.
`existing
`amount of software
`4.1. Processor Design
`generally
`have
`families
`processor
`Established
`of M ICON is to allow novice designers
`to
`A requirement
`than new processor
`available
`more software
`It is assumed that the
`build single board computers.
`successfully
`would rank·
`processors
`so established
`families,
`but has a feel for
`processors,
`about specific
`novice knows nothing
`higher in this measure. Second, in order to
`Through a
`processors.
`used in describing
`some of the attributes
`of designs produced by
`the quality
`evaluate
`element are
`of the processing
`the requirements
`set of queries,
`is needed. To gain
`MICON, a set of metrics
`below does not
`The set of queries presented
`determined.
`for these metrics,
`a
`points of comparison
`criteria,
`other imaginable
`a closed set, there are several
`represent
`number of designs using the processors
`is
`may be added at a
`queries
`such as data path width. Additional
`of designs
`and variety
`The availability
`required.
`the queries
`to
`of this project,
`for the purposes
`later date; however,
`very important.
`is considered
`available
`If the user would like to use a
`adequate.
`follow are considered
`is based upon
`of single board computers
`The construction
`the automatic
`to circumvent
`it is possible
`processor,
`particular
`are well Imown
`The subsystems
`of subsystems.
`the integration
`by naming the processor.
`process
`selection
`units:
`to functional
`and cormspond
`are:
`The queries
`• processor
`
`• memory array and controller
`
`and controllers.
`devices
`• peripheral
`
`name.
`• Processor
`
`time. This is intended
`• Average instruction execution
`power.
`to be a rough measure of processing
`
`.. Cycle time.
`
`qualification,
`each
`By a predetermined
`• Application.
`stored in the
`applications
`has its potential
`processor
`data base as an attribute.
`
`cost and power
`• Cost and Power. The suggested
`of the processor.
`consumption
`
`chips to realize
`have developed
`manufacturers
`circuit
`Integrated
`single board
`Thus, the task of designing
`these functions.
`units
`needed functional
`as selecting
`can be pictured
`computers
`this appears simple it should
`them. Although
`and interconnecting
`as trivial.
`not be construed
`subtasks
`MICON is based on a set of tasks and associated
`units.
`The
`of the function
`to the construction
`which correspond
`two major tasks involve
`design (of a single board computer)
`and
`of a set of
`Each task is comprised
`analysis (of the design).
`subtas/<s,
`of the system
`later. The philosophy
`to be described
`In fact, the designer
`can
`must be answered.
`Not all the queries
`for each subsystem
`in
`requirements
`the user to specify
`requires
`answer none of them. If this is done, MICON assumes no
`turn and then have MICON implement that
`subsystem.
`The
`virtually
`at
`and selects a processor
`preferences
`processor
`gained through
`is based on knowledge
`design of each subsystem
`random.
`that preceded
`it.
`the design of the subsystem
`Weights are
`a weight is required.
`Along with each criterion,
`which
`the processor
`for choosing
`function
`used in an evaluation
`4. The Design Subtasks
`function
`The evaluation
`matches the requirements.
`most closely
`steps towards
`incremental
`may be considered
`The subtasks
`a processor
`for a
`since the method for choosing
`is essential
`of a task. For the design task, each of the subtasks
`the completion
`that a processor
`It is doubtful
`task is not well specified.
`particular
`For the
`at some time during the design process.
`must be activated
`matches the needs of the user. The
`will be found that exactly
`may be
`that only some of the subtasks
`task, it is possible
`analysis
`is qiven in Figure 2.
`evaluation function
`used.
`4.2. Memory Design
`of each subtask
`in
`required
`basic functions
`There are several
`the design task:
`The next step in the design task is memory specification
`and
`memory are RAM (static
`The three types of recognized
`selection.
`Specification:
`to enter requirements
`The user is requested
`and ROM (blown fuse). The user must specify
`the
`and dynamic)
`if the
`For example,
`subsystem.
`for a particular
`If the amount
`memory required.
`type and amount of addressable
`the memory array, it is
`user is designing
`range of the
`the addressing
`of memory specified exceeds
`the type of memory, the
`to specify
`necessary
`d
`that the amount of specifie
`user is notified
`processor, the
`arid so forth.
`amount required,
`memory should be changed. The power and area limit for the
`Selection:
`has been ascertained,
`memory array may also be specified.
`After the requirement
`parts are sought. If no part
`the required
`of the memory array is the
`The first step in the construction
`the closest
`matches the requirement,
`exactly
`For dynamic FlAM 16K, 64K. and
`of a memory chip.
`selection
`If there is no
`will be substituted.
`alternative
`RAM 1 Kx4, 4Kx1, and 16Kx1
`For static
`256K chips are available.
`the case for
`(frequently
`alternative
`For ROM 2Kx4, 4Kx4, and 8Kx8 chips are
`chips are available.
`the user is notified
`and
`dCNices)
`input/output
`ThH most dense chip that uses the least amount of area
`available.
`must change the requirement.
`was 20K of
`if the requirement
`will always be chosen. For example,
`dynamic RAM, a single row of 64K chips would be used, ralher
`Instantiation:
`they are instantiated
`Once parts are selected
`the single most
`than two rows of 16K. Real estate is considered
`into the design. This is done by creating
`even for an increase
`and is always �onserved,
`resource
`valuable
`copies of the devices from the data
`"logical"
`in the cost of some other factors.
`base and interconnecting
`them.
`
`Paper 34.2
`566
`
`Page 2 of 7
`
`FORD 1106
`
`

`
`Figu r� 1: Task and Subtask hierarchy in MICON
`
`
`
`For those devices that handle a large amount of data quickly, it is
`
`
`possible
`
`to connect a direct memory access (DMA) controller to
`them.
`After the appropriate device has been found in the data base,
`
`
`
`the user is requested to give the device an address. If a device
`
`address is not given, MICON will automatically select the address
`
`
`and reserve several words in memory for the device's control
`
`
`register locations. The amount of memory needed for control
`
`
`registers is stored as an attribute of the device in ttie data base. It
`
`
`
`is recommended that peripheral device addresses be placed at the
`
`
`top of RAM when no ROM is present. The peripheral devices
`
`should be placed just below ROM when it is present. M ICON will
`
`always select addresses in this fashion. An automatically
`
`
`
`generated address is displayed to the user.
`After all devices have been assigned an address, they are
`
`
`
`
`
`
`then assigned an interrupt priority (all the peripheral chips used
`
`
`
`have interrupt capability). If the user does not want to specify a
`
`
`priority for each device, then all are assumed to be equal. The
`
`
`
`peripherals are instantiated into the design by interconnecting the
`
`
`
`
`interrupt lines followed by the data, address, and control lines.
`
`
`
`the method of connecting Each processor has its own special
`
`
`interrupt lines. To handle each case, MICON invokes an interrupt
`
`
`model for each processor. The models are represented in the form
`
`
`
`of rules which describe in what manner the processor expects its
`
`
`
`
`interrupt structure to be built. As in previous subtasks, all the
`
`
`
`
`necessary glue chips are included without designer intervention.
`After the type of memory chip has been selected, M ICON
`
`
`
`
`This includes wait·state generators for slow chips, interrupt
`
`determines the array size. The chips are then logically
`
`prioritizers, and baud rate generators.
`
`
`interconnected. For example, the chip select lines are connected
`
`
`to the address decoder. The inclusion of any support chips,
`
`
`Once all the subtasks outlined above have been completed,
`a
`
`
`
`design exists that represents the system's best attempt to match
`
`
`usually in the form of memory controllers, occurs automatically
`
`
`
`the specifications. A list may be obtained that documents the
`
`
`without intervention of the designer. To accomplish this,
`
`templates are used (see Section 4.5).
`
`
`
`logical interconnections and a memory map of the addm�;ses for
`
`
`the memory and peripheral devices.
`The actual memory chip part number and manufacturer to be
`
`
`used in the design is selected from the data base after the
`f(e)=(user-specified-value/stored-value)
`
`
`
`controller has been determined. This order is mandatory because
`.. wei�ll1t
`
`
`the memory chip speed will be directly 'related to the speed of the
`Where:
`
`
`
`
`controller. For the initial design, the memory chips selected are
`user-specified value = value that the
`
`fast enough to ensure zero wait states for the processor.
`user supplies to a query.
`
`
`For ROM there are some special requirements. Since many
`stored-value = the processor's
`
`
`
`
`designers use a particular ROM chip, it is possible to specify a
`characteristic for a particular
`query. For example, the zao would
`
`specific part number. If the system does not know the part, the
`have 1.0 watt as its value for
`
`user is queried about the part to enhance the system data base.
`power consumption.
`
`
`For a designer who has no preference, the system will determine
`weight = the user specified importance of
`
`the correct chip in the same manner as used for RAM selection.
`that particular
`
`
`Additionally, the user must specify where to place the ROM in the
`user specified-value.
`
`
`
`
`address space. For the processors currently described in the data
`
`Figu re 2: Evaluation Function
`
`base it is recomnwnded that the ROM be placed at the top of
`4.4. Analysis Task
`
`
`memory: this is where the processors look for boot programs
`Analysis provides the user with the capability to verify part of
`
`
`
`
`
`
`during power· up and reset. It is possible to overlay ROM on RAM
`
`
`the design, or modify a portion of the design to bring it into closer
`so that no RAM space is lost. If the user does not have any idea
`
`
`
`agreement with the requirements. Modifications take the form of
`about where the ROM should be placed M ICON will locate it at
`
`
`part replacement. Chips which more closely match the
`
`the top of the address space.
`
`requirements of the user (e.g. with respect to cost and power
`4.3. Peripheral Device Design
`
`
`dissipation) may be substituted. If there is a need for a change in
`The speCification of peripheral devices is slightly more
`
`
`
`
`
`the structure of the design the current design should be saved,
`
`
`
`complicated than for the previously mentioned subsystems.
`
`and M ICON be invoked again with different design parameters.
`
`
`
`Peripherals are specified after memory so certain parts can be
`
`
`
`
`The two subtasks forming the analysis task are described below.
`
`
`shared between subsystems, Typically these parts are chip select
`
`
`logic and bus drivers. The user is required to give the type of
`
`
`
`The verification subtask enables the user to critically evaluate
`
`
`device needed. The choices consist of:
`
`
`what MICON has produced along three dimensions. These are:
`
`• timers
`
`cost:
`
`The cost of each component is given as well
`
`as the total cost of the system. The costs are
`
`
`based on estimates and act as a guideline in
`
`
`evaluating the relative costs of, different
`designs.
`
`Paper 34.2
`567
`
`
`
`• parallel input/output devices (PIO)
`
`
`
`
`
`
`
`
`
`• serial input/output devices (SIO).
`
`
`
`Page 3 of 7
`
`FORD 1106
`
`

`
`power:
`
`timing:
`
`• Memory path:
`processor
`driver/latch
`address
`-memory
`control
`decode/memory
`chip access -data driver.
`
`-driver
`path: processor
`• Peripheral
`-address decode -peripheral
`chip
`access -data driver.
`
`then the design will be
`part is slower,
`replacement
`of each component
`The power consumption
`inconsistent.
`and thetotal system power are calculated.
`that system
`is true, the user is notified
`If the precondition
`timing paths are known to the
`critical
`Several
`with the new part. To determine
`if
`may be degraded
`performance
`can verify the system
`system. The designer
`the access time of the new part is
`a design is inconsistent,
`critical
`has chosen parts that meet certain
`of the processor"
`The number
`with the requirements
`compared
`timi!!g paths by examing each path. The paths
`the delay of the
`by comparing
`of wait states needed is determined
`are :
`data ready time and bus cytle
`new part with the processor's
`the design is considered
`length. If no wait states are required,
`then the wait state
`If wait states are required,
`consistent.
`(if it had not been previously)
`and all
`is instantiated
`generator
`are made. The number of wait states
`connections
`necessary
`to the user .
`needed is reported
`above deals with
`to the method outlined
`The one exception
`is the
`used in dynarnic RAM designs
`dynamic RAM. The controller
`Intel 8207 which only allows chips with either 100 ns or 150 ns
`the range of change for dynamic RAM is
`access times. Therefore,
`for a read operation.
`The
`above are typical
`The paths listed
`limited.
`devices and memory stems
`made between peripheral
`distinction
`Memory
`devices.
`needed for peripheral
`control
`from the simpler
`to some form of
`in addition
`needs address decode logic,
`typically
`4.5. Data Base
`timing control.
`It holds
`part of the workbench.
`The data base is an interyal
`paths thClt e)(ist for each of
`parallel
`Since there are several
`and chip
`two key parts of the system: design templates
`for each and
`is perfor med
`a timing calculation
`the subsystems,
`below.
`base is discussed
`Each part of the data
`information.
`paths
`to the user. In the memory path above, the parallel
`reported
`about the chips used in the design are
`All the information
`the iAPX-186 as an example.
`Consider
`by slashes.
`are delineated
`of the production
`held in working memory: this is a vestige
`This chip has its data and address bus time multiplexed.
`The
`100 chips
`system (see Section 5). There are approximately
`After
`since it only lasts for one bus cycle.
`must be latched,
`address
`to be added. Not all
`base, with more expected
`in the data
`currently
`of the bus cycle, data is applied for the
`the address portion
`those chips
`For efficiency
`these chips are used in a single design.
`are available
`cycle. The control signals
`of the instruction
`duration
`can be
`Activation
`to the design are activated.
`essential
`cycle and they only need pass
`the entire instruction
`throughout
`in two ways. The first way keeps the attention
`of the
`accomplished
`a driver.
`through
`with the selected
`system focused on those chips associated
`to note that the timing subtask uses nominal
`It is important
`The second way forms a list of part instantiations
`used
`processor.
`and does not take into account delays in
`times for calculations
`design. MICON makes use of both ways; attention
`in the current
`Delays
`slew rates are also assumed.
`Instantaneous
`board lines.
`for glue chips.
`and list generation
`selection
`for template
`focusing
`since no routing
`calculated
`can not be accurately
`due to routing
`and are represented
`Three major chip types were identified
`occurs at a later time).
`to MICON (routing
`is available
`information
`Working
`type of working memory element.
`with their own specific
`task is replacement.
`The
`in the analysis
`The second subtask
`Each field
`of as Pascal records.
`can be thought
`memory elements
`allows the user to change the parts selected
`subtask
`replacement
`of the chip.
`an attribute
`in the working memory element represents
`but not all, parts ill the
`to change certain,
`by M ICON. It is possible
`The chip types and their attributes are:
`family,
`It would not make sense to change the processor
`design.
`change the bus
`since this would significantly
`for instance,
`of the design
`It is assumed that memory is the portion
`structure.
`to need redesign.
`most likely
`to change apart:
`is required
`information
`The following
`
`• memory chip element-name, manufacturer,
`cost,
`access-time, cycle­
`power dynamic,
`power-static,
`number of
`RAM, ROM, etc.),
`time, type (dynamic
`number of rows, number of pins, width,
`columns,
`flags.
`and several
`area, power supply required,
`
`part
`• the number of the current
`
`change (e.g. cost)
`of the part to
`• what attribute
`
`(e.g. less power).
`• the type of change requested
`
`• 110 chip element-name, function parallel
`address
`device, etc.), manufacturer,
`input/output
`with, number of
`compatible
`space needed, processors
`cost, power, access time.
`generated,
`interrupts
`chip elementclock cycle time, average
`• processor
`power, memory access
`time, name, cost,
`execution
`u"nit (byte, word), time for zero wait state data
`flags
`several
`available,
`
`the type of part is determined
`and an
`Based on this information,
`attempt is made to find a part that will match the new
`a series of candidates
`and
`MICON will "activate"
`requirements.
`each to the user until one is found or there are no more
`describe
`candidates.
`"activated"
`stored in
`I'vllCON has most of its design knowledge
`time by providing large
`save computational
`Templates
`templates.
`by the user for change, it
`Once a part has been accepted
`so 11 ICON does not have to re create
`the
`sections,
`pre-designed
`whether the timing of this part is consistent
`must be determined
`A precondition
`generic
`may be considered
`The templates
`basics of each design.
`is used to determine
`if
`with the rest of the design.
`for each processor.
`which are modified
`designs
`The precondition
`is:
`be violated.
`could possibly
`the consistency
`The major templates
`are used to describe
`the relationship
`than the replaced
`If a new part is as fast, or faster,
`between the processor,
`the board level bus, and the generation
`of
`that timing will be consistent.
`If the
`pmt it is concluded
`
`,.
`Each processor's descliption
`when it assumes datil
`telling
`has an attribute
`that both devices are active in
`Please note that the symbol "/" indicates
`will be ready in a zero wait '>tate machine cycle.
`parallel.
`
`Paper 34.2
`568
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`Page 4 of 7
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`FORD 1106
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`'i
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`a few extraneous signals needed by various parts, e.g. data
`
`
`have catastrophic effects n another part of the program when
`
`
`
`
`
`there is no apparent connection. One of the simplest and most
`
`
`�ransmit signal for bus transceivers. The iAPX 186one of the
`
`
`
`
`effective ways to organize the productions is to partition them
`
`
`
`orocessors which M ICON uses· template is tailored to construct
`MICON.
`
`
`
`
`according to the different tasl<s and subtasks constituting
`
`
`templates for the other processors used by I'vIICON. Due to the
`
`
`In MICON's implementation task and subtasks correspond to
`
`
`
`iAPX 186 bus structure (multiplexed data and address) this
`
`
`contexts. Each production is specified to run only in a certain
`
`
`
`processor requires a superset of parts compared with those
`
`
`
`context, with the exception of a few special productions.
`
`
`needed for the other two processors, which have separate data
`
`
`and address busses. If a processor other than the iAPX 186 is
`
`
`
`Switching between contexts is controlled by the user.
`
`being used in a design, M ICON knows how to modify a template
`
`
`
`Whenever the user decides to build a.specific subsystem, or verify
`
`for proper customization. An important point to keep in mind: the
`
`
`
`
`a portion of the design, I'vI ICON's context is implicitly changed. In
`
`
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`templates represent a "logical" design, dealing with such entities
`
`
`
`many expert systems, much effort is devoted to deciding when to
`
`
`
`as busses or control lines. Templates do not contain actual pin
`
`switch contexts or to generating new contexts. Since MICON
`
`
`
`
`information. The mapping to chip pin information occurs during
`
`
`allows the user to switch the context, some effort was saved in the
`post processing.
`
`
`control structure implementation.
`
`
`
`Tho templates are represented as amalgamations of parts
`(p design-phase-help
`
`
`and ports. All the parts needed for a template are represented as
`{ <s> (state tuser-mode deSign-phase) }
`
`
`working memory elements. Representing the connections
`{ <t> (tokan Hype design-command-string
`tval « help? ») }
`
`
`between these paris are port descriptors. Port-descriptors are
`-- >
`
`
`
`working memory elements that detail port linkages across chips.
`(write (crlf)The following subsystems are)
`
`
`Ports may correspond to actual chip pins, although in some cases
`(write rocognized:)
`
`
`they represent a group of pins, e.g. a bus. Templates typically
`(write (crlf)memory processor 1/0)
`
`
`contain about 10 parts and have about 50 connections.
`lwrita (crlf)status-shows state of design)
`(remove <t»
`(modify <s> tuser-mode design)
`)
`
`5. Production System Implementation
`
`
`
`Expert systems are rapidly becoming an important approach
`
`
`in tackling many engineering tasks. Expert systems should
`5.3. Searc:h
`
`perform as well as human experts. Generally, expert systems are
`The job of building a single board computer can be thought
`
`
`
`
`
`build on the extracted collective knowledge of "human" experts.
`
`
`of as a search through a large space, which can be quite costly in
`
`One of the acknowledged weak pOints of expert systems is the
`both computer and human time. With the chips in I'vI ICON's
`
`
`
`
`limited domain of discourse, or knowledge; they are "experts" in
`
`
`current data base, over 1600 different combinations of
`
`one field and usually only in a small subset of that field. Many
`
`
`
`processors, memory and peripheral chips are possible. Search in
`
`
`
`
`expert systems are written as production systems: a collection of
`
`
`
`I'vIICON is directed by knowledge gained from the construction of
`
`previous subsystems. For this reason it is important that the order
`
`
`knowledge repres�nted as a large number of IF-THEN clauses.
`
`
`5.1. The Production System Paradigm
`
`
`of the subtasks be preserved, otherwise the search may become
`Knowledge is explicitly represented in production systems as
`
`
`
`
`
`
`
`unbound, or nonsensical designs may result.
`
`
`a set of rules, or productions. lhe terminology used to refer to
`Once the decision is made to build a certain subsystem, it is
`
`
`
`
`
`
`these productions is situation action pairs. The left hand side
`
`constructed in a linear fashion without backtracking across
`
`
`
`(LHS) of a production, corresponding to the IF part, defines some
`
`
`
`contexts. If the design techniques of the subsystems were not
`
`
`l;iiuation or pattern to match. The right hand side (RHS),
`
`
`
`
`well defined, it would be necessary to provide a mechanism for
`
`
`
`corresponding to the THEN part, describes some action that is to
`
`
`
`allowing design decisions to be undone. A limited form of
`
`
`take place. Working memory elements are used in evaluating the
`
`
`
`
`backtracking is permitted within a context to recover from a bad
`
`
`
`
`left hand side. In essence, productions look for specific patterns
`
`
`specification. The attention of I'vI ICON remains focused on the
`
`
`in memory and upon recognizing them, carrying out some action.
`
`
`
`
`
`particular path it is currently following, performing a depth· first
`Often the action will change working memory causing another
`search.
`
`
`production to fire. in the course of program execution, the
`The directed search paradigm works effectively for the
`
`
`
`
`paltern·match/production fire steps occur repeatedly until there
`
`
`
`
`situations tested. For the selection of a processor, an evaluation
`
`
`
`is an explicit halt or no LHS can find a matching pattern in
`
`
`function was developed and is used in an A' ·like search
`Illemory.
`
`paradigm. It should also be noted that the working memory is
`An example OPS 5 [41 production taken from I'vIICON is given
`
`
`
`
`
`organized to help in search. The working memory t;llements have
`
`in Figure 3. The first line is the name of the production. The two
`
`
`been sorted, usually slowest chip first, so that the search path is
`
`
`
`statements before the " .. >" constitute the left hand side (the
`shortened.
`
`
`
`working memory pattern to match), the statements after are the
`
`
`
`right hand side (the actions to be carried out). The English
`
`
`tnmslation for the production in Figure;3 is:
`6. Performance
`
`
`If there exists a working memory element named state whose
`
`Expert systems should perform as well as a human expert in
`
`
`attribute user mode has the value "design phase" AND there
`
`the domain of expertise. For the purpose of this paper, the
`
`is a working memory element named token whose type
`
`
`
`following criteria are presented on which to judge the
`
`
`attribute has the value "design command string" and
`
`performance of MICON.
`
`attribute val has the value "heip" or "?"
`
`
`performance Quality of design: The number of chips, relative
`
`
`THEN execute the statement.
`
`and cost are a good basis of comparison with
`5.2. Contexts
`A metllod of organizing the productions is needed, especially
`
`
`
`other systems.
`when a large number of productions
`
`
`are required. Sometimes, a
`
`Design Time: Design time is defined to be the time it tak�s to
`
`
`seemingly insignificant change in ope part of the program can
`bring a '»design trom the hardware
`
`Figure 3: Rule Example
`
`Paper 34.2
`569'
`
`Page 5 of 7
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`FORD 1106
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`

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`requirements to net list generation. For the
`
`
`designs to which this program is to be
`
`
`compared, design time is estimated as the
`
`overall run time of M ICON.
`
`PI'ocessor
`Performance
`Execution Time(s)
`
`iAPX-186
`
`Z80
`
`I
`101.2
`I
`107.5
`I
`98.6
`
`I
`103.0
`101. 1
`I
`I
`101.5
`
`comparing the run time required for M ICON to select the
`
`
`
`
`
`processor to designing a system with a processor the user had
`
`
`
`chosen. It is expected that total execution time for experts will
`
`
`
`probably be longer than for novices: experts will perform more
`
`
`
`
`parts replacement and analysis functions, a result of exploring the
`For each of the processors currently used by MICON· the
`
`
`
`design space to a greater degree.
`
`iAPX 186, Z80, and Tl 9900· several designs have been chosen
`From analysis of the production traces, selecting and
`
`
`
`
`
`that bound the design space of each processor. The variables
`
`
`
`
`
`customizing templates require the majority of the execution time.
`
`
`perturbated are cost and performance. Through general
`
`
`
`
`This includes the subtasks of parts selection and instantiation. Of
`
`
`
`
`consensus of experienced designers it was concluded that power
`
`
`these two activities, the instantiation subtask is mor