INTEL CORP (UP/PRPHLS)
`
`20E D .. 4826175 0079078 8 ..
`[f)OOI§I!:.OIMIOOO~OOW
`
`MCS®-51
`T-ttt-1~-o7
`8-BIT CONTROL-ORIENTED MICROCOMPUTERS
`8031/8051
`8031 AH/8051 AH
`8032AH/8052AH
`8751H/8751H-8
`•
`• Boolean Processor
`High Performance HMOS Process
`•
`• Bit-Addressable RAM
`Internal Timers/Event Counters
`• Programmable Full Duplex Serial
`•
`2-Level Interrupt Priority Structure
`•
`32 1/0 Lines (Four 8-Bit Ports)
`• 111 Instructions (64 Single-Cycle)
`• •
`64K Program Memory Space
`Security Feature Protects EPROM Parts • 64K Data Memory Space
`
`Against Software Piracy
`
`Channel
`
`The MCS®-51 products are optimized for control applications. Byte-processing and numerical operations on
`small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
`instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc(cid:173)
`tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
`manipulation and testing in control and logic systems that require Boolean processing.
`
`The 8051 is the original member of the MCS-51 family. The 8051AH is identical to the 8051, but it is fabricated
`with HMOS II technology.
`
`The 8751 H is an EPROM version of the 8051AH; that is, the on-chip Program Memory can be electrically
`programmed, and can be erased by exposure to ultraviolet light. It is fully compatible with its predecessor, the
`8751-8, but incorporates two new features: a Program Memory Security bit that can be used to protect the
`EPROM against unauthorized read-out, and a programmable baud rate modification bit (SMOD). The 8751 H-8
`is identical to the 8751H but only operates up to 8 MHz.
`
`The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is
`fabricated with HMOS II technology. The 8052AH enhancements are listed in the table below. Also refer to this
`table for the ROM, ROMiess, and EPROM versions of each product.
`
`Device
`
`8052AH
`8051AH
`8051
`8032AH
`8031AH
`8031
`8751H
`8751H-8
`
`Internal Memory
`
`Program
`
`8Kx8 ROM
`4Kx8 ROM
`4Kx8 ROM
`none
`none
`none
`4Kx8EPROM
`4Kx8EPROM
`
`Data
`
`256x8 RAM
`128x8 RAM
`128x8RAM
`256x8RAM
`128x8 RAM
`128x8 RAM
`128x8RAM
`128x8 RAM
`
`Timers/
`Event Counters
`
`Interrupts
`
`3 X 16-Bit
`2x 16-Bit
`2 X 16-Bit
`3 X 16-Bit
`2 X 16-Bit
`2 X 16-Bit
`2 X 16-Bit
`2x 16-Bit
`
`6
`5
`5
`6
`5
`5
`5
`5
`
`7-44
`
`October 1988
`Order Number: 270048.004
`
`t
`
`VIZIO, Inc. Exhibit 1028
`1 of 14
`
`

`
`INTEL CORP (UP/PRPHLS)
`
`inter
`
`20E D II 4826175 0079079 T II
`IPOO~I!..OIMIOOO~OOW
`
`T-49-19-07
`
`Figure 1. MCS®-51 Block Diagram
`
`PACKAGES
`Part
`B051AH/
`B031AH
`
`8052AH/
`8032AH
`
`8751H/
`8751H-B
`
`Prefix
`p
`D
`N
`p
`D
`N
`D
`R
`
`Package Type
`40-Pin Plastic DIP
`40-Pin CERDIP
`44-Pin PLCC
`40-Pin Plastic DIP
`40-Pin CERDIP
`44-Pin PLCC
`40-Pin CERDIP
`44-Pin LCC
`
`PIN DESCRIPTIONS
`
`Vee: Supply voltage.
`
`Vss: Circuit ground.
`
`Port 0: Port 0 is an B-bit open drain bidirectional I/O
`port. As an output port each pin can sink B LS TTL
`inputs.
`
`Port 0 pins that have 1 s written to them float, and in
`that state can be used as high-impedance inputs.
`
`Port 0 is also the multiplexed low-order address and
`data bus during accesses to external Program and
`Data Memory. In this application it uses strong inter(cid:173)
`nal pull ups when emitting 1 s and can source and
`sink B LS TTL inputs.
`
`Port 0 also receives the code bytes during program(cid:173)
`ming of the EPROM parts, and outputs the code
`bytes during program verification of the ROM and
`EPROM parts. External pulfups are required during
`program verification.
`
`7-45
`
`VIZIO, Inc. Exhibit 1028
`2 of 14
`
`

`
`INTEL CORP (UP/PRPHLS)
`
`20E D II 4826175 0079080 6 II
`~OOI§!l.OIMJOOO~OO\'?
`T-49-19-07
`
`:--: t--J ~·: :"1 ;..: I"'• ~~ :~ LQ"' ::;~ tt:
`P1.5 !:! I.. .I I.
`.., "" ...... ~~ P0.4 (AD4)
`PU :O:l
`P1.7 :c
`RST i~]
`(RXDI P3.o m
`NC lt}
`(TXD) P3.1 JU
`{INTO) P3.2 m
`(INTI) P3.3 m
`(TO) P3.4 li~
`{T21 P3.s m
`
`L..O
`
`\...J
`
`..., ......
`
`... ""
`
`(~ P0.5(AD6)
`[it P0.8 (ADe)
`(l! P0.7 (AD7)
`m wv,.·
`[~ NC
`D! AWISJRRI•
`[H mti
`U! P2.7 (.1.15)
`(i! P2.1 (.1.14)
`:n P2.5 (A131
`:~: 1"!1 i21 fi! f~ 1Q1 ~ ~1 f~el f:.1 f~
`
`INDEX
`CORNER
`
`805218032 ON~Y
`
`Vee
`PO.O ADO
`PO.t AOI
`P0.2 AD2
`P0.3 AD3
`P0.4 AD4
`P0.5 ADS
`PO.& AD&
`P0.7 AD7
`EA/Vpp'
`A~EIPROG'
`PSEN
`P2.7 AIS
`P2.6AI4
`P2.5 .1.13
`P2.4 .1.12
`P2.3 All
`P2.2 AIO
`P2.1 .1.9
`P2.0 AI
`
`L~.::
`
`PI.O
`Pl.l
`Pl.2
`Pl.3
`PU
`PI.S
`Pl.&
`Pl.7
`RST
`RXD P3.0
`TXO P3.1
`INTO P3.2
`INTI P3.3
`TO P3.4
`Tl P3.5
`WRP3.6
`Rii P3.7
`XTAU
`XTALI
`Vss
`
`"EPROM only
`
`Pin (DIP)
`
`Pad
`(LCC,PLCC)
`
`270048-3
`
`Figure 2. MCS®-51 Connections
`
`Port 1: Port 1 is an 8-bit bidirectional 1/0 port with
`internal pullups. The Port 1 output buffers can sink/
`source 4 LS TTL inputs. Port 1 pins that have 1 s
`written to them are pulled high by the internal pull(cid:173)
`ups, and in that state can be used as inputs. As
`inputs, Port 1 pins that are externally being pulled
`low will source current (IlL on the data sheet) be(cid:173)
`cause of the internal pullups.
`
`Port 1 also· receives the low-order address bytes
`during programming of the EPROM parts and during
`program verification of the ROM and EPROM parts.
`
`In the 8032AH and 8052AH, Port 1 pins P1.0 and
`P1.1 also serve the T2 and T2EX functions, respec(cid:173)
`tively.
`
`Port 2: Port 2 is an 8-bit bidirectional 1/0 port with
`internal pullups. The Port 2 output buffers can sink/
`source 4 LS TTL inputs. Port 2 pins that have 1 s
`written to them are pulled high by the internal. pull-
`ups, and in that state can be used as inputs. As
`inputs, Port 2 pins that are externally being pulled
`low will source current (Ill on the data sheet) be(cid:173)
`cause of the internal pullups.
`
`Port 2 emits the high-order address byte during
`fetches from external Program Memory and during
`accesses to external Data Memory that use 16-bit
`addresses (MOVX ®DPTR). In this application it
`uses strong internal pullups when emitting 1s. Dur-
`
`ing accesses to external Data Memory that use 8-bit
`addresses (MOVX ®Ri), Port 2 emits the contents of
`the P2 Special Function Register.
`
`Port 2 also receives the high-order address bits dur(cid:173)
`ing programming of the EPROM parts and during
`program verification of the ROM and EPROM parts.
`
`Port 3: Port 3 is an 8-bit bidirectional 1/0 port with
`internal pullups. The Port 3 output buffers can sink/
`source 4 LS TTL inputs. Port 3 pins that have 1 s
`written to them are pulled high by the internal pull(cid:173)
`ups, and in that state can be used as inputs. As
`inputs, Port 3 pins that are externally being pulled
`low will source current (Ill on the data sheet) be(cid:173)
`cause of the pullups.
`
`Port 3 also serves the functions of various special
`features of the MCS-51 Family, as listed below:
`
`Alternative Function
`
`Port
`Pin
`P3.0
`RXD (serial input port)
`TXD (serial output port)
`P3.1
`INTO (external interrupt 0)
`P3.2
`INT1 (external interrupt 1)
`P3.3
`TO (Timer 0 external input)
`P3.4
`P3.5
`I:!Jlimer 1 external input)
`P3.6 WR (external data memory write strobe)
`RD (external data memory read strobe)
`P3.7
`
`7-46
`
`VIZIO, Inc. Exhibit 1028
`3 of 14
`
`

`
`INTEL CORP (UP/PRPHLS)
`infef
`
`20E 0 • 4826175 0079081 8 •
`IF>!RU§I!..OIMJOOO~OOW
`MCS®·51
`T-49-19-07
`XTAL 1: Input to the invertjng oscillator amplifier.
`
`RST: Reset input. A high on this pin for two machine
`cycles while the oscillator is running resets the de·
`vice.
`
`ALE/PROG: Address Latch Enable output pulse for
`latching the low byte of the address during accesses
`to external memory) This pin is also the program
`pulse input (PROG during programming of the
`EPROM parts.
`
`In normal operation ALE is emitted at a constant
`rate of Ys the oscillator frequency, and may be used
`for external timing or clocking purposes. Note, how(cid:173)
`ever, that one ALE pulse is skipped during each ac(cid:173)
`cess to external Data Memory.
`
`PSEN: Program Store Enable is the read strobe to
`external Program Memory.
`
`When the device is executing code from external
`Program Memory, PSEN is activated twice each ma(cid:173)
`chine cycle, except that two PSEN activations are
`skipped during each access to external Data Memo(cid:173)
`ry.
`
`EA/Vpp: External Access enable EA must be
`strapped to Vss in order to enable any MCS-51 de(cid:173)
`vice to fetch code from external Program memory
`locations starting at OOOOH up to FFFFH. EA must
`be strapped to Vee for internal program execution.
`
`Note, however, that if the Security Bit in the EPROM
`devices is programmed, the device will not fetch
`code from any location in external Program Memory.
`
`This pin also receives the 21V programming supply
`voltage (VPP) during programming of the EPROM
`parts.
`
`C2
`
`C1
`
`.... ------~ vss
`
`XTAL2: Output from the inverting oscillator amplifi·
`er.
`
`OSCILLATOR CHARACTERISTICS
`
`XT AL 1 and XTAL2 are the input and output, respec(cid:173)
`tively, of an inverting amplifier which can be config(cid:173)
`ured for use as an on-chip oscillator, as shown in
`Figure 3. Either a quartz crystal or ceramic resonator
`may be used. More detailed information concerning
`the use of the on-chip oscillator is available in Appli(cid:173)
`cation Note AP-155, "Oscillators for Microcontrol(cid:173)
`lers."
`
`To drive the device from an external clock source,
`XTAL1 should be grounded, while XTAL2 is driven,
`as shown in Figure 4. There are no requirements on
`the duty cycle of the external clock signal, since the
`input to the internal clocking circuitry is through a
`divide-by-two flip-flop, but minimum and maximum
`high and low times specified on the Data Sheet must
`be observed.
`
`EXTERNAL
`OSCILLATOR - - - - f XTAL2
`SIGNAL
`
`r---- XTAL1
`
`......--1 vss
`
`Figure 4. External Drive Configuration
`
`270048-5
`
`DESIGN CONSIDERATIONS
`
`If an 8751 BH or 8752BH may replace an 8751 H in a
`future design, the user should carefully compare
`both data sheets for DC or AC Characteristic differ(cid:173)
`ences. Note that the V1H and I1H specifications for
`the EA pin differ significantly between the devices.
`
`C1, C2 = 30 pF ± 10 pF for Ctystals
`= 40 pf' ± 10 pf' for Ceramic Resonators
`
`270048-4
`
`Figure 3. Oscillator Connections
`
`Exposure to light when the EPROM device is in op(cid:173)
`eration may cause logic errors. For this reason, it is
`suggested that an opaque label.be placed over the
`window when the die is exposed to ambient light.
`
`7-47
`
`VIZIO, Inc. Exhibit 1028
`4 of 14
`
`

`
`INTEL CORP (UP/PRPHLS)
`
`inter
`
`20E
`
`0 • 4826175 0079082 T •
`~OOI:§I!::.O~OOO~fi
`
`ABSOLUTE MAXIMUM RATINGS*
`
`Ambient Temperature Under Bias •••••• O"C fo 70"C
`Storage Temperature •••••••••• - 55•c to + 15o•c
`Voltage on EA/Vpp Pin to Vss ... -0.5V to + 21.5V
`Voltage on Any Other Pin to Vss .... -0.5V to + 7V
`Power Dissipation .......................... 1.5W
`
`-- T -49-19-07
`• Notice: Stresses above those listed under '~bso­
`lute Maximum Ra_tings" may cause permanent dam(cid:173)
`age to the device. This is a stress rating only and
`functional operation of the device at these or any
`other conditions above those indicated in the opera(cid:173)
`tional sections of this specification is not implied. Ex(cid:173)
`posure to absolute maximum rating conditions for
`extended periods may affect device reliability.
`
`VtL1
`
`VtH
`
`V1H1
`VoL
`VQL1
`
`v
`
`0.7
`
`0
`2.0 Vee+ 0.5 v
`2.5 Vee+ 0.5 v XTAL1 = Vss
`v
`0.45
`loL = 1.6mA
`
`:
`
`D.C. CHARACTERISTICS TA = o•cto7o•c;Vcc = 5V ±10%;Vss = ov
`Units Test Conditions
`Symbol
`Min
`Max
`Parameter
`v
`-0.5
`Input low Voltage (Except EA Pin of
`0.8
`VtL
`8751 H & 8751 H-8)
`Input Low Voltage to EA Pin of
`8751H & 8751H-8
`Input High Voltage (Except XTAL2, ·
`RST)
`Input High Voltage to XTAL2, RST
`Output Low Voltage (Ports 1, 2, 3)*
`Output Low Voltage (Port 0, ALE, PSEN)*
`8751H, 8751H·8
`
`0.60
`0.45
`0.45
`
`v
`v
`v
`v
`v
`
`loL = 3.2mA
`loL = 2.4mA
`loL = 3.2mA
`loH = -:'80 p.A
`loH = -400 p.A
`
`2.4
`2.4
`
`All Others
`Output High Voltage (Ports 1, 2, 3, ALE, PSEN)
`Output High Voltage (Port 0 in
`External Bus Mode)
`Logical 0 Input Current (Ports 1, 2, 3,
`RST) 8032AH, 8052AH
`All Others
`Logical 0 Input Current to EA Pin of
`8751 H & 8751 H-8 Only
`Logical 0 Input Current (XTAL2)
`Input Leakage Current (Port 0)
`8751H & 8751H-8
`All Others
`Logical1 Input Current to EA Pin of
`8751 H & 8751 H-8
`Input Current to RST to Activate Reset
`Power Supply Current:
`8031/8051
`8031AH/8051AH
`8032AH/8052AH
`8751H/8751H-8
`Pin Capacitance
`
`VoH
`VoH1
`
`ltL
`
`ltu
`
`I1L2
`lu
`
`ltH
`
`I1H1
`Icc
`
`C1o
`
`-800
`-500
`-15
`
`p.A VtN = 0.45V
`p.A VtN = 0.45V
`mA VtN = 0.45V
`
`-3.2
`
`rnA
`
`V1N = 0.45V
`
`±100
`±10
`500
`
`0.45 s V1N s Vee
`p.A
`0.45 s VtN s Vee
`p.A
`p.A VtN = 2.4V
`
`500
`
`160
`125
`175
`250
`10
`
`p.A
`
`V1N < (Vee -·1.5V)
`
`rnA
`rnA All Outputs
`rnA Disconnected;
`rnA EA =Vee
`pF Test freq = 1 MHz
`
`*NOTE:
`Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VoLs of ALE and Ports 1
`and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0
`transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may
`exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
`Trigger STROBE input.
`
`7-48
`
`I ,.
`
`H
`,.
`1..; I
`j
`
`VIZIO, Inc. Exhibit 1028
`5 of 14
`
`

`
`INTEL CORP (UP/PRPHLS)
`inter
`
`20E D .. 4826175 0079083 1 ..
`
`~OOI§!!..OIMIOOO~OOW
`
`T-49-19-07
`
`A.C. CHARACTERISTICS TA = o•cto +7o•c;Vcc = 5V ±10%;V55 = ov:
`Load Capacitance for Port 0, ALE, and PSEN = 1 00 pF;
`Load Capacitance for All Other Outputs = 80 pF
`12 MHz Oscillator
`Min
`Max
`
`Symbol
`
`Parameter
`
`1/TCLCL
`TLHLL
`TAVLL
`TLLAX
`TLLIV
`
`TLLPL
`TPLPH
`
`TPLIV
`
`TPXIX
`TPXIZ
`TPXAV
`TAVIV
`
`TPLAZ
`TRLRH
`TWLWH
`TRLDV
`TRHDX
`TRHDZ
`TLLDV
`TAVDV
`TLLWL
`TAVWL
`TQVWX
`
`TQVWH
`TWHQX
`TRLAZ
`TWHLH
`
`Oscillator Frequency
`ALE Pulse Width
`Address Valid to ALE Low
`Address Hold after ALE Low
`ALE Low to Valid lnstr In
`8751H
`Ali Others
`ALE Low to PSEN Low
`PSEN Pulse Width
`8751H
`Ali Others
`PSEN Low to Valid lnstr In
`8751H
`All Others
`input lnstr Hold after PSEN
`Input lnstr Float after PSEN
`PSEN to Address Valid
`Address to Valid lnstr in
`8751H
`All Others
`PSEN Low to Address Float
`RD Pulse Width
`WR Pulse Width
`RD Low to Valid Data in
`Data Hold after RD
`Data Float after RD
`. ALE Low to Valid Data In
`Address to Valid Data In
`ALE Low to RD or WR Low
`Address to RD or WR Low
`Data Valid to WR Transition
`8751H
`All Others
`Data Valid to WR High
`Data Hold after WR
`RD Low to Address Float
`RD or WR High tQ ALE High
`8751H
`All Others
`
`127
`43
`48.
`
`58
`
`190
`215
`
`0
`
`75
`
`400
`400
`
`0
`
`200
`203
`
`13
`23
`433
`33
`
`33
`43
`
`Variable Oscillator
`Max
`Min
`12.0
`3.5
`2TCLCL-4b
`TCLCL-40
`TCLCL-35
`
`183
`233
`
`100
`125
`
`63
`
`267
`302
`20
`
`252
`
`97
`517
`585
`300
`
`20
`
`133
`123
`
`4TCLCL-150
`4TCLCL-100
`
`3TCLCL-150
`3TCLCL-125
`
`TCLCL-20
`
`5TCLCL-150
`5TCLCL-115
`20
`
`5TCLCL-165
`
`2TCLCL-70
`BTCLCL-150
`9TCLCL-165
`3TCLCL+50
`
`TCLCL-25
`
`3TCLCL-60
`3TCLCL-35
`
`0
`
`TCLCL-8
`
`STCLCL-100
`STCLCL-100
`
`0
`
`3TCLCL-50
`4TCLCL-130
`
`TCLCL-70
`TCLCL-60
`7TCLCL-150
`TCLCL-50
`
`20
`
`TCLCL-50
`TCLCL-40
`
`TCLCL+50
`TCLCL+40
`
`Units
`
`MHz
`ns
`ns
`-ns
`
`ns
`ns
`ns
`
`ns
`ns
`
`ns
`ns
`ns
`ns
`ns
`
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`
`ns
`ns
`ns
`ns
`ns
`
`ns
`ns
`
`NOTE:
`•This table does not include the 8751·8 A.C. characteristics (see next page).
`
`7-49
`
`,,
`II
`
`VIZIO, Inc. Exhibit 1028
`6 of 14
`
`

`
`-INTEL CORP (UP/PRPHLS)
`
`This Table Is only for the 8751H·8
`
`20E D • 482617s oo79o84 3 •
`!F-'00[g!60!MIOOO&OOW
`
`MCS®·51
`
`. T -49-19-07
`
`A.C. CHARACTERISTICSTA = o•cto +700C;Vcc = 5V ±10%;V5s = OV;
`Load Capacitance for Port 0, ALE, and PSEN = 1 00 pF;
`Load Capacitance for All Other Outputs = 80 pF
`Variable Oscillator
`
`Symbol
`
`Parameter
`
`1/TCLCL Oscillator Frequency
`
`8 MHz Oscillator
`Min
`
`Max
`
`Min
`
`3.5
`2TCLCL-40
`
`TCLCL-40
`
`TCLCL-35
`
`TCLCL-25
`
`3TCLCL-60
`
`0
`
`TLHLL
`
`TAVLL
`
`TLLAX
`
`TLLIV
`
`TLLPL
`
`TPLPH
`
`TPLIV
`
`TPXIX
`
`TPXIZ
`
`TPXAV
`TAVIV
`
`TPLAZ
`
`ALE Pulse Width
`Address Valid to ALE Low
`
`Address Hold after ALE Low
`
`ALE Low to Valid lnstr In
`
`ALE Low to PSEN Low
`
`PSEN Pulse Width
`
`PSEN Low to Valid lnstr In
`
`210
`85
`
`90
`
`100
`
`315
`
`Input lnstr Hold after PSEN
`
`0
`
`Input lnstr Float after PSEN
`
`350
`
`225
`
`105
`
`PSEN to Address Valid
`
`117
`
`TCLCL-8
`
`Address to Valid lnstr In
`
`PSEN Low to Address Float
`
`Max
`8.0 .
`
`4TCLCL-150
`
`3TCLCL-150
`
`TCLCL-20
`
`5TCLCL-150
`
`Units
`
`-MHz
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`ns
`
`ns
`
`TRLRH
`RD Pulse Width
`TWLWH WR Pulse Width
`TRLDV
`RD Low to Valid Data In
`
`TRHDX
`
`Data Hold after RD
`
`TRHDZ
`TLLDV
`
`TAVDV
`
`TLLWL
`
`Data Float after RD
`ALE Low to Valid Data In
`Address to Valid Data·tn
`
`ALE Low to RD or WR Low
`
`TAVWL
`
`Address to RD or WR Low
`
`TQVWX
`
`Data Valid to WR Transition
`
`TQVWH
`
`Data Valid to WR High
`
`TWHQX
`
`Data Hold after WR
`
`TRLAZ
`
`TWHLH
`
`RD Low to Address Float
`RD or WR High to ALE High
`
`650
`
`650
`
`0
`
`325
`
`370
`
`55
`
`725
`
`75
`
`75
`
`475
`20
`
`460
`
`180
`850
`
`960
`
`425
`
`20
`
`175
`
`6TCLCL-100
`
`6TCLCL-100
`
`0
`
`20
`
`5TCLCL-165
`
`2TCLCL-70
`
`8TCLCL-150
`9TCLCL-165
`
`3TCLCl-50
`
`3TCLCL+50
`
`4TCLCL-130
`
`TCLCL-70
`
`7TCLCL-150
`
`TCLCL-50
`
`20
`
`TCLCL-50
`
`TCLCL+50
`
`ns
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`7-50
`
`VIZIO, Inc. Exhibit 1028
`7 of 14
`
`

`
`INTEL CORP (UP/PRPHLS)
`intef
`
`20E 0 • 4826175 oo79085 5 •
`lf)OO~I!..OIMIOOO~OOW
`MCS®-51
`
`EXTERNAL PROGRAM MEMORY READ CYCLE
`
`.· T -49-19-07
`
`PORT~
`
`PoftT2
`
`270048-6
`
`7-51
`
`l
`
`VIZIO, Inc. Exhibit 1028
`8 of 14
`
`

`
`INTEL CORP (UP/PRPHLS)
`
`20E D II
`
`MCS®-51
`
`4826175 0079086 7 II
`fP>OO[g!!..OIMJOOO~OOW
`
`EXTERNAL DATA MEMORY READ CYCLE
`
`T-49-19-07
`
`ALE
`
`POIIT Q
`
`-t----TRLRH +---M
`
`POIIT2
`
`P2.0-P2.7 OR Al-A IS FROM DPH
`
`Al-A 15 FROM PCH
`
`270048-7
`
`EXTERNAL DATA MEMORY WRITE CYCLE
`
`ALE
`
`TWHLH
`
`TLLWL -1*">------TWLWH -----J
`
`TQVWX
`~-._---t 1-+4---TQYWH------o~
`
`PORTO
`
`DATA OUT
`
`PORTa
`
`P2.0-~.7 OR A8-A15 FROM OPH
`
`A8-A15 FROM PCH
`
`270048-8
`
`7-52
`
`VIZIO, Inc. Exhibit 1028
`9 of 14
`
`

`
`INTEL CORP (UP/PRPHLS)
`infer
`
`20E
`
`D • 4826175 oo79087 9 •
`~OO[gll.OIMIOOO~OOW
`MCS®-51
`T-49-19-07
`
`Symbol
`
`Parameter
`
`SERIAL PORT TIMING-SHIFT REGISTER MODE ·
`Test Conditions: TA = o•c to 70"C; VCC = 5V ±10%; VSS = OV; Load Capacitance= 80 pF
`12 MHz Oscillator
`Variable Oscillator
`Min
`Max
`Max
`Min
`1.0
`12TCLCL
`700
`10TCLCL -133
`
`TXLXL Serial Port Clock Cycle Time
`TQVXH Output Data Setup to Clock Rising
`Edge
`TXHQX Output Data Hold after Clock
`Rising Edge
`Input Data Hold after Clock Rising
`Edge
`TXHDV Clock Rising Edge to Input Data .
`Valid
`
`TXHDX
`
`SHIFT REGISTER TIMING WAVEFORMS
`
`t
`
`Cl.tM"'
`
`•
`
`Units
`
`p.s
`ns
`
`·· ns
`
`ns
`
`50
`
`0
`
`2TCLCL-117
`
`0
`
`700
`
`10TCLCL-133
`
`ns
`
`I
`
`I
`
`•
`
`t .....
`
`270048-9
`
`7-53
`
`VIZIO, Inc. Exhibit 1028
`10 of 14
`
`

`
`INTEL CORP (UP/PRPHLS)
`infef
`
`20E D
`MCS®-51
`
`.. 4826175 0079088 0 ..
`!P'ffiljg(LOIMJOOO~OOW
`
`EXTERNAL CLOCK DRIVE
`Symbol
`
`Parameter-·
`
`1/TCLCL
`
`TCHCX
`
`TCLCX
`TCLCH
`
`TCHCL
`
`Oscillator Frequency (except 8751 H-8)
`8751H-8
`
`High Time
`
`Low Time
`
`Rise Time
`
`Fall Time
`
`EXTERNAL CLOCK DRIVE WAVEFORM
`
`Min
`3.5
`3.5
`
`20
`20
`
`T-49-19-07
`
`Max
`
`12
`8
`
`20
`
`20
`
`Units
`
`MHz
`MHz
`
`ns
`ns
`
`ns
`
`n&-.
`
`...... ----TCLCL-------i~
`
`270048-10
`
`A.C. TESTING INPUT, OUTPUT WAVEFORM
`
`> lEST POINTS <
`
`2.0
`
`0.1
`
`2.0
`
`0.1
`
`•
`
`270048-11
`A.C. Testing: Inputs are driven at 2.4V for a logic "1" and 0.45V
`for a logic "0". Timing measurements are made at 2.0V for a
`logic "1" and o.av for a logic "O".
`
`7-54
`
`..
`
`VIZIO, Inc. Exhibit 1028
`11 of 14
`
`

`
`INTEL CORP (UP/PRPHLS)
`intef
`
`20E Q .. 4826175 0079089 2 ..
`~[ru[g!L.OIMIOOO~OOW
`
`MCS®-51
`
`EPROM CHARACTERISTICS
`Table 3. EPROM Programming Modes
`EA
`P2.7
`PSEN
`ALE
`o•
`0
`VPP
`1
`0
`X
`1
`1
`0
`0
`1
`1
`o•
`0
`VPP
`1
`
`RST
`1
`1
`1
`1
`
`Mode
`Program
`Inhibit
`Verify
`Security Set
`NOTE:
`"1" "" logiC high for that pin
`"0" = logic low for that pin
`.. X .. = .. don't care"
`
`T-49-19-07
`
`P2.6
`0
`0
`0
`1
`
`P2.5
`X
`X
`X
`X
`
`P2.4
`X
`X
`X
`X
`
`"VPP" = +21V ±0.5V
`•ALE is pulsed low for 50 ms .
`
`Note that the EAIVPP pin must not be allowed to go
`above the maximum specified VPP level of 21.5V for
`any amount of time. Even a narrow glitch above that
`voltage level can cause permanent damage to the
`device. The VPP source should be well regulated
`and free of glitches.
`
`Program Verification
`If the Security Bit has not been programmed, the on(cid:173)
`chip Program Memory can be read out for verifica(cid:173)
`tion purposes, if desired, either during or after the
`programming operation. The address of the Program
`Memory location to be read is applied to Port 1 and
`pins P2.0-P2.3. The other pins should be held at the
`"Verify" levels indicated in Table 3. The contents of
`the addressed location will come out on Port 0. Ex(cid:173)
`ternal pullups are required on Port 0 for this opera(cid:173)
`tion.
`
`The setup, which is shown in Figure 6, is the same
`as for programming the EPROM except that pin P2.7
`is held at a logic low, or may be used as an active(cid:173)
`low read strobe.
`
`+SV
`
`Figure 6. Program Verification
`
`270048-13
`
`7-55
`
`Programming the EPROM
`To be programmed, the part must be running with a
`4 to 6 MHz oscillator. (The reason the oscillator
`needs to be running is that the internal bus is being
`used to transfer address and program data to appro(cid:173)
`priate internal registers.) The address of an EPROM
`location to be programmed is applied to Port 1 and
`pins P2.0-P2.3 of Port 2, while the code byte to be
`programmed into that location is applied to Port 0.
`The other Port 2 pins, and RST, PSEN, and EA
`should be held at the "Program" levels indicated in
`Table 3. ALE is pulsed low for 50 ms to program the
`code byte into the addressed EPROM location. The
`setup is shown in Figure 5.
`
`Normally EA is held at a logic high until just before
`ALE is to be pulsed. Tlien EA is raised to + 21V,
`ALE is pulsed, and then EA is returned to a logic
`high. Waveforms and detailed timing specifications
`are shown in later sections of this data sheet.
`
`+5V
`
`1151H
`
`P2.4
`
`P2.5
`
`P2.f
`P2.7
`r---t--l XTAL2
`
`Figure 5. Programming Configuration
`
`270048-12
`
`VIZIO, Inc. Exhibit 1028
`12 of 14
`
`

`
`INTEL CORP (UP/PRPHLS)
`
`inter
`
`20E D II 4826175 0079090 9 II
`~OO!§I!:.OIMIOOO&OOW
`
`MCS®·51
`
`EPROM Security
`
`The security feature consists of a "locking" bit which
`when programmed denies electrical access by any
`external means to the on-chip Program Memory.
`The bit is programmed as shown in Figure 7. The
`'setup and procedure are the same as for normal
`EPROM programming, except that P2.6 is held at a
`logic high. Port 0, Port 1, and pins P2.0-P2.3 may be
`in any state. The other pins should be held at the
`"Security" levels indicated in Table 3.
`
`Once the Security Bit has been programmed, it can
`be cleared only by full erasure of the Program Mem(cid:173)
`ory. While it is programmed, the internal Program
`Memory can not be read out, the device can not be
`further programmed, and it can not execute out of
`external program memory. Erasing the EPROM,
`thus clearing the Security Bit, restores the device's
`full functionality. It can then be reprogrammed.
`
`Erasure Characteristics
`
`Erasure of the EPROM begins to occur when the
`chip is exposed to light with wavelengths shorter
`than approximately 4,000 Angstroms. Since sunlight
`and fluorescent lighting have wavelengths in this
`range, exposure to these light sources over an ex(cid:173)
`tended lime (about 1 week in sunlight, or 3 years in
`room-level fluorescent lighting) could cause inadver(cid:173)
`tent erasure. If an application subjects the device to
`this type of exposure, it is suggested that an opaque
`label be placed over the window.
`
`X = "DON'T <;ARE"
`
`T-49-19-07
`+SV
`
`X
`
`X
`
`EAIVPP
`
`VIH1
`
`270048-14
`
`Figure 7. Programming the Security Bit
`
`The recommended erasure procedure is exposure
`to ultraviolet light (at 2537 Angstroms) to an integrat(cid:173)
`ed dose of at least 15 W-sec/cm2. Exposing the
`EPROM to an ultraviolet lamp of 12,000 p.W/cm2
`rating for 20 to 30 minutes, at a distance of about 1
`inc~, should be sufficient.
`
`Erasure leaves the array in an all 1 s state.
`
`EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
`TA = 21•c to 2rc; vee= 5V ± 10%; vss = ov
`Symbol
`Parameter
`VPP
`Programming Supply Voltage
`IPP
`Programming Supply Current
`1/TCLCL
`Oscillator Frequency
`Address Setup to PROG Low
`TAVGL
`Address Hold after PROG -
`TGHAX
`TDVGL
`Data Setup to PROG Low
`TGHDX
`Data Hold after PROG
`TEHSH
`P2.7 (ENABLE) High to VPP
`TSHGL
`VPP Setup to PROG Low
`TGHSL
`VPP Hold after PROG
`TGLGH
`PROGWidth
`Address to Data Valid
`TAVQV
`TELQV
`ENABlE Low to Data Valid
`TEHQZ
`Data Float after ENABLE
`
`Min
`20.5
`
`4
`48TCLCL
`48TCLCL
`48TCLCL
`48TCLCL
`48TCLCL
`10
`10
`45
`
`0
`
`7-56
`
`Units
`v
`rnA
`MHz
`
`p.S
`MS
`ms
`
`Max
`21.5
`30
`6
`
`55
`48TCLCL
`48TCLCL
`48TCLCL
`
`VIZIO, Inc. Exhibit 1028
`13 of 14
`
`

`
`~ -TGHDX
`~ TGHAX
`
`'w
`
`TGLGH
`21V ± .sv
`
`TAVGL
`
`1
`
`L!/PROG
`
`TSHGL
`
`Ei./vPf'~
`
`TEHSit
`1--
`
`P2.7
`(ENABLE) J
`
`TGHSL
`
`'
`
`\
`
`nLHIGH
`
`TTL HIGH
`
`nLHIGH
`
`TELQV-
`
`~-- f--TEHQZ
`
`'
`
`I
`
`270048-15
`
`INTEL CORP (UP/PRPHLS)
`
`20E D •
`
`4826175 0079091 0 •
`
`EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
`
`T-49-19-07
`
`MCS®-51
`
`p
`1.0-91.7
`P2 .CI-P2.3
`
`PROGRAMMING
`
`ADORESS
`
`PORTO
`
`DATA IN
`
`TDVGtf- -
`
`-
`
`"' J
`
`VERIFI~ATION
`
`AIIORESS
`
`-TAVQV
`
`DATA OUT
`
`For programming conditions see F"~gure 5.
`
`For verification conditions see Figure 6.
`
`DATA SHEET REVISION SUMMARY
`The following are the key differences between this and the -003 version of this data sheet:
`1. Introduction was expanded to include product descriptions ..
`2. Package table was added.
`·
`3. Design Considerations added.
`4. Test Conditions for I1L 1 and I1H specifications added to the DC Characteristics.
`5. Data Sheet Revision Summary added.
`
`7-57
`
`VIZIO, Inc. Exhibit 1028
`14 of 14