P8748H/P8749H
`8048AH/8035AHL/8049AH/8039AHL/8050AH/8040AHL
`HMOS SINGLE-COMPONENT 8-BIT
`MICROCONTROLLER
`• Programmable ROMs Using 21V
`High Performance HMOS II
`• Easily Expandable Memory and 1/0
`Interval Time/Event Counter
`• Up to 1.36 p,s Instruction Cycle All
`Two Single Level Interrupts
`Single 5-Volt Supply
`Over 96 Instructions; 90% Single Byte
`The Intel MCS®-48 family are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
`using Intel's advanced N-channel silicon gate HMOS process.
`The family contains 27 1/0 lines, an 8-bit timer/counter, and on-board oscillator/clock circuits. For systems
`that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
`
`Instructions 1 or 2 Cycles
`
`•
`•
`•
`• •
`
`These microcontrollers are available in both masked ROM and ROMiess versions as well as a new version,
`The Programmable ROM. The Programmable ROM provides the user with the capability of a masked ROM
`while providing the flexibility of a device that can be programmed at the time of requirement and to the desired
`data. Programmable ROM's allow the user to lower inventory levels while at the same time decreasing delay
`times and code risks.
`
`These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
`extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
`program memory results from an instruction set consisting of mostly single byte instructions and no instruc(cid:173)
`tions over 2 bytes in length.
`
`Device
`8050AH
`8049AH
`8048AH
`8040AHL
`8039AHL
`8035AHL
`P8749H
`P8748H
`
`Internal
`4Kx 8 ROM
`2Kx8 ROM
`1Kx 8 ROM
`None
`None
`None
`2K x 8 Programmable ROM
`1 K x 8 Programmable ROM
`
`Memory
`256x8 RAM
`128 x8 RAM
`64x8 RAM
`256x8 RAM
`128x8 RAM
`64x8 RAM
`128x8 RAM
`64x8 RAM
`
`RAM STANDBY
`yes
`yes
`yes
`yes
`yes
`yes
`no
`no
`
`Figure 1. Block Diagram
`
`270053-1
`
`Figure 2. Logic Symbol
`
`270053-2
`
`August 1989
`Order Number: 270053-0Q3
`
`1-27
`
`VIZIO, Inc. Exhibit 1021
`1 of 13
`
`

`
`MCS®-48
`
`intel~
`
`1
`
`TO
`XTAL 1
`XTAL 2
`RESET
`55
`iNT
`EA
`Ali
`PSEN
`Wii
`ALE
`DBo 12
`DB1
`13
`082 14
`DB3 15
`DS. 11
`DBs 11
`DBe
`087
`vss
`
`6 5" l
`
`2 144-43424140
`
`iNi'
`EA
`Rli
`PSEN
`W.
`NC
`ALE
`080
`081
`082
`083
`
`10
`11
`12
`13
`14
`15
`16
`17
`
`8049AH/8039AHL
`8050AH/8040AHL
`«-PIN
`PLCC
`
`Top VIew
`Looking down on PC Boord
`
`39
`38
`37
`36
`35
`34
`33
`32
`31
`30
`29
`
`P2.-4
`P1.7
`P1.6
`P1.5
`P1.4
`NC
`Pl.l
`P1.2
`P1.1
`P1.0
`VDO
`
`18 19 20 21 22 232" 25 26 27 28
`
`270053-3
`
`270053-14
`
`Figure 3. Pin Configuration
`
`Figure 4. Pad Configuration
`
`Symbol
`
`Vss
`Voo
`
`Pin
`No.
`20
`26
`
`Table 1. Pin Description
`
`Function
`
`Circuit GND potential.
`+ 5V during normal operation.
`Low power standby pin.
`
`Programming power supply ( + 21 V).
`
`Vee
`PROG
`
`40
`25
`
`Main power supply; + 5V during operation and programming.
`Output strobe for 8243 1/0 expander.
`Program pulse ( + 18V) input pin During Programming.
`
`27-34
`
`8-bit quasi-bidirectional port.
`
`21-24
`35-38
`
`8-bit quasi-bidirectional port. P20-P23 contain the four high order
`program counter bits during an external program memory fetch and
`serve as a 4-bit 1/0 expander bus for 8243.
`
`12-19 True bidirectional port which can be written or read synchronously
`using the RD, WR strobes. The port can also be statically latched.
`Contains the 8 low order program counter bits during an external
`program memp~ fetch, and receives the addressed instruction under
`the control of EN. Also contains the address and data during an
`external RAM data store instruction, under control of ALE, RD. and
`WR.
`Input pin testable using the conditional transfer instruction JTO and
`JNTO. TO can be designated as a clock output using ENTO CLK
`instruction.
`Used during programming.
`
`1
`
`P10-P17
`Port 1
`P20-P23
`P24-P27
`Port 2
`DBO-DB7
`BUS
`
`TO
`
`1-28
`
`Device
`
`All
`All
`8048AH
`8035AHL
`8049AH
`8039AHL
`8050AH
`8040AHL
`P8748H
`P8749H
`All
`All
`P8748H
`P8749H
`All
`
`All
`
`All
`
`All
`
`P8748H
`P8749H
`
`I
`
`VIZIO, Inc. Exhibit 1021
`2 of 13
`
`

`
`Table 1. Pin Description (Continued)
`
`Function
`
`Device
`
`Input pin testable using the JT1, and JNT1 instructions. Can be
`designated the timer/counter input using the STAT CNT instruction.
`Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is
`disabled after a reset. Also testable with conditional jump instruction.
`(Active low) interrupt must remain low for at least 3 machine cycles for
`proper operation.
`Output strobe activated during a BUS read. Can be used to enable
`data onto the bus from an external device.
`Used as a read strobe to external data memory. (Active low)
`Input which is used to initialize the processor. (Active low) (Non TIL
`VI H)
`Used during power down.
`
`Used during programming.
`
`Used during ROM verification.
`
`All
`
`All
`
`All
`
`All
`
`8048AH
`8035AHL
`8049AH
`8039AHL
`8050AH
`8040AHL
`P8748H
`P8749H
`8048AH
`P8748H
`8049AH
`P8749H
`8050AH
`All
`
`All
`
`All
`
`All
`
`8048AH
`8035AHL
`8049AH
`8039AHL
`8050AH
`8040AHL
`All
`
`P8748H
`P8749H
`8048AH
`8049AH
`8050AH
`All
`
`All
`
`1-29
`
`Symbol
`
`T1
`
`INT
`
`AD
`
`RESET
`
`Pin
`No.
`39
`
`6
`
`8
`
`4
`
`WR
`
`ALE
`
`PSEN
`ss
`
`10
`
`11
`
`9
`
`5
`
`Output strobe during a bus write. (Active low)
`Used as write strobe to external data memory.
`Address latch enable. This signal occurs once during each cycle and is
`useful as a clock output.
`The negative edge of ALE strobes address into external data and
`program memory.
`Program store enable. This output occurs only during a fetch to
`external program memory. (Active low)
`Single step input can be used in conjunction with ALE to "single step"
`the processor through each instruction.
`(Active low) Used in sync mode.
`
`EA
`
`7
`
`External access input which forces all program memory fetches to
`reference external memory. Useful for emulation and debug. (Active
`high)
`Used during (18V) programming.
`
`Used during ROM verification (12V).
`
`XTAL1
`
`XTAL2
`
`2
`
`3
`
`One side of crystal input for internal oscillator. Also input for external
`source. (Non TIL V1H)
`Other side of crystal input.
`
`I
`
`VIZIO, Inc. Exhibit 1021
`3 of 13
`
`

`
`MCS®-48
`
`Accumulator
`
`Table 2. Instruction Set
`--- ~-------
`
`Input/Output
`
`infel®
`
`Mnemonic
`ADDA, A
`ADDA, @A
`
`ADDCA, @A
`
`ANLA, A
`ANLA, @A
`
`Description
`Add register to A
`Add data memory
`to A
`ADDA, #data 1\dd immediate to A
`ADDCA, A
`Add register with
`carry
`Add data memory
`with carry
`ADDC A. *data Add immediate with
`carry
`And register to A
`And data memory
`to A
`ANLA, #data And immediate to A
`ORLA, A
`Or reg1ster to A
`ORLA, @A
`Or data memory
`to A
`ORL A, #data Or immediate to A
`XRLA, A
`Exclusive or register
`to A
`Exclusive or data
`memory to A
`XRLA, #data Exclusive or
`1m mediate to .A
`Increment A
`Decrement A
`Clear A
`Complement A
`Decimal adjust A
`Swap nibbles of A
`Rotate A left
`Rotate A left
`through carry
`Rotate A right
`Rotate A right
`through carry
`
`XRLA, @A
`
`INCA
`DECA
`CLRA
`CPLA
`DAA
`SWAP A
`ALA
`RLCA
`
`RRA
`RRCA
`
`Bytes Cycles
`1
`1
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`Mnemonic
`INA, P
`joUTLP, A
`ANL P, #data
`
`Description
`Input port to A
`Output A to port
`And immediate to
`port
`ORL P, #data Or immediate to
`port
`INS A, BUS
`Input BUS to A
`OUTLBUS, A
`Output A to BUS
`v-.NL BUS, #data And immediate to
`BUS
`ORL BUS, #data Or immediate to
`BUS
`Input expander port
`to A
`Output A to
`expander port
`And A to expander
`port
`Or A to expander
`port
`
`MOVDA,P
`
`MOVD P, A
`
`ANLD P,A
`
`ORLDP, A
`
`Bytes Cycles
`1
`1
`2
`
`2
`2
`2
`
`2
`
`1
`2
`
`2
`
`2
`
`2
`2
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`Registers
`
`Mnemonic
`INCA
`INC@R
`DECR
`
`Description
`Increment register
`Increment data memory
`Decrement register
`
`Bytes Cycles
`
`Branch
`
`Mnemonic
`Description
`JMP addr
`Jump unconditional
`JMPP @A
`Jump indirect
`DJNZ A, addr Decrement register
`and skip
`Jump on carry = 1
`Jump on carry = 0
`Jump on A zero
`Jump on A not zero
`Jump on TO= 1
`Jump onTO= 0
`JumponT1 = 1
`Jump on Tt = 0
`Jump on FO = 1
`Jump on F1 = 1
`Jump on timer flag
`Jump on INT = 0
`Jump on accumulator
`bit
`
`JC addr
`JNCaddr
`JZ addr
`JNZ addr
`JTO addr
`JNTO addr
`JT1 addr
`JNT1 addr
`JFOaddr
`JF1 addr
`JTF addr
`JNI addr
`JBb addr
`
`Bytes Cycles
`2
`2
`1
`2
`2
`2
`
`2
`2
`2
`2
`2
`2
`2
`2
`2
`2
`2
`2
`2
`
`2
`2
`2
`2
`2
`2
`2
`2
`2
`2
`2
`2
`2
`
`1-30
`
`I
`
`VIZIO, Inc. Exhibit 1021
`4 of 13
`
`

`
`~------------------------T_a_b_l_e_2_._1n_s_tr __ uctionrs_e_t_(C_o_n_t_in_u_e_d_l ________________________ ~
`Subroutine
`Timer/Counter
`
`MCS®-48
`
`Mnemonic
`CALL addr
`RET
`RETR
`
`Description
`Jump to subroutine
`Return
`Return and restore
`status
`
`Bytes Cycles
`2
`2
`1
`2
`1
`2
`
`Flags
`
`Mnemonic
`CLRC
`CPLC
`CLR FO
`CPLFO
`CLRF1
`CPLF1
`
`Description
`Clear carry
`Complement carry
`ClearflagO
`Complement flag 0
`Clear flag 1
`Complement flag 1
`
`Bytes Cycles
`1
`1
`1
`1
`1
`1
`1
`1
`1
`1
`1
`1
`
`Data Moves
`
`Mnemonic
`MOVA,R
`MOVA, ®R
`
`MOVR,A
`MOV®R,A
`
`Bytes Cycles
`1
`1
`1
`1
`1
`1
`1
`1
`1
`1
`1
`1
`
`Description
`Read timer/counter
`Load timer I counter
`Start timer
`Start counter
`Stop timer I counter
`Enable timer I
`counter interrupt
`Disable timer I
`counter interrupt
`
`Mnemonic
`MOVA, T
`MOVT,A
`STRTT
`STRTCNT
`STOPTCNT
`ENTCNTI
`
`DISTCNTI
`
`Control
`
`Bytes Cycles
`1
`1
`
`DIS I
`
`Mnemonic
`ENI
`
`Description
`Enable external
`interrupt
`Disable external
`interrupt
`Select register bank 0
`SEL ABO
`Select register bank 1
`SELRB1
`SEL MBO Select memory bank 0
`SELM81 Select memory bank 1
`ENTOCLK Enable clock output
`on TO
`
`Mnemonic
`NOP
`
`Description
`No operation
`
`Bytes Cycles
`1
`1
`
`Bytes Cycles
`1
`1
`1
`1
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`Description
`Move register to A
`Move data memory
`to A
`MOVA, #data Move immediate to
`A
`Move A to register
`Move A to data
`memory
`MOVR, #data Move immediate to
`register
`MOV ®R, #data Move immediate to
`data memory
`MOVA, PSW Move PSWtoA
`MOVPSW,A Move A to PSW
`XCHA, R
`Exchange A and
`register
`Exchange A and
`data memory
`Exchange nibble of
`A and data memory
`Move external data
`memory to A
`MOVX®R,A Move A to external
`data memory
`Move to A from
`current page
`MOVP3A, ®A Move to A from
`page3
`
`XCHA, ®R
`
`XCHDA, ®R
`
`MOVXA, ®R
`
`MOVPA, ®A
`
`I
`
`1-31
`
`VIZIO, Inc. Exhibit 1021
`5 of 13
`
`

`
`MCS®-48
`
`ABSOLUTE MAXIMUM RATINGS*
`
`Case Temperature Under Bias ....... o•c to + 7o•c
`Storage Temperature .......... - 55•c to + 15o•c
`Voltage on any Pin with Respect
`to Ground ...................... - 0.5V to + 7V
`Power Dissipation .......................... 1.5W
`
`NOTICE: This is a production data sheet. The specifi(cid:173)
`cations are subject to change without notice.
`• WARNING: Stressing the device beyond the "Absolute
`Maximum Ratings" may csuse permanent damage.
`These are stress ratings only. Operstion beyond the
`"Operating Conditions" is not recommended and ex(cid:173)
`tended exposure beyond the "Operating Conditions"
`msy affect device reliability.
`
`D.C. CHARACTERISTICS TA = o•cto +7o•c;Vee = Voo = 5V ±10o/o;Vss = ov
`Limits
`Typ
`
`Min
`-0.5
`
`Max
`0.8
`
`0.6
`
`Vee
`
`Vee
`
`0.45
`
`0.45
`
`0.45
`
`0.45
`
`-0.5
`
`2.0
`
`3.8
`
`2.4
`
`2.4
`
`2.4
`
`Symbol
`
`Parameter
`
`Input Low Voltage (All
`Except RESET, X1, X2)
`
`Input Low Voltage
`(RESET, X1, X2)
`
`Input High Voltage
`(All Except XT AL 1,
`XTAL2, RESET)
`
`Input High Voltage
`(X1, X2, RESET)
`
`Output Low Voltage
`(BUS)
`
`Output Low Voltage
`(RD, WR, PSEN, ALE)
`Output Low Voltage
`(PROG)
`
`Output Low Voltage
`(All Other Outputs)
`
`Output High Voltage
`(BUS)
`
`Output High Voltage
`(RD. WR, PSEN, ALE)
`
`Output High Voltage
`(All Other Outputs)
`
`v,L
`
`V1L1
`
`v,H
`
`VIH1
`
`VoL
`
`Vou
`
`VoL2
`
`VQL3
`
`VoH
`
`VoH1
`
`VoH2
`
`1-32
`
`Unit
`
`Teat Conditions
`
`v
`
`v
`
`v
`
`v
`
`v
`
`v
`
`v
`
`v
`
`v
`
`v
`
`v
`
`loL = 2.0mA
`
`loL = 1.8 rnA
`
`IQL = 1.0mA
`
`loL = 1.6 rnA
`
`loH = - 400 /LA
`
`loH = -100 /LA
`
`loH = -40 /LA
`
`Device
`
`All
`
`All
`
`All
`
`All
`
`All
`
`All
`
`All
`
`All
`
`All
`
`All
`
`All
`
`I
`
`VIZIO, Inc. Exhibit 1021
`6 of 13
`
`

`
`MCS®-48
`
`D.C. CHARACTERISTICS TA = O"Cto +70"C;Vcc = Voo = sv ±10%;Vss = OV(Continued)
`Umlts
`
`Unit
`
`Test Conditions
`
`Device
`
`Symbol
`
`Parameter
`
`Leakage Current
`(T1' Tm')
`Input Leakage Current
`(P10-P17, P20-P27,
`EA,SS)
`
`Input Leakage Current
`RESET
`Leakage Current
`(BUS, TO) (High
`Impedance State)
`
`Voo Supply Current
`(RAM Standby)
`
`Min
`
`Typ Max
`
`±10
`
`!J-A
`
`Vss :S: V1N :S: Vee
`
`-500
`
`!J-A
`
`Vss + 0.45 :S: V1N s Vee
`
`-10
`
`-300
`
`!J-A
`
`Vss s V1N s 3.8
`
`±10
`
`!J-A
`
`Vss s V1N S Vee
`
`3
`
`4
`
`5
`
`5
`
`7
`
`mA
`
`mA
`
`10
`
`mA
`
`Total Supply Current•
`
`30
`
`65
`
`mA
`
`lu
`
`lu1
`
`lu2
`
`ILo
`
`loo
`
`loo +
`Icc
`
`35
`
`70
`
`mA
`
`40
`
`80
`
`mA
`
`30
`
`50
`
`100
`
`110
`
`5.5
`
`5.5
`
`mA
`
`mA
`v
`
`v
`
`Standby Mode Reset
`:S:VIL1
`
`Voo
`
`RAM Standby Voltage
`
`2.2
`
`2.2
`
`All
`
`All
`
`All
`
`All
`
`8048AH
`8035AHL
`
`8049AH
`8039AHL
`
`8050AH
`8040AHL
`
`8048AH
`8035AHL
`
`8049AH
`8039AHL
`
`8050AH
`8040AHL
`
`P8748H
`
`P8749H
`
`8048AH
`8035AH
`
`8049AH
`8039AH
`
`8050AH
`8040AHL
`"Icc + 100 are measured with all outputs In their high Impedance state; RrSET low; 11 MHz crystal applied; INT. SS. and EA floatmg.
`
`2.2
`
`5.5
`
`v
`
`I
`
`1-33
`
`VIZIO, Inc. Exhibit 1021
`7 of 13
`
`

`
`MCS®-48
`
`Symbol
`
`Parameter
`
`A.C. CHARACTERISTICS T A = o•c to + 7o•c; Vee = v 00 = 5V ± 10%; Vss = ov
`11 MHz
`f (t)
`(Note 3)
`
`Min
`
`Max
`
`Unit
`
`t
`
`ILL
`
`IAL
`
`tLA
`
`tcc1
`
`tcc2
`
`tow
`
`two
`
`toR
`
`IR01
`
`IR02
`
`tAw
`
`tA01
`
`IA02
`
`tAFC1
`
`Clock Period
`
`ALE Pulse Width
`
`Addr Setup to ALE
`
`Addr Hold from ALE
`
`Control Pulse Width (AD, WR)
`
`Control Pulse Width (PSEN)
`
`Data Setup before WR
`
`Data Hold after WR
`
`Data Hold (RD. PSEN)
`
`RDto Data in
`
`PSEN to Data in
`
`Addr Setup to WR
`
`90.9
`
`150
`
`70
`
`50
`
`480
`
`350
`
`390
`
`40
`
`0
`
`1 /xtal freq
`
`3.5!-170
`
`2t-110
`
`t-40
`
`7.5!-200
`
`6t-200
`
`6.5!-200
`
`t-50
`
`1.5!-30
`
`6t-170
`
`4.5!-170
`
`5t-150
`
`300
`
`Addr Setup to Data (AD)
`
`Addr Setup to Data (PSEN)
`
`10.5t-220
`
`7.5!-200
`
`Addr Float to RD. WR
`
`2t-40
`
`140
`
`1000
`
`110
`
`375
`
`240
`
`730
`
`460
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`Conditions
`(Note 1)
`
`(Note3)
`
`(Note2)
`
`(Note2)
`
`(Note2)
`
`tAFC2
`
`tLAFC1
`
`tLAFC2
`
`tcA1
`
`tcA2
`
`tcp
`
`tpc
`
`tpR
`
`tpF
`
`top
`
`tpo
`
`tpp
`
`tpL
`
`tLP
`tpv
`
`Addr Float to PSEN
`
`ALE to Control (RD. WR)
`
`ALE to Control (PSEN)
`
`Control to ALE (AD, WR, PROG)
`
`Control to ALE (PSEN)
`
`Port Control Setup to PROG
`
`Port Control Hold to PROG
`
`PROG to P2 Input Valid
`
`Input Data Hold from PROG
`
`Output Data Setup
`
`Output Data Hold
`
`PROG Pulse Width
`
`Port 2 1/0 Setup to ALE
`
`Port 21/0 Hold to ALE
`
`Port Output from ALE
`
`toPRR
`
`tcv
`
`TO Rep Rate
`
`Cycle Time
`
`0.5!-40
`
`3t-75
`
`1.5t-75
`
`t-65
`
`4t-70
`
`1.5!-80
`
`4t-260
`
`8.5!-120
`
`1.5t
`
`6t-290
`
`1.5t-90
`
`10.5t-250
`
`4t-200
`
`0.5t-30
`
`4.5t+ 100
`
`3t
`
`15t
`
`10
`
`200
`
`60
`
`25
`
`290
`
`50
`
`100
`
`0
`
`250
`
`40
`
`700
`
`160
`
`15
`
`270
`
`1.36
`
`650
`
`140
`
`5.0
`
`15.0
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`fLS
`
`NOTES:
`1. Control outputs: CL = 80 pF. BUS Outputs: CL = 150 pF.
`2. BUS High Impedance Load 20 pF
`3. f(t) assumes 50% duty cycle on X1, X2. Max clock period is for a 1 MHz crystal input.
`
`1-34
`
`I
`
`VIZIO, Inc. Exhibit 1021
`8 of 13
`
`

`
`WAVEFORMS
`
`INSTRUCTION FETCH FROM PROGRAM
`MEMORY
`
`READ FROM EXTERNAL DATA MEMORY
`
`270053-4
`
`270053-5
`
`WRITE TO EXTERNAL DATA MEMORY
`
`INPUT AND OUTPUT FOR A.C. TESTS
`
`~ ILAFCI :---
`r----1
`ALE_J ~ L
`f--•cct -j teAt 1---
`WR ----------~L____j
`I •ow f:::-±.j two
`
`ADDRESS
`
`2.4V~
`2 O-. TEST POINTS .-a.
`0.45V
`O.l,..
`'D.I
`
`270053-7
`A. C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for
`a logic "0". Output timing measurements are made at 2.0V for a
`logic "1" and O.BV for a logic "0".
`
`BUS F~
`
`FLOATING
`
`[ . .
`tAw---J
`
`270053-6
`
`PORT 1/PORT 2 TIMING
`
`'1ST CYCL_E I
`
`ALE
`
`r--IPL-1
`
`2ND
`CYCLE
`
`!I
`
`PIEN --+------''--,
`i I
`I
`I \~ ___ ____,I/'--:------~-------J-+-1--.-LP
`-j ~ILP
`,--~-----~lr--~----~r-----,
`I PCH
`PCH
`P~RT 20-23 DATA
`I
`NEW PORT ~ATA
`
`NEW P20-23 DATA
`
`P20-23
`OUTPUT
`
`OUTPUT
`
`EXPANDER
`PORT
`
`INPUT
`
`PCH
`
`PCH
`
`'I
`-------------:lr-tpp--j
`
`PROG
`
`270053-8
`
`1-35
`
`I
`
`VIZIO, Inc. Exhibit 1021
`9 of 13
`
`

`
`MCS®-48
`
`CRYSTAL OSCILLATOR MODE
`
`CERAMIC RESONATOR MODE
`
`1
`Cr
`------,-------,---=2'-l XTAL1
`
`_:-r." r J;::
`~ L.-
`
`In-:
`
`XTAL2
`
`3
`
`C3
`
`1
`
`Cl--------;r----2=-j XTAL1
`
`_r
`E1
`~ C"·-,~f
`
`C3
`
`XTALZ
`
`270053-10
`
`270053-9
`C1 ~ 5pF +'f.pF +(STRAY< 5pF)
`C2 ~ (CRYSTAL + STAY) < 8 pF
`C3 ~ 20 pF ± 1 pF + (STRAY < 5 pF)
`Crystal series resistance should be less than 300 at 11 MHz; less
`than 750 at 6 MHz; less than 18011 at 3.6 MHz.
`
`DRIVING FROM EXTERNAL SOURCE
`
`•SV
`
`270053-11
`For XT AL 1 and XTAL2 define "high" as voltages above 1.6V and
`"low" as voltages below 1.6V. The duty cycle requirements for
`externally driving XTAL 1 and XTAL2 using the circuits shown
`above are as follows: XTAL1 must be high 35-65% of the period
`and XTAL2 must be high 35-65% of the period. Rise and fall bmes
`must be faster than 20 ns.
`
`1-36
`
`I
`
`VIZIO, Inc. Exhibit 1021
`10 of 13
`
`

`
`PROGRAMMING AND VERIFYING THE
`P8749H/48H PROGRAMMABLE ROM
`
`Programming Verification
`
`In brief, the programming process consists of: acti(cid:173)
`vating the program mode, applying an address,
`latching the address, applying data, and applying a
`programming pulse. Each word is programmed com(cid:173)
`pletely before moving on to the next and is followed
`by a verification step. The following is a list of the
`pins used for programming and a description of their
`functions:
`
`Pin
`
`Function
`
`Clock Input (3 to 4.0 MHz)
`
`XTAL1
`XTAL2
`RESET
`TO
`EA
`BUS
`
`Initialization and Address Latching
`Selection of Program or Verifying Mode
`Activation of Program/Verify Modes
`Address and Data Input
`Data Output During Verify
`P20-P22 Address Input
`Programming Power Supply
`Voo
`PROG
`Program Pulse Input
`
`MCS®-48
`
`WARNING:
`
`An attempt to program a missocketed P8749H/48H
`will result in severe damage to the part. An indication
`of a properly socketed part is the appearance of the
`ALE clock output. The lack of this clock may be
`used to disable the programmer.
`
`The Program/Verify sequence is:
`1. Voo = 5V, Clock applied or internal oscillator
`operating, RESET = OV, TO = 5V, EA = 5V,
`BUS and PROG floating. P10 and P11 must be
`tied to ground.
`2. Insert P8749H/48H in programming socket
`3. TO = OV (select program mode)
`4. EA = 18V (activate program mode)
`5. Address applied to BUS and P20-22
`6. RESET = 5V (latch address)
`7. Data applied to BUS
`8. Voo = 21 V (programming power)
`9. PROG = Vee or float followed by one 50 ms
`pulse to 18V
`10. v00 = sv
`11. TO = 5V (verify mode)
`12. Read and verify data on BUS
`13. TO = OV
`14. RESET = OV and repeat from step 5
`15. Programmer should be at conditions of step 1
`when P8749H/48H is removed from socket.
`
`NOTE:
`Once programmed the P8749H/48H cannot be
`erased.
`
`l
`
`1-37
`
`VIZIO, Inc. Exhibit 1021
`11 of 13
`
`

`
`MCS®-48
`
`A.C. TIMING SPECIFICATION FOR PROGRAMMING P8748H/P8749H ONLY
`
`TA = 2s•c ±s•c; Vee= sv ±5%; Voo = 21 ±o.sv
`
`Symbol
`tAw
`twA
`tow
`two
`tpH
`tvoow
`tvooH
`tpw
`trw
`twT
`too
`tww
`tr,tt
`tev
`tRE
`
`Parameter
`Address Setup Time to RESET
`Address Hold Time After RESET
`Data in Setup Time to PROG
`Data in Hold Time After PROG
`RESET Hold Time to Verify
`V00 Hold Time Before PROG
`Voo Hold Time After PROG
`Program Pulse Width
`TO Setup Time for Program Mode
`TO Hold Time After Program Mode
`TO to Data Out Delay
`RESET Pulse Width to Latch Address
`Voo and PROG Rise and Fall Times
`CPU Operation Cycle Time
`RESET Setup Time before EA
`
`Min
`4tcv
`4tcy
`4tcv
`4tcy
`4tcv
`0
`0
`50
`4tcv
`4tcv
`
`4tcv
`0.5
`3.75
`4tcv
`
`NOTE:
`If Test 0 is high, too can be triggered by RESET.
`
`Max
`
`Unit
`
`Test Conditions
`
`1.0
`1.0
`60
`
`4tcv
`
`100
`5
`
`ms
`ms
`ms
`
`,...s
`,...s
`
`D.C. CHARACTERISTICS FOR PROGRAMMING P8748H/P8749H ONLY
`
`TA = 25•c ±5•c; Vee= sv ±5%; v 00 = 21 ±o.sv
`Parameter
`Symbol
`Voo Program Voltage High Level
`VooH
`Voo Voltage Low Level
`VooL
`PROG Program Voltage High Level
`VpH
`PROG Voltage Low Level
`__'!.PL
`EA Program or Verify Voltage High Level
`VEAH
`v00 High Voltage Supply Current
`loo
`PROG High Voltage Supply Current
`lpRQG
`EA High Voltage Supply Current
`lEA
`
`Min
`20.5
`4.75
`17.5
`4.0
`17.5
`
`Max
`21.5
`5.25
`18.5
`Vee
`18.5
`20.0
`1.0
`1.0
`
`Unit
`v
`v
`v
`v
`v
`rnA
`rnA
`rnA
`
`Test Conditions
`
`1-38
`
`I
`
`VIZIO, Inc. Exhibit 1021
`12 of 13
`
`

`
`SUGGESTED ROM VERIFICATION ALGORITHM FOR ROM DEVICE ONLY
`
`INITIAL ROM DUMP CYCLE
`
`SUBSEQUENT ROM DUMP CYCLES
`
`ALE
`(NOTE1)
`
`! (OUTPUT)
`
`MCS®-48
`
`EA __:]
`DB---i._ __ A-DD...,R:-E __ s.,..s_.JH ROM DATA H .. --A-:D::-D::R::-:E=ss:---'~~--------
`
`(INPUT)
`
`(OUTPUT)
`
`:(INPUT)
`
`(INPUT)
`
`(OUTPUT):
`
`RESET-------'
`
`p2~p23 -------1~----A-D_D_R_E_s_s ______ ~~
`
`ADDRESS
`
`A10
`A11
`
`SOH
`ADDR
`ADDR
`
`NOTE:
`ALE is function of X1, X2 inputs.
`
`1 (INPUT)
`I
`
`Vee~ Voo ~ +SV
`Vss ~ OV
`
`270053-12
`
`COMBINATION PROGRAM/VERIFY MODE (PROGRAMMABLE ROMS ONLY)
`
`~IREt
`
`t=rrw_
`
`tww--
`
`YEAH
`
`vee
`
`vee
`
`EA
`
`TO
`
`VtL1
`vee
`iiEiET
`
`LAST
`ADDRESS
`
`PROGRAM ---------lr--- VERIFY----i---- PROGRAM-
`
`--~ ~
`
`NEXT
`ADDRESS
`
`V~::--_··---------~-D_D_W~~-~-----------------------­
`~LJ~~twD
`PRO~PL-------------1-v- ~-.1_ _______ -------------·
`270053-13
`
`I
`
`1·39
`
`VIZIO, Inc. Exhibit 1021
`13 of 13