KINGSTON TECHNOLOGY COMPANY, INC. (Petitioner)
`v.
`POLARIS INNOVATIONS LTD. (Patent Owner)
`Oral Argument Demonstratives
`
`Case IPR2017‐00114
`Patent 7,206,978
`
`1
`
`KINGSTON 1021
`Kingston v. Polaris
`IPR2017-00114
`
`
`v.
`POLARIS INNOVATIONS LTD. (Patent Owner)
`Oral Argument Demonstratives
`
`Case IPR2017‐00114
`Patent 7,206,978
`
`1
`
`KINGSTON 1021
`Kingston v. Polaris
`IPR2017-00114
`
`
`
`Overview
`
`• Introduction to the Claimed Technology
`• Raynham‐Based Combinations Render Obvious
`All Instituted Claims (1, 6, 8–11, 13, & 14)
`• Humphrey‐Based Combinations Render Obvious
`All Relevant Instituted Claims (1, 6, 8–11, & 13)
`• PO’s Expert’s Opinions Are Based on Faulty
`Understanding and Use of POSITA
`
`2
`
`
`
`INTRODUCTION TO THE CLAIMED
`TECHNOLOGY
`
`INTRODUCTION TO THE CLAIMED
`
`TECHNOLOGY
`
`3
`
`
`
`The ’978 Patent is About Putting Well—Known Circuitry on a
`
`Memory Chip
`
`FIG 1
`(PRIOR ART)
`
`FIG 3
`
`302
`
`354
`
`302
`
`352
`
`-
`
`WEI—iii?!Eli—t
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`
`3‘ ”£=E=:==I=E'
`
`
`
`100
`
`iiiil
`ii
`
`1201211221
`
`14
`
`BUFFER OR
`
`WWW}?!
`
`lmlim
`iiiilEE
`
`Error detection units
`
`320 321 322323 324
`
`’978 Patent, Ex. 1001, Figs. 1 and 3
`
`See also Patent Owner Response, Paper 1 7 at 2
`
`
`
`Prosecution History: Overcoming the ”Phelps” § 102 Rejection
`
`1.
`
`(Currently Amended) A circuit module comprisingi
`
`a module board;
`
`a plm'ality ofcircuit [[chips]]—
`
`— -
`
`a main bus having a plurality of lines, branching into a plurality of sub-buses having a
`
`plurality of Iins, each of the sub-basses being connected to one of the plurality of circuit
`
`[EchiPSJJ M;
`
`wherein each circuit [[chip]] grit comprises an indication signal generating unit for
`
`providingan indication signal based on a combination of the signals received on the plurality of
`
`lines ofthe sub-bus connected to the respective circuit [[chip]] Em}, and an indication signal
`
`output for outputting the indication signal.
`
`In order to more clearly recite this distinction, claim I has been amended so that the term
`
`the term 'circuit chips. has been replaced by the term "circuit units.” The claim also very
`
`clearly recites that "each circuit unit consist[s] of a single integrated circuit memory chip." This
`
`amendment clarifies the original scope of the claim and is consistent with the application as
`
`
`
`RAYNHAM COMBINATIONS RENDER ALL
`
`INSTITUTED CLAIMS OBVIOUS
`
`References
`
`in Light of References
`
`Claims Obvious
`
`Raynham & Seyyedy
`
`1, 8, 10, 11, 13, 14
`
`Raynham & Seyyedy & Humphrey
`
`Raynham & Seyyedy & Admitted Prior Art
`
`Raynham & Seyyedy & Cromer
`
`6
`
`8
`
`9
`
`.
`Umted States Patent
`_
`
`[19]
`
`IIIIII||||||||||ll|l||||l|llllllillllllllllllll||||l||||||||||l||i|l||l||||
`U5005127014A
`in] Patent Number:
`[45] Date of Patent:
`
`5,127,014
`Jun.30, 1992
`
`[54]_ 4,945,517
`
`7/1990 Miyalake etal.
`
`365/2385
`
`
`
`
`
`
`Inventor: Michael Raynham, Los Gatos, Calif".
`[75]
`[73] Assignee: Hewlett-Packard Company, Palo
`Alto, Caiif.
`[2]] App]. No.: 479.781
`
`Primary Examiner—Charles E. Atkinson
`Attorney, Agent. or Firm—Roland l. Griffin; Alan H.
`Haggard
`
`[57]
`
`ABSTRACT
`
`
`Bcc use data and error cor-
`
`
`
`Ample Reason to Combine Raynham & Seyyedy
`
`Raynham, Ex. 1005
`
`Seyyedy, Ex. 1009
`
`7
`
`
`
`Ample Reason to Combine Raynham & Seyyedy
`
`° Raynham provides a reason
`
`It has also been recognized
`
`to improve the known prior
`art m SEWEdy
`
`Furthermore, in previous devices, memory access
`
`time is adversely affected by the— 0 Additional references show
`
`reason to combine
`
`Raynham, Ex. 1005 at 3:22-27
`
`2:36—37, 2:46—52; Ex. 1008, 2:17—27, 3:17—20; Ex. 1006, Abstract; Decl. of
`
`See also Ex. 1005, 3:22—27, 5:4—17, 7:14—16, 7:23—25, Figs. 3, 4; Ex. 1009,
`
`Dr. Subramanian, Ex. 1003 111] 49—52.
`
`”Each of these references further demonstrate that one of ordinary skill in
`
`the art would have found it obvious to combine Raynham’s technique, in
`
`which an ECC is included as a component of a DRAM chip and configured
`
`to provide a signal indicating an error state on a signal line that is output
`
`from the DRAM chip, into the RDIMM with multiple DRAM chips described
`
`
`
`by SEWGdY." Petition at 39-44
`
`
`
`Raynham and Seyyedy Render Claim 1 Obvious
`
`1. A circuit module comprising:
`a module board;
`a plurality of circuit units arranged on the module board, each circuit unit consisting of a
`single integrated circuit memory chip;
`a main bus having a plurality of lines, branching into a plurality of sub‐buses having a
`plurality of lines, each of the sub‐busses being connected to one of the plurality of circuit units;
`wherein each circuit unit comprises an indication signal generating unit for providing an
`indication signal based on a combination of the signals received on the plurality of lines of the
`sub‐bus connected to the respective circuit unit, and an indication signal output for outputting
`the indication signal.
`
`9
`
`
`
`The Main Dispute Is In Claim 1 (and 13)’s “wherein” Clause
`
`1. …
`wherein each circuit unit comprises
`an indication signal generating unit for
`providing an indication signal based on
`a combination of the signals received on
`the plurality of lines of the sub‐bus
`connected to the respective circuit unit,
`and an indication signal output for
`outputting the indication signal.
`
`10
`
`
`
`Patent Owner Adds Non-Existent Claim Limitations
`
`wherein each circuit unit com ris-
`p
`an indication signal generating u '
`for
`providing an indication signal‘based on
`
`
`and an indication signal output for
`
`a combination of the sinals received ~
`
`the plurality of lines of the sub-bus
`connected to the respective circuit unit,
`
`outputting the indication signal.
`
`where providing an indication
`
`signal must occur within a
`.
`.
`.
`.
`temporal limitation, I.e., before
`data is "stored in the memory
`chi "
`p
`
`- Patent Owner Response, Paper 1 7 at 44-45
`
`where signals received cannot
`include:
`1. “control signals,"
`
`2. signals “necessary for the
`
`logistics of the disclosed error
`correction operation"
`
`3. signals necessary for “any
`
`other plausible operation"
`
`- Patent Owner Response, Paper 1 7 at 51-52
`
`
`
`Raynham Provides an indication signal (42) based on
`a combination of the signals received (into 50)
`
`Raynham, Ex. 1005 at Fig. 3
`
`12
`
`
`
`Raynham Teaches How the Indication Signal Is Provided
`
`Raynham, Ex. 1005 at Fig. 4 & 7:3‐32
`
`13
`
`
`
`First, the 10‐bit Row Address Arrives On the Address Bus 62
`and the RAS Signal 58 is Asserted
`
`Raynham, Ex. 1005 at Fig. 4 & 7:3‐32
`
`14
`
`
`
`Then the Row Decoder 76 Enables the Chip and the ECC Signal
`is Asserted on Line 60
`
`Raynham, Ex. 1005 at Fig. 4 & 7:3‐32
`
`15
`
`
`
`After the WE Signal 54 is Asserted, ECC 92 “provides a signal
`indicating [error] state on signal line 42”
`
`Raynham, Ex. 1005 at Fig. 4 & 7:3‐32
`
`16
`
`
`
`The Dispute With Claim 14 is the “check signal”
`
`14. The memory unit according to
`claim 13, comprising a check
`signal input for receiving a
`check signal, and wherein said
`indication signal generating
`unit generates said indication
`signal based on a combination
`of the signals on the plurality
`of lines of the memory bus
`and the check signal, so that
`the indication signal
`represents an error signal.
`
`17
`
`
`
`Raynham Discloses a check Signal
`
`-
`
`u
`
`-
`
`n
`
`Petitioner’s Expert:
`
`a. The memory unit according to claim 13, comprising a
`
`check signal input for receiving a check signal,
`
`
`
`Petitioner’s ExPert:
`(DEPOSition)
`
`119. As described by Raynham. "a DRAM chip 52. usable in the DRAM memory
`
`array 50. receives. . .an error correction code (ECC) line 60 from the memory
`
`controller 22." Raynham. 5:16-21. fig. 4.
`
`Dr. Subramanian Dec/., Exhibit 1003 at 68
`
`Q. My question is; what is ECC? And if it helps,
`I can maybe help you. Column five, line 60, I believe.
`A. You said column five, line 60?
`
`Q. No. No. I'm sorry. Column seven, line ten,
`
`I think is the one.
`
`A. The ECC signal in figure three, which is the
`one I believe you're referring to-
`—as sent from the
`memory controller to the DRAM memory array in figure
`
`three.
`
`
`
`Patent Owner Again Adds Non-Existent Claim Limitations,
`
`Explicitly Limiting ”check signal”
`
`14. The memory unit according to
`
`claim 13, comprising a check
`
`where check signal :
`
`indication signal generating
`
`.
`.
`.
`sngnal Input for rec- .
`
`.
`
`g a
`
`check signalhand wherein said
`
`1. cannot initiate error correction
`
`2. cannot be a control signal
`3. must contain “check bits or
`parity bits”
`
`unit generates said indication
`
`- patent Owne, Response, pope, 17 at 54
`
`signal based on a combination
`
`of the signals on the plurality
`
`of lines of the memory bus
`
`and the check signal, so that
`
`the indication signal
`
`represents an error signal.
`
`
`
`Patent Owner’s ”check signa
`
`I” Is Incorrect and Unsupported
`
`
`
`Patent Owner’s Claim:
`
`Patent Owner’s Expert:
`
`While Petitioner has neglected to expressly explain what it understands a
`
`“check signal” to mean. a POSlTA would in fact tuiderstand “check signal" to be a
`
`“signal that contains check bits or parity bits.“ In other words. even wider BRI. a
`
`“check signal" cannot merely be a control and timing signal relating to the
`
`initiation or timing of error correction. Rather. it must contain substantive
`
`information used in the process of checking data for errors—hence. the name “check signal.” Ex. 2004 [Bernstein Declaration] M 112-114.
`Bernstein Decl, Ex. 2004 at par 114, page 63
`
`Patent Owner Response, Paper 1 7 at 54
`
`114. The broadest reasonable interpretation of the phrase “check signal” in
`
`light of the ’978 Patent specification is a signal that contains check bit(s) or parity
`
`bitm-
`
`
`
`HUMPHREY COMBINATIONS RENDER ALL
`
`RELEVANT INSTITUTED CLAIMS OBVIOUS
`
`Claims Obvious References
`
`in Light of References
`
`Humphrey alone
`
`1, 6, 8, 10, 11, 13
`
`Humphrey & Admitted Prior Art
`
`1, 6, 8, 10, 11, 13
`
`Humphrey & Cromer
`
`Humphrey & Cromer & Admitted Prior Art
`
`9
`
`9
`
`
`
`Ample Reason to Combine Humphrey & Admitted Prior Art
`
`
`
`Humphrey, Ex. 1008
`
`Admitted Prior Art, Ex. 1001
`
`FiG.|
`
`102
`
`102
`
`102
`
`MAP / MEMORY CONTROL
`ADDRESS
`DAT -
`“a
`
`~/
`
`100
`
`PROCESSOR
`
`SUBSYST EM
`
`
`DATAMEMORYEB
`WRITE
`
`MEMORY
`
`106
`
`120121122123124
`
`
`
`Ample Reason to Combine Humphrey & Admitted Prior Art
`
`° Humphrey provides reasons
`
`'
`
`toimpmvethelgys FAdmitted Prior Art
`
`the memory error resulting from'the erroneous operation command.
`Ex. 1003 111] 28—31, 44—47).
`
`See also Pet. 13-20 (citing Ex. 1008, Abstract,
`2:17—27, 4:7—8, 4:13—20, 7:23—34, Figs. 1, 2; Ex.
`
`F" example’ if—
`should result in producing a write command at the
`
`wrong time,
`
`the error system for detecting stuck bits
`
`in a data field would not give any protection against
`
`Humphrey, Ex. 1008 at 2:1 7-27
`
`' Additional references show
`further reasons to comblne
`
`1001, 1:11-38, 1:57-59, Figs. 1, 2; EX. 1005,
`
`Abstract; Ex. 1006; Decl. of Dr. Subramanian,
`
`
`
`Humphrey & Admitted Prior Art Render Claim 1 Obvious
`
`1. A circuit module comprising:
`a module board;
`a plurality of circuit units arranged on the module board, each circuit unit consisting of a
`single integrated circuit memory chip;
`a main bus having a plurality of lines, branching into a plurality of sub‐buses having a
`plurality of lines, each of the sub‐busses being connected to one of the plurality of circuit units;
`wherein each circuit unit comprises an indication signal generating unit for providing an
`indication signal based on a combination of the signals received on the plurality of lines of the
`sub‐bus connected to the respective circuit unit, and an indication signal output for outputting
`the indication signal.
`
`24
`
`
`
`The Dispute Is In Claim 1 (and 13)’s “wherein” Clause
`
`1. …
`wherein each circuit unit comprises
`an indication signal generating unit for
`providing an indication signal based on
`a combination of the signals received on
`the plurality of lines of the sub‐bus
`connected to the respective circuit unit,
`and an indication signal output for
`outputting the indication signal.
`
`Patent Owner takes a narrow view
`of Humphrey’s “memory module”
`to argue that Humphrey does not
`render this element obvious
`
`25
`
`
`
`Humphrey
`
`I
`
`Chips
`
`5 ”Memory Module” Is Not Required to Be Multiple
`
` °
`
`Petitioner’s expert testified that
`
`Humphrey’s memory module was not
`
`constrained in implementation, and
`
`could be implemented in a chip.
`
`
`
`
`THE WITNESS:
`
`
`
`
`
`
`Petitioner’s Expert Deposition, Ex. 2007 at 46:4-13
`
`ME
`E MORY SYSTEM
`RRDR ENCODER
`
`I7
`‘ ““3“ 095 mum
`cnecx
`
`PROCESSOR
`SUESYST cu
`
`
`
`
`
`<I-
`a:
`E‘é'
`
`
`
`
`
`
`
`READ DATA BUS
`
`22
`
`45
`WRITE DATA BUS
`
`22
`
`
` CONTROL BUS
`TIMING 3
`
`
`CONTROL LOGIC
`3 -
`
`
`
`
`
`
`22 DATA en's
`
`
`ADDRESS
`
`OUTPUT LATCH
`
`SEMICO NWCTOR
`
`
`STORAGE ARRAY
` PHYSICAL
`
`256K WORDS
`ADDRESS BUS
`
`X 22 BITS
`
`OPERATION
`STATE BUS
` OPERATION
`
`STATE
`
`MACHINE
` 6|
`
`
`57
`
`
`
`
`
`PO Uses Artificially Narrow Definition of ”Memory Module”
`
`Patent Owner’s expert acknowledged
`
`-
`
`that there were broader definitions of
`
`"memory module” than what he had
`used to interpret Humphrey.
`
`MR. LOWENSTEIN: Objection; the document
`Speaks t“ “5‘?”
`,
`THE WITNESS: I've never seen this
`
`definition before, and I don't know the context of
`
`COMPREHENSIVE
`DICTIONARY
`
`which he's putting this in.
`I understand that memory module is used even
`for the little SD. You probably have one in your
`cell hone, at least one.
`I have one in m hone.
`
`g muffin; memory module
`
`up? ( in may
`
`<4)» IEEE pness
`
`a physical component used
`in the implementation of a memory. See also
`memory bank. interleaved memory.
`
`
`
`PO’s Extrinsic Evidence Argument Focusing at the Time of
`Humphrey Both Fails and Misses the Point
`
`•
`
`•
`
`•
`
`Patent Owner (relying on its expert) claims that “the technology at the time of
`Humphrey prevented the logic required for the operation state machine 61 to be
`manufactured on a DRAM chip.”
`Patent Owner (relying on an article) claims that Humphrey’s DRAM could not fit
`on a chip.
`Patent Owner (relying on a Wikipedia page) claims that Humphrey’s memory
`module was found in a commercial product that was not on a chip.
`Patent Owner Response, Paper 17 at 23‐25.
`
`• Patent Owner’s claims are wrong.
`
`•
`
`See Petitioner’s Reply, Paper 21 at 21.
`Focus on time of Humphrey misses the point. Proper focus on what a POSITA
`would understand about Humphrey’s teachings at the time of the ‘978 Patent.
`
`28
`
`
`
`The Dispute Is In Claim 1 (and 13)’s “wherein” Clause
`
`1. …
`wherein each circuit unit comprises
`an indication signal generating unit for
`providing an indication signal based on
`a combination of the signals received on
`the plurality of lines of the sub‐bus
`connected to the respective circuit unit,
`and an indication signal output for
`outputting the indication signal.
`
`Patent Owner claims that that
`there is no combination of
`signals in Humphrey
`
`Paper 17 at 38‐39
`
`29
`
`
`
`Humphrey Discloses Providing an Indication Signal Based on
`a Combination of the Signals Received
`
`Humphrey, Ex. 1008 at Fig. 2
`
`30
`
`
`
`PO'S EXPERT’S OPINIONS RELY ON FAULTY
`
`DEFINITION AND USE OF POSITA
`
`
`
`PO’s Expert’s Analysis Was Not Based on the Proper
`
`Definition of a POSITA
`
`°
`
`In Opining '978 was not
`obvious Patent Owner's
`I
`
`Expert dld nOt presume that a
`POSITA had read, understood,
`and remembered the prior
`art, let alone prior art of
`record.
`
`,
`° Patent Owner 5 expert
`rejected ”technology that's in
`
`resea rch a nd development”
`Rep/y, Paper 21 at 8 "-7 (collecting cites}
`
`° Patent Owner’s expert
`
`repeatedly conflated “his”
`
`definition with Petitioner’5
`
`definition of POSITA
`
`Reply, Paper 21 at 8 n.7 (collecting cites)
`
`Q. Do the opinions that you've given in your
`declaration and today about what a POSITA would know
`or believe at the time of the '978 patent invention
`assume that a POSITA would have read Exhibits 1010,
`1011, 1006, 1007?
`
`A-
`
`I know that there are certain 1e a1
`standards, and
`
`301
`
`don’t have an exact database for what I would have
`
`
`ex ected the POSITA to have read or not read.
`
`
`Excuse me.
`
`Patent Owner’s Expert’s Deposition, Ex. 1020 at 238:6-239:3
`
`
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