`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`KINGSTON TECHNOLOGY COMPANY INC.,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LTD.,
`Patent Owner.
`____________
`
`Case IPR2017-00114
`Patent 7,206,978
`____________
`
`EXHIBIT 2004
`DECLARATION OF PROF. JOSEPH BERNSTEIN, PH.D.
`
`
`
`
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`TABLE OF CONTENTS
`
`Page
`INTRODUCTION ..................................................................................... 1
`
`I.
`
`II. QUALIFICATIONS .................................................................................. 1
`
`III. BASES OF OPINIONS. ............................................................................10
`
`IV. APPLICABLE LEGAL STANDARDS. ..................................................11
`
`A. Ordinary Skill In The Art. ................................................................. 11
`
`B.
`
`C.
`
`Claim Construction. .......................................................................... 15
`
`Obviousness (35 U.S.C. § 103). ........................................................ 15
`
`V.
`
`BACKGROUND OF THE ’978 PATENT. ..............................................17
`
`VI. HUMPHREY, ALONE OR IN COMBINATION WITH THE
`ADMITTED PRIOR ART DOES NOT RENDER THE CLAIMS
`OBVIOUS. .................................................................................................22
`
`A.
`
`B.
`
`Background Of Humphrey. ............................................................... 22
`
`Humphrey, Alone Or In Combination With Admitted Prior Art,
`Does Not Disclose Claims 1 And 13. ................................................ 28
`
`1.
`
`2.
`
`Humphrey Does Not Disclose An “Indication Signal
`Generating Unit” On A Chip. ................................................. 28
`
`Humphrey Does Not Disclose That The Control Bus 39 And
`Address Bus 33 Are Combined In Humphrey’s Timing And
`Control Logic 59. ................................................................... 44
`
`VII. RAYNHAM, ALONE OR IN COMBINATION WITH THE
`ADMITTED PRIOR ART DOES NOT RENDER THE CLAIMS
`OBVIOUS. .................................................................................................50
`
`A. Unlike The ’978 Patent, Raynham Detects Errors For Data Already
`Stored On The Chip. ......................................................................... 50
`
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`B.
`
`C.
`
`Raynham, Alone Or In Combination With Seyyedy, Does Not
`Render Obvious Claims 1 And 13. .................................................... 53
`
`Raynham, Alone Or In Combination With Seyyedy, Does Not
`Render Claim 14 Obvious. ................................................................ 60
`
`VIII. CONCLUSION .........................................................................................65
`
`
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`I.
`
`INTRODUCTION
`
`1. My name is Joseph Bernstein. I have been retained as an expert
`
`witness to provide my independent opinion in regard to matters at issue in inter
`
`partes review of U.S. 7,206,978 (“the ’978 Patent”), proceeding No. IPR2017-
`
`00114. I have been retained by Polaris Innovations Ltd. (“Polaris”), the Patent
`
`Owner in the above proceedings. The Petitioner in this case is Kingston
`
`Technology Company, Inc. (“Kingston”).
`
`2.
`
`Unless otherwise noted, the statements made herein are based on my
`
`personal knowledge and if called to testify about this declaration I could and would
`
`do so competently and truthfully.
`
`3.
`
`A detailed record of my professional qualifications, including a list of
`
`patents, publications, other professional activities, and relevant industry experience
`
`is attached to this Declaration as Exhibit A and is summarized in Section II below.
`
`4.
`
`I am not a legal expert and offer no opinions on the law. However, I
`
`have been informed by counsel of the various legal standards that apply, and I have
`
`applied those standards in arriving at my conclusions.
`
`II.
`
`QUALIFICATIONS
`
`5.
`
`I earned a Master of Science degree in Electrical Engineering and
`
`Computer science in 1986, an Electrical Engineering degree in 1987, and a Doctor
`
`of Philosophy in Electrical Engineering and Computer Science in 1990 from
`
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`Massachusetts Institute of Technology (MIT). Prior to attending MIT, I graduated
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`Summa Cum Laude from the Union College in Schenectady, NY with a Bachelor
`
`of Science degree in Electrical Engineering in 1984.
`
`6.
`
`After earning my Ph.D., I worked at MIT Lincoln Laboratory as a
`
`senior research staff member, during which time I taught at Boston University as
`
`an Adjunct Professor.
`
`7.
`
`From 1995 to 2007, I was first an Assistant and then Associate
`
`Professor of engineering at University of Maryland. I was also the chief scientist
`
`and co-founder of Lightspeed Semiconductor, a silicon-valley company that
`
`commercialized a patent of mine from MIT relating to high performance, metal-
`
`configurable gate arrays. I was involved in every aspect of chip design and layout
`
`as we were implementing technology that I had developed as the sole inventor,
`
`thus I became quite familiar with all aspects of logic and memory design and
`
`layout.
`
`8. While at the University of Maryland, I taught in the Reliability
`
`program as the specialist in microelectronics device reliability. In the summer of
`
`1998, I joined the Jet Propulsion Laboratories as a NASA Summer Faculty
`
`Research Fellow. I was promoted from Assistant to Associate Professor with
`
`tenure in 2001. From 2003 to 2005, I was a Professor of engineering at Tel-Aviv
`
`University on Sabbatical from University of Maryland.
`
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`9.
`
`During my tenure at Maryland, I had many programs also sponsored
`
`at the National Institute of Standards and Technology (NIST), where I worked
`
`directly with the semiconductor industry by means of the connection with NIST. I
`
`had Ph.D. students constantly in the laboratory at NIST as I supervised many
`
`doctoral dissertations from work in the Semiconductor Electronics branch at NIST.
`
`This group acted as a government liaison with semiconductor manufacturing
`
`companies and often was the center for JEDEC roundtables and committee groups
`
`focused on reliability and standards for the semiconductor industry. Specifically,
`
`we focused on the gate oxide integrity, gate and metallization features and other
`
`aspects that affect the reliability of newly developed semiconductor technology.
`
`10. Currently, I participate with the European standards organization,
`
`FIDES, to develop updated reliability protocols and methodologies for reliability
`
`assurance in microelectronic systems for avionics and for space applications.
`
`11.
`
`I am currently employed at Ariel University in Ariel, Israel. At Ariel,
`
`a focus of my research is on issues related to chip reliability, including links
`
`between reliability and power and thermal behavior. At Ariel, I focus on the
`
`packaged devices at the board level. We look at the functionality and performance
`
`of the system level boards, including FPGA’s embedded with DRAM and Flash
`
`memory. We look at all the failure mechanisms that can affect the reliability of the
`
`cards and model these mechanisms in order to derive a complete reliability
`
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`prediction methodology. Through this work, I have several consulting clients who
`
`apply my methodology, including SanDisk, Marvell as well as system level
`
`customers including Thales Aerospace (France) and various smaller companies.
`
`12.
`
`I have published numerous papers, including five books and more
`
`than 60 refereed publications, a more complete list of which is included in Exhibit
`
`A. Most of my publications are in the area of microelectronics reliability and
`
`interconnects. In addition to my publications, I have given numerous tutorials,
`
`talks, presentations, and lectures, in both academic and corporate settings, on
`
`reliability of semiconductor devices.
`
`13. My work in microelectronics reliability has been the subject of awards
`
`or other industry or academic recognition on many occasions, including the
`
`following:
`
`-
`
`-
`
`-
`
`In 2014, I was awarded the best paper/lecturer award by ChipEx 2014;
`
`In 2004-2005, I was a Fulbright Senior Researcher;
`
`In 2003, I was an IEEE Senior Member.
`
`14.
`
`I had been affiliated with the Reliability Program of the Mechanical
`
`Engineering Department, the Electrical and Computer Engineering Department,
`
`and the Institute for Research in Electronics and Applied Physics at the University
`
`of Maryland. I was also affiliated with the Nano-Science and Nano-Technology
`
`Center at Tel-Aviv University, which I headed during my Sabbatical there.
`
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`15.
`
`I have also served as the Founder and Faculty advisor for the Israel
`
`Electronics Manufacturers Working Group on Reliability (ILTAM), and I lead the
`
`Laboratory for Reliable Electronics Systems at Ariel University.
`
`16.
`
`I currently supervise two Ph.D. candidates. I have served as the
`
`advisor or co-advisor for nineteen Ph.D. graduates in electrical and electronic
`
`engineering, many of whom graduated in the materials and mechanical engineering
`
`departments through the Reliability Program at University of Maryland.
`
`17.
`
`I teach classes at Ariel University that include Undergraduate and
`
`Graduate courses in Electrical Engineering. Some courses I have taught include
`
`VLSI Design, Reliability Engineering Fundamentals, Microelectronics Device
`
`Reliability, Advanced Reliability Engineering, and Quality Engineering
`
`Fundamentals. I also teach two VLSI laboratories where we instruct the students
`
`in design and layout of analog circuits as well as a complete memory system. I
`
`instruct the students how to make the complete memory design, including the bus
`
`structure, architecture, registers and silicon layout. I have also developed
`
`coursework and curriculum on Reliability Engineering and Electronic Device
`
`Reliability. In my laboratory, my students are taught to develop reliability testing
`
`plans to evaluate the underlying technology using commercially built circuits
`
`including FPGAs and embedded DRAM as well as FLASH and Analog chips and
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`microcontrollers. I have authored numerous books, manuals, and teaching
`
`materials on reliability in electronics. My course material includes:
`
`- Bernstein, J.B., “Fundamentals of Failure,” teaching manual reliability.
`
`Departmental Brochure, “Microelectronics Reliability Engineering.”
`
`18. Some of my research papers include:
`
`- Hoang, H.H., Schutz, R., Bernstein, J.B., Vasquez, B., Multi-level
`
`Interconnection: Issues that Impact Competitiveness, Proceedings of
`
`SPIE 2090, 1993.
`
`- L. Yang, J.B. Bernstein, “Reliability Study of High-Density EBGA
`
`Packages Using the Cu Metalized Silicon,” IEEE Transaction on
`
`Components and Packaging Technology, vol. 31, no. 3, pp. 702-11
`
`(2008).
`
`- Joseph B. Bernstein, Moshe Gurfinkel, Xiaojun Li, Jörg Walters, Yoram
`
`Shapira and Michael Talmor, Electronic circuit reliability modeling,
`
`Microelectronics Reliability, vol. 46, pp. 1957- 1979 (2006).
`
`- X. Li, J. Qin, B. Huang, X. Zhang, and J.B. Bernstein, SRAM Circuit
`
`Failure Modeling and Reliability Simulation with SPICE, IEEE Trans. on
`
`Device and Mat. Rel., vol. 6, no. 2, pp.235-246 (2006).
`
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`- L.-S. Yang and J.B. Bernstein, “Encapsulation Process Development for
`
`Flexible-Circuit Based Chip Scale Packages,” IEEE Trans. Electronics
`
`Packaging Manufacturing, vol. 25, no. 4, pp. 344-354 (October 2002).
`
`- L.-S. Yang, J.B. Bernstein and K.C. Leong, “Effect of the Plasma
`
`Cleaning Process on Plastic Ball Grid Array Package Assembly
`
`Reliability,” IEEE Trans. Electronics Packaging Manufacturing, vol. 25,
`
`no. 2, pp. 91-99 (April 2002).
`
`19. Some of my conference presentations include:
`
`- J. Qin, M. White, J.B. Bernstein, “A Study of Scaling Effect on DRAM
`
`Reliability,” Annual Reliability and Maintainability Symposium
`
`(RAMS), Final Report, pp. 9C-4 (January 2011).
`
`- B. Yan, J. Qin, J. Dai, Q. Fan, J.B. Bernstein, “Reliability Simulation and
`
`Design Consideration of High Speed ADC Circuits.” International
`
`Integrated Reliability Workshop (IIRW) Final Report, pp. 125-128
`
`(October 2008)
`
`- J. Qin, X. Li, J.B. Bernstein, “SRAM Stability Analysis Considering
`
`Gate Oxide SBD, NBTI and HCI,” 2007 International Integrated
`
`Reliability Workshop (IIRW) Final Report, 2.2, (October 2007)
`
`- Y. Chen, D. Nguyen, S. Guertin, J.B. Bernstein, M. White, R. Menke, S.
`
`Kayali, “A Reliability Evaluation Methodology for Memory Chips for
`
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`Space Applications when Sample Size is Small,” Proceedings of
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`Integrated Reliability Workshop, Lake Tahoe (Nevada 2003).
`
`- Murguia, J.E., Bernstein, J.B., “Short-time failure of metal interconnect
`
`caused by current pulses,” IEEE Electron Device Letters, vol. 14, no. 10,
`
`pp. 481-3 (1993).
`
`20.
`
`I am a named inventor on at least six U.S. utility patents, most of
`
`which are directed to electrical interconnections. These patents relate to the field
`
`of repairable systems. These relate to redundancy in DRAM and SRAM devices
`
`and relates to the well-known procedure of testing and replacing defective cells,
`
`columns and rows of memory on the chip level. My publication in 1993, with Jim
`
`Murguia as my co-author, became the basis for the common “e-fuse” technology
`
`that is ubiquitous today in the memory industry for repairing defective cells.
`
`21.
`
`In my professional experience, I have become familiar with the many
`
`problems faced by electrical engineers when designing printed circuit boards,
`
`including those that include memory modules. My research group has direct
`
`experience analyzing reliability of interconnections in printed circuit board
`
`designs. We deal with most of the issues that affect reliability and data integrity. I
`
`have helped a commercial client with interface issues dealing with communication
`
`from the chip to the board and the problems associated with timing, capacitance
`
`and inductance of the matching network between the chip and the board. Many
`
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`issues that I research are directly related to memory module design have direct
`
`connections to the reliability challenges that I have explored in my own research
`
`since the ’978 Patent fall in the category of Microelectronics Reliability, a subset
`
`of which is signal and data integrity.
`
`22. Furthermore, I was a computer hardware hobbyist going back to my
`
`early days and into high school from the later 1970’s. I will describe later, with
`
`reference to the Humphrey patent, that my personal experience as a back-room
`
`computer store technician gives me first hand experience soldering and repairing
`
`computer module boards that supported early Intel 8080 and 8086 processors and
`
`comparable technology.
`
`23.
`
`I have previously served as a testifying expert in litigation in five
`
`district court cases. I have also previously served as an expert in matters at the
`
`Patent Trial and Appeals Board, including Inter-Partes Reviews and Patent Re-
`
`examinations.
`
`24.
`
`I have also served as a technical consultant for electronics and
`
`computer systems companies on issues including testing and reliability. Some
`
`companies I have consulted on behalf of include Sandisk, Marvell Corp., Cypress
`
`Semiconductor, Teradyne Corporation, and Freescale Semiconductor.
`
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`III.
`
`BASES OF OPINIONS.
`
`25.
`
`In the course of conducting my analysis and forming my opinions, I
`
`have reviewed at least the materials listed below:
`
`i.
`
`ii.
`
`U.S. Patent No. 7,206,978 and its prosecution history;
`
`Petition by Kingston Technologies Company, Inc.;
`
`iii. Declaration of Vivek Subramanian;
`
`iv.
`
`v.
`
`Patent Owner’s Preliminary Response to the Petition;
`
`Institution Decision by the P.T.A.B.;
`
`vi. Deposition transcript of Vivek Subramanian;
`
`vii. European Patent Application Publication 0084460 A2 (“Humphrey”);
`
`viii. U.S. Pat. No. 5,127,014 (“Raynham”);
`
`ix.
`
`x.
`
`European Patent EP 1029326 B1 (“Cromer”);
`
`U.S. Patent No. 6,282,689 (“Seyyedy”);
`
`xi. Various publications and research regarding DRAM and other
`
`memory manufacture, sizes and architecture.
`
`26.
`
`In the course of conducting my analysis, I have also relied on my
`
`nearly three decades of experience at the forefront of research and application of
`
`memory design technology.
`
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`IV.
`
`APPLICABLE LEGAL STANDARDS.
`
`A. Ordinary Skill In The Art.
`
`27. My opinions in this declaration, including opinions on validity and
`
`claim construction, are based on the understandings of a person of ordinary skill in
`
`the art (which I understand is sometimes referred to by the acronyms “POSITA” or
`
`“PHOSITA”) at the time of the effective filing date of the patent application
`
`resulting in the Patent (May 28, 2003).
`
`28.
`
`I understand that factual indicators of the level of ordinary skill in the
`
`art include the various prior art approaches employed, the types of problems
`
`encountered in the art, the rapidity with which innovations are made, the
`
`sophistication of the technology involved, and the educational background of those
`
`actively working in the field. I understand that, in assessing the level of skill of a
`
`person of ordinary skill in the art, one should consider the type of problems
`
`encountered in the art, the prior solutions to those problems found in the prior art
`
`references, the rapidity with which innovations are made, the sophistication of the
`
`technology, the level of education of active workers in the field, and my own
`
`experience working with those of skill in the art at the time of the invention.
`
`29.
`
`In this case, Dr. Subramanian has asserted in his declaration that a
`
`person of ordinary skill in the art as of the time of the ʼ978 Patent would have a
`
`Master’s degree in Electrical Engineering and at least two years of experience
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`working in the field of semiconductor memory design. Ex. 1003 [Subramanian
`
`Declaration] ¶¶ 17-19. In my opinion, this is not a reasonable statement of the
`
`level of ordinary skill of the art for this patent and claims. It is too high. Based on
`
`my review of the ’978 Patent, its claims challenged here, and the references cited
`
`by Dr. Subramanian and Petitioner, in my opinion the hypothetical person of
`
`ordinary skill in the art of the patent and claims would have had a bachelor’s
`
`degree in Electrical Engineering or the equivalent. (I note that Dr. Subramanian’s
`
`declaration does not include any explanation or basis for selecting the particular
`
`level of skill he set forth, as opposed to, say, a lower level, and, in particular, I do
`
`not see, and he does not offer, any basis for his statement that a person of ordinary
`
`skill in the art would have a master’s degree in Electrical Engineering.). In my
`
`experience, at the time of the effective filing date of the patent (mid 2003), people
`
`working in the semiconductor memory design industry were more likely to have
`
`bachelor’s degrees than to have a master’s or higher degrees. I am not aware of
`
`any basis for Dr. Subramanian’s contrary conclusion, and he does not offer any
`
`reason for his conclusion.
`
`30.
`
`I was at the time of invention, and am, one of more than ordinary skill
`
`in the art through my education and work experience. Indeed, I am very familiar
`
`with people having this level of skill. For more than two decades, I have been
`
`teaching undergraduate and graduate level courses. I have supervised many
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`doctoral theses in my career as a Professor in Electrical and Electronic
`
`Engineering. I also supervised students in materials and in mechanical engineering
`
`so I am quite familiar with combining remote disciplines for achieving originality
`
`and patents. I am also familiar with the level of typical graduates in Electrical
`
`Engineering disciplines and how much experience is acquired over the course of
`
`only two to five years of practical work in the field.
`
`31.
`
`I note that, in addition to providing no specifics about why he believes
`
`his preferred level of ordinary skill would be the correct one, Dr. Subramanian
`
`makes many broad assertions relating to the level of ordinary skill of the art with
`
`which I do not agree. For example, he asserts in his declaration that “before the
`
`time of the ’978 Patent, semiconductor and device manufacturing technologies had
`
`evolved to such an extent that one of ordinary skill would understand that absent a
`
`specific technical limitation, memory and support circuitry could be
`
`fabricated/packaged on a single chip and multiple chips can be assembled onto one
`
`or multiple circuit boards depending on the desired application to achieve a
`
`particular cost, size, or manufacturing goal. These matters were simply design
`
`choices for an engineer and had long since ceased to be technical obstructions.”
`
`Ex. 1003 ¶ 19. In my opinion, this statement by Dr. Subramanian is not correct. It
`
`is far too broad.
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`32. As I noted in ¶¶ 28-30, supra, the “ordinary” person working in
`
`semiconductor memory design would not have had experience designing chips at
`
`all, except at most, the design of small standard memory chips as exemplified in
`
`the undergraduate VLSI lab that I teach. Moreover, such an ordinary artisan would
`
`not have understood that there “ceased to be technical obstructions” for any
`
`“particular cost, size, or manufacturing goal” to be achieved by fabricating or
`
`packaging any memory or support circuitry “onto one or multiple circuit boards
`
`depending on the desired application,” because that is not true, even today, and
`
`certainly was not true in 2003. The fabrication of integrated circuits is a complex
`
`technology. So is packaging. So is the fabrication and design of memory modules.
`
`It is well-known that billions of dollars are spent, and many patents are filed, to
`
`this day on ways that semiconductor memory modules and chips are designed so as
`
`to solve technical challenges based, in part, on how “memory and support
`
`circuitry” are “fabricated” or “packaged” on a single chip, or how multiple chips
`
`are assembled onto one or more circuit boards. Whether there are challenges or
`
`limitations, or unexpected benefits or problems, to doing these things depends on
`
`many things, including the particular application, whether ongoing changes in the
`
`rapidly changing fields of computer technology have created new challenges (such
`
`as by increasing the number of memories needed or the speed of throughput
`
`necessary, for example), and many other factors.
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`33.
`
`I note that even if I take Dr. Subramanian’s statement of the level of
`
`ordinary skill at the outset of his analysis as correct, my opinions set forth in this
`
`declaration would remain the same unless otherwise stated.
`
`B. Claim Construction.
`
`34.
`
`I understand that claims in a patent-at-issue in an IPR are generally
`
`interpreted according to their broadest reasonable interpretation in light of the
`
`specification of the patent in which they appear. Under the broadest reasonable
`
`interpretation, I understand that claim terms are presumed to have their plain
`
`meaning unless the meaning is inconsistent with the patent specification or the
`
`patent’s prosecution history.
`
`35.
`
`In addition to the Patent specification, I understand that prosecution
`
`history should also be consulted in construing the meaning of the claims.
`
`36. Claim terms are interpreted as they would have been interpreted by a
`
`person of ordinary skill in the art at the time of the invention. The understanding
`
`of the person of ordinary skill in the art regarding various claim terms are
`
`discussed throughout this declaration as they come up.
`
`C. Obviousness (35 U.S.C. § 103).
`
`37.
`
`I have been informed that a patent may be invalid if the claimed
`
`invention would have been obvious at the time the invention was made to a person
`
`having ordinary skill in the art. I have been informed that the following factors
`
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`must be evaluated to determine whether Petitioner has met its burden of proof that
`
`a claimed invention is obvious:
`
` the scope and content of the prior art relied upon by Petitioner;
`
` the difference or differences, if any, between each claim of the patent and
`
`the prior art;
`
` the level of ordinary skill in the art at the time the invention of the patent
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`was made; and
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` any objective indicia of non-obviousness, including : (1) commercial
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`success of an embodiment; (2) a long-felt need; (3) skepticism; (4) failure
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`by others to find the solution provided by the claimed invention; (5)
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`copying by others of the subject matter of the claim invention;
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`(6) unexpected results of the claimed invention; (7) acceptance of others
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`and industry praise; and (8) licensing of the patents.
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`38.
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`I have been informed that a claim is not proved obvious merely by
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`demonstrating that each of the elements was independently known in the prior art.
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`I have been informed that many, if not all, inventions rely on building blocks long
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`since uncovered, and claimed discoveries almost of necessity will likely be
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`combinations of what is already known. I have been informed that it is important
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`to identify whether a reason existed at the time of the invention that would have
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`prompted a person of ordinary skill in the art in the relevant field to combine the
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`known elements in the way the claimed invention does. In addition, I have been
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`informed that a person of ordinary skill in the art should have had a reasonable
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`expectation of success in combining the teachings of the references.
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`39.
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` In assessing obviousness, I have been instructed to consider the
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`distortion caused by hindsight bias, guard against slipping into the use of hindsight,
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`be cautious of arguments that rely upon after-the-fact reasoning, and avoid the
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`temptation to read into the prior art the teachings of the invention at issue.
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`V.
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`BACKGROUND OF THE ’978 PATENT.
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`40. The ’978 Patent specification is focused on detecting errors that occur
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`on address/command signals that are sent to the system’s memory device(s). Ex.
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`1001 [’978 Pat.] at, e.g., 1:25-33; 3:25-29. The errors include any corruption in the
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`command/address signals while those signals are in transit from the host system
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`(e.g., computer’s memory controller) to the memory device.
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`41. An important aspect of the improvement of the ’978 Patent as
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`compared to the prior art prior to the Patent’s invention is that the error detection
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`circuitry for address/command signals is placed within each memory chip, as
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`opposed to simply providing a single parity error detection circuitry for all memory
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`chips on the module. Id. at 3:25-45; comp. Fig. 1 with Fig. 3.
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`42. As the ’978 Patent explains, this moving of the error detection and
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`alert circuitry from the module to within the memory chips was because the
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`inventors of the ’978 Patent recognized that with advancing technology, errors on
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`the sub-buses of the module become sufficiently important to warrant the said
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`improvement to the prior art:
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`The present invention is based on the finding that in new generations
`of memory systems that provide high data rates, errors that happen on
`a command/address bus on a memory module become significant for
`the error rate of the whole system.
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`Ex. 1001 [The ’978 Pat.] at 3:25-29.
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`43. The ’978 Patent schematically shows its recognition of the importance
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`of sub-bus errors by demonstrating the complexity of the sub-buses 216 in its
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`Figure 2, reproduced below::
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`Id. at Fig. 2; see also, 2:63-67 (“This high number of sub-buses 216 is not
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`protected by the error detection circuit elements that are embedded in the registers
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`
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`210 [of the prior art]. Thus, as outlined above, errors that occur on
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`command/address lines of the sub-busses 216 cannot be detected according to this
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`prior art approach.”); 3:65-4:4 (“The inventive approach of error detection allows
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`to detect errors occurred on the command/address bus between a memory
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`controller and each of the memory chips (DRAMs, for example) on the memory
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`modules.”).
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`44. The inventors of the ’978 Patent also recognized numerous other
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`benefits of their invented system. For example, the system disclosed by the ’978
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`Patent permits memory address/command error detection even for unregistered
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`modules. This is because the address/command signal error detection and alert
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`circuitry would have generally been placed in the module’s command and register
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`circuitry since this is where the commands are interpreted and then sent to the
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`chips. See also, id. at 3:60-65.
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`45. Furthermore, the memory system disclosed by the ’978 Patent permits
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`error signals that are individualized to a particular chip or group of chips, thereby
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`providing the memory controller with detailed information about the location an
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`error may have occurred. Id. at 4:5-13.
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`46. During prosecution of the application that resulted in the issuance of
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`the ’978 Patent, the applicant also clearly distinguished its invention, which
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`provided for address/command error detection within the individual memory chips,
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`from the prior art systems that provided error detection circuitry on the module,
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`servicing all of the chips on that module:
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`Claim 1, as originally filed, specifically recited that “each
`circuit chip comprises an indication signal generating unit for
`providing an indication signal based on a combination of the signals
`received on the plurality of lines of the sub-bus connected to the
`respective circuit chip, and an indication signal output for outputting
`the indication signal.” Phelps does not teach or suggest such a circuit
`chip.
`
`In rejecting the claim, the Examiner correctly stated that the
`claims subject to examination must be given their broadest reasonable
`interpretation consistent with the specification. In this particular case,
`the question is whether the term “circuit chip” is broad enough to
`encompass a “module” as taught by Phelps. Applicants respectfully
`submit that one of ordinary skill in the art understands that a “chip” is
`not the same as a module (and that a DIMM chip is not the same as a
`memory chip).
`
`In order to more clearly recite this distinction, claim 1 has b