BRANDON FERNALD
`Brandon.fernald@fernaldlawgroup.com
`FERNALD LAW GROUP LLP
`A REGISTERED LIMITED LIABILITY PARTNERSHIP
`510 W 6th Street, Suite 700
`Los Angeles, California 90014
`T:323.410.0320 | F:323.410.0330 | C:323.842.7473
`
`DAVID A. SKEELS
`skeels@fsclaw.com
`JONATHAN T. SUDER
`jts@fsclaw.com
`FRIEDMAN, SUDER & COOKE
`Tindall Square Warehouse No. 1
`604 East 4th Street, Suite 200
`Fort Worth, TX 76102
`T: 817-334-0400
`F: 817-334-0401
`
`Attorneys for Plaintiff
`PROGRESSIVE SEMICONDUCTOR SOLUTIONS LLC
`
`UNITED STATES DISTRICT COURT
`
`CENTRAL DISTRICT OF CALIFORNIA
`
`SOUTHERN DIVISION
`
` PROGRESSIVE SEMICONDUCTOR
`SOLUTIONS LLC,
`
`CASE NO. 8:13-cv-01535 ODW (JEMx)
`CASE NO. 8:14-cv-00330 ODW (JEMx)
`
`PLAINTIFF’S MEMORANDUM
`REGARDING TECHNOLOGY
`TUTORIAL
`
`Plaintiff,
`
`vs.
`
`QUALCOMM TECHNOLOGIES,
`INC.
`
`Defendant.
`
`PROGRESSIVE SEMICONDUCTOR
`SOLUTIONS LLC,
`
`Plaintiff,
`
`v.
`
`MARVELL SEMICONDUCTOR,
`INC.,
`
`Defendant.
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`1
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`Ex. 1009.001
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`Plaintiff has asserted U.S. Patent Nos. 6,473,349 (“the ‘349 Patent”) and
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`6,862,208 (“the ‘208 Patent”) (the “Patents-in-Suit”). The Patents-in -Suit relate
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`generally to memory within a semiconductor chip, and more particularly to circuit
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`designs and methods for accessing that memory in a manner that increases speed
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`and reliability, while reducing power consumption of the chip.
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`Semiconductor Chips. Defendants sell semiconductor chips, which are
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`sometimes referred to as “integrated circuits,” or “ICs.” An IC is a set of electronic
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`circuits on one small plate, or chip, of semiconductor material – such as silicon.
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`Early ICs contained only a few transistors. Today, ICs may contain millions (or
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`even billions) of transistors. ICs have revolutionized the world of electronics. For
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`example, a central processing unit (“CPU”) may exist on a single IC. Generally
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`speaking, processors perform calculations on data that is stored and retrieved from
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`memory.
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`Memory. Computers store data in the form of 0s or 1s, known as bits, in
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`various forms of memory. Each bit is stored by means of electrical voltages that
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`correspond to a 0 or 1. The term “RAM” stands for “random access memory,” and
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`refers to a computer data storage technology that allows data to be accessed in
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`random order from a large array of storage cells, thereby allowing the same data
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`retrieval time for data stored anywhere in the RAM. RAM is normally associated
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`with volatile types of memory, meaning the stored information is lost if power is
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`removed. There are two primary forms of RAM. Static RAM (“SRAM”) uses
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`multiple transistors (or multi-transistor circuits) to store and access each bit of data
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`(0 or 1). Bits are stored in the form of electric signals.1 By contrast, Dynamic
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`RAM (“DRAM”) uses a single transistor and a single capacitor to store each bit of
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`data. Each type of RAM design has pros and cons and may be employed in
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`different applications, depending on various design factors. SRAM is often used in
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`1 The operation of a circuit and the flow of electrons within the circuit may be described in
`various ways. For example, it may be appropriate to speak in terms of current, voltage, electric
`charge, electric signals, or electric potential – depending on the context.
`2
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`Ex. 1009.002
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`processor caches, which store data or instructions for immediate use by the
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`processor, because SRAM has faster access times than DRAM.
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`This suit involves SRAM. Data in SRAM is stored in tiny circuits, called
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`memory cells, which collectively form a memory array. Data is accessed via
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`addresses assigned to the memory cells, i.e., each memory cell has its own unique
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`address. The memory cells are organized into rows and columns, so a cell’s
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`address consists of a row address part and a column address part. When data from
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`a memory cell is to be retrieved or accessed, signals corresponding to that cell’s
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`address are typically sent to a memory controller situated between a CPU and the
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`SRAM. The memory controller sends an address to the SRAM in order to access
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`(i.e., read from or write to) a particular memory cell. Lines, typically referred to as
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`“wordlines,” run along the rows of the memory. Similarly, other lines, typically
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`referred to as “bit lines,” run up and down each side of the columns. Each memory
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`cell is associated with a wordline and two “complementary” bit lines. Each set of
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`complementary bit lines is connected to a sense amplifier.
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`The act of reading data from RAM is analogous to retrieving a snack from a
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`vending machine. For example, a vending machine may sell nine different snacks,
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`arranged in rows A, B, C and columns 1, 2, 3, with chips stored in row A, cookies
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`in row B, and candy in row C. A consumer may select the chocolate cookies
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`stored at location B3 by pressing the B3 button on the keypad, thereby delivering
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`the cookies to the retrieval bin at the bottom of the vending machine.
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`For various reasons, including concerns about size and power consumption,
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`the electric signal held in an SRAM memory cell is typically very small. The
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`stored value is transmitted, or “read,” in the form of two complementary signals –
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`each with different voltage values. The bit line may be referred to as “BL” and the
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`complementary bit line as “~BL” (sometimes referred to as “not BL” or “BL-bar”).
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`The two complementary or “differential” signals appearing on the bit lines
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`represent a single bit of logical information, either 0 or 1. This stored bit is
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`Ex. 1009.003
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`determined by the voltage difference between the differential signals on BL and
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`~BL. For example, if BL has a higher voltage level than ~BL, then the stored
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`value is 1; if BL has a lower voltage level than ~BL, then the stored value is 0.
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`However, because the voltage differences involved are so small, a “sense
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`amplifier” circuit is employed to detect (“sense”) and amplify the differential
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`signal. Once amplified by the sense amplifier, the differential data signal may be
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`easily read and the value transmitted by that signal (0 or 1) determined.
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`Memory Devices / Latches. Both Patents-in-Suit require an understanding
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`of the above-described interaction between the bit lines and the sense amplifier.
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`The ‘208 Patent goes a step further and therefore requires an additional discussion
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`of what happens to the amplified data signal and the corresponding data (0 or 1).
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`The retrieved bit (0 or 1) is stored in a storage device called a “latch” for later
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`access or use, much like how a snack from the vending machine may be retrieved
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`immediately from the retrieval bin or held there for a period of time. A latch is one
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`common type of memory device and takes the form of an electronic circuit that is
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`commonly used to store a single bit of information. An SRAM chip, for example,
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`would typically include millions of latches. A latch may receive various types of
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`inputs, such as data signals or control signals. One type of control signal is a clock
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`signal, which occurs in regular cycles or periods. These periodic signals oscillate
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`between a high and low state and operate like a metronome to coordinate actions
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`within the circuit. Some latches synchronize their operation so that the data stored
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`by the latch only changes state in response to a clock signal.
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`Schematics and Timing Diagrams. A schematic diagram shows, by means
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`of graphic symbols, the electrical connections and functions of an actual or
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`proposed circuit, and facilitates tracing the circuit and its functions without regard
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`to the actual physical size, shape or location of the component device or parts.
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`They are logical and functional “maps” that communicate to engineers the manner
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`in which the components are or should be interconnected and the manner in which
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`Ex. 1009.004
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`electric signals travel or operate in the circuit. They do not necessarily represent
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`the actual, physical placement of the components, and they do not communicate
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`the detailed electrical behavior of the components.
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`Similarly, a timing diagram provides a two-dimensional map showing how
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`electrical signals change over time. Timing diagrams (see, e.g., ‘208 Patent, Fig.
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`4) show – as a function of time -- the relationship between various input signals,
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`output signals, and device states.
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`Transistors. A transistor is commonly used as an electronic switch and
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`operates much like a valve in an indoor plumbing system, current is represented by
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`water flowing through the pipe and voltage is the water pressure. Like a valve, a
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`transistor may be turned on to allow current to flow, or turned off to prevent
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`current from flowing. Certain transistors or transistor pairs that operate as a switch
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`between data signals are sometimes referred to as pass transistors, pass gates, or
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`isolation transistors. Pass transistors may be used to construct an “isolation
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`circuit,” because when the transistors are turned “off,” they serve to “isolate” one
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`part of the circuit (for example, the data paths) from another part of the circuit (for
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`example, the sense amplifier). Stated another way, when the pass transistors are
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`“conductive,” they allow variable signals to pass and to travel to the sense
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`amplifier; when they are non-conductive, signals cannot travel between the data
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`paths and the sense amplifier.
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`Ex. 1009.005
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`

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`By: /s/ David A. Skeels
`
`David A. Skeels
`State Bar No. 24041925
`Jonathan T. Suder
`State Bar No. 19463350
`FRIEDMAN, SUDER & COOKE
`Tindall Square Warehouse No. 1
`604 East 4th Street, Suite 200
`Fort Worth, Texas 76102
`(817) 334-0400
`Fax (817) 334-0401
`jts@fsclaw.com
`skeels@fsclaw.com
`gunter@fsclaw.com
`
`Attorneys for Plaintiff,
`Progressive Semiconductor Solutions LLC
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`DATED: July 9, 2014.
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`Ex. 1009.006
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`

`
`PROOF OF SERVICE
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`I, Max B. Master, declare:
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`I am a citizen of the United States and employed in Los Angeles County, California. I am
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`over the age of eighteen years and not a party to the within-entitled action. My business address
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`is 510 W 6th St, Suite 700, Los Angeles, California, 90014. On June 18, 2014, I served a copy of
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`the within document(s):
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`PLAINTIFF’S MEMORANDUM REGARDING TECHNOLOGY TUTORIAL
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`
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`
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`
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`
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`
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`by transmitting via facsimile the document(s) listed above to the fax number(s) set
`forth below on this date before 5:00 p.m.
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`by placing the document(s) listed above in a sealed envelope with postage thereon
`fully prepaid, in the United States mail at Los Angeles, California addressed as set
`forth below.
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`by placing the document(s) listed above in a sealed Federal Express envelope and
`affixing a pre-paid air bill, and causing the envelope to be delivered to a Federal
`Express agent for delivery.
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`by personally delivering the document(s) listed above to the person(s) at the
`address(es) set forth below.
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`by transmitting via e-mail the document(s) listed above to the e-mail address(es)
`set forth below on this date before 5:00 p.m.
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`
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`
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`Ruffin B. Cordell
`Indranil Mukerji
`Joseph V. Colaianni
`Stephen A. Marshall
`Fish & Richardson P.C.
`1425 K Street, NW 11th Floor
`Washington, DC 20005
`cordell@fr.com
`mukerji@fr.com
`colaianni@fr.com
`smarshall@fr.com
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`Attorneys for Defendant Marvell
`Semiconductor, Inc.
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`Michael M. Rosen
`Olga May
`Daniel Chan
`Fish & Richardson P.C.
`12390 El Camino Real
`San Diego, CA 92130
`rosen@fr.com
`omay@fr.com
`dchan@fr.com
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`Attorneys for Defendant Marvell
`Semiconductor, Inc.
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`PROOF OF SERVICE
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`Ex. 1009.007
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`

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`Justin C. Griffin
`QUINN EMANUEL URQUHART &
`SULLIVAN, LLP
`865 South Figueroa Street, 10th Floor
`Los Angeles, California 90017-2543
`justingriffin@quinnemanuel.com
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`David A. Nelson
`Marc Kaplan
`QUINN EMANUEL URQUHART &
`SULLIVAN, LLP
`500 West Madison Street, Suite 2450
`Chicago, Illinois 60661-2510
`davenelson@qunnemanuel.com
`marckaplan@quinnemanuel.com
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`
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`Counsel for Defendant Qualcomm
`Technologies, Inc.
`
`Counsel for Defendant Qualcomm
`Technologies, Inc.
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` I
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` am readily familiar with the firm's practice of collection and processing
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`correspondence for mailing. Under that practice it would be deposited with the U.S. Postal
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`Service on that same day with postage thereon fully prepaid in the ordinary course of
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`business. I am aware that on motion of the party served, service is presumed invalid if
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`postal cancellation date or postage meter date is more than one day after date of deposit for
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`mailing in affidavit.
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`I declare under penalty of perjury under the laws of the State of California that the above
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`is true and correct.
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`Executed on July 9, 2014 at Los Angeles, California.
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`___________________________________
` Max B. Master
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`DO CUM E NT PRE P A RE D
` O N RE CY CLE D PA P E R
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`PROOF OF SERVICE
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`Ex. 1009.008