United States Patent [19J
`Reohr et al.
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111
`US005481500A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,481,500
`Jan.2, 1996
`
`[54] PRECHARGED BIT DECODER AND SENSE
`AMPLIFIER WITH INTEGRATED LATCH
`USABLE IN PIPELINED MEMORIES
`
`[75]
`
`Inventors: William R. Reohr, Pleasantville; Yuen
`H. Chan, Poughkeepsie; Pong-Fei Lu,
`Yorktown Heights, all of N.Y.
`
`[73] Assignee: International Business Machines
`Corporation, Armonk, N.Y.
`
`[21] Appl. No.: 279,366
`Jul. 22, 1994
`
`[22] Filed:
`
`Int. Cl.6
`..............................•...................... GllC 13/00
`[51]
`[52] U.S. CI . .......................... 365/203; 3651205; 365/208;
`365/189.05; 365/194
`[58] Field of Search ..................................... 365/203, 205,
`365/207, 208, 189.05, 194; 327/50, 51,
`55, 57
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`RE 34,026
`3,983,412
`4,045,785
`4,253,163
`4,843,264
`4,843,595
`4,922,461
`
`8/1992 Duvvury et al ..
`9/1976 Roberts et al ..
`8/1977 Kirkpatrick, Jr ..
`2/1981 Komoriya et al ..
`6/1989 Galbraith .
`6/1989 Suzuki .................................... 365/207
`5/1990 Hayakawa et al. ..................... 365/207
`
`BL 4
`
`DEC4 9--<I
`
`1
`
`BL3
`Bl2
`'
`DEC3.-q h DEC29-<I
`12
`.
`I
`
`3
`
`Bll
`
`DEC19-<i
`
`4
`
`4,932,002
`5,007,024
`5,015,891
`5,034,636
`5,126,974
`5,127,739
`5,204,560
`5,247,479
`5,305,272
`
`6/1990 Houston .
`411991 Tanaka et al ........................... 365/203
`5/1991 Choi ........................................ 365/205
`7/1991 Reis et al ..
`6/1992 Sasaki et al. . .......................... 365/208
`7/1992 Duvvury et al ......................... 365/205
`4/1993 Bredin et al. .
`9/1993 Young .
`4/1994 Matsuo et al ........................... 365/203
`
`Primary Examiner-David C. Nelms
`Assistant Examiner-Yu A. Le
`Attorney, Agent, or Firm-Lynn L. Augspurger; Marshall M.
`Curtis
`
`[57]
`
`ABSTRACT
`
`A memory and sense amplifier with latched output included
`therein derives high speed and noise immunity with pre(cid:173)
`charged logic circuits through the separation of sense ampli(cid:173)
`fier enablement and resetting by use of the precharge opera(cid:173)
`tion. Inclusion of bit line decoders which are wholly or
`partially self-resetting and self-precharging in sense ampli(cid:173)
`fier support circuitry allows high performance at extremely
`short memory operation cycle times. A multiplexor is
`included which is usable in operating cycles as well as test
`cycles of the memory and further, in combination with other
`elements of the memory and sense amplifier arrangement,
`enables the pipelining of plural memory operations in a
`single memory cycle.
`
`4 Claims, 13 Drawing Sheets
`
`BR1
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`OUT
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`PCN
`
`CORE SENSE AMPLIFIER CIRCUIT
`
`Ex. 1005.001
`
`

`
`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet 1of13
`
`5,481,500
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`

`
`U.S. Patent
`
`Jan.2, 1996
`
`Sheet 3of13
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`5,481,500
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`

`
`U.S. Patent
`
`Jan.2, 1996
`
`Sheet 4of13
`
`5,481,500
`
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`
`Ex. 1005.005
`
`

`
`U.S. Patent
`
`Jan.2, 1996
`
`Sheet 5of13
`
`5,481,500
`
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`
`Ex. 1005.006
`
`

`
`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet 6of13
`
`5,481,500
`
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`Ex. 1005.007
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`

`
`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet 8of13
`
`5,481,500
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`
`

`
`U.S. Patent
`
`Jan.2, 1996
`
`Sheet 12 of 13
`
`5,481,500
`
`FOR THE BIT DECODER OF FIGURE 8 WHICH
`IS MODIFIED FOR A
`SINGLE CYCLE READ AND WRITE
`_n...._ ___ ___.n.___ ___ ___.I
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`
`Ex. 1005.013
`
`

`
`U.S. Patent
`
`Jan.2, 1996
`
`Sheet 13 of 13
`
`5,481,500
`
`1130
`
`WRITE CIRCUIT
`
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`(FIGURE 4)
`
`Ex. 1005.014
`
`

`
`5,481,500
`
`1
`PRECHARGED BIT DECODER AND SENSE
`AMPLIFIER WITH INTEGRATED LATCH
`USABLE IN PIPELINED MEMORIES
`
`BACKGROUND OF THE INVENTION
`
`5
`
`2
`logic state is only done when the input signal requires such
`a change. Thus, the circuit can be easily optimized to
`enhance the speed of such a transition. The establishment of
`the logic state before an input signal is applied is generally
`referred to as precharging.
`Other advantages also accrue from such logic designs.
`Consider, for example, a CMOS inverter comprised of an
`N-channel FET and a P-channel FET. To obtain symmetrical
`response, the P-channel FET must be of approximately twice
`the size (and gate capacitance) of the N-channel FET. In a
`dynamic or precharged logic device having a comparable
`function, complementary transistors need not be provided
`with a consequent decrease in element count and gate
`capacitance. Moreover, the transistor used to provide or hold
`the precharged state may be very weak (e.g. of relatively low
`conductivity) and thus ofreduced size.
`Unfortunately, while the potential gains in speed of opera(cid:173)
`tion are substantial using precharged or dynamic logic,
`response of the circuit is more sensitive to noise and
`20 recovery from a transition triggered by noise cannot readily
`be accomplished within the same cycle time (e.g. a clock
`cycle or a memory operation cycle).
`For this reason also, precharged logic circuits require
`meticulous tracking and analysis of effects such as noise
`sources, charge sharing, signal coupling, power supply con(cid:173)
`siderations and the like, particularly when used in critical
`paths of digital signal processing circuitry. In this regard, it
`should be understood that digital signal processing generally
`involves logical operations on combinations of signals and
`signals of the correct logical levels must be present at the
`time the logical operation is carried out in order to achieve
`the correct result. Therefore, variations in signal level which
`may be encountered in normal operations of digital circuits
`may cause erroneous operation when applied to precharged
`logic circuits unless timing is carefully analyzed and con-
`trolled to assure that voltage levels will be properly recog(cid:173)
`nized as the logical states they are intended to represent.
`However, precharging of a circuit and the design of
`circuits in which precharging can be exploited are not
`necessarily straightforward since states of transistors may be
`achieved which cause transient serial conduction paths if
`precharge and evaluation transistors are simultaneously
`active. This results in excessive power consumption which
`may, in turn, affect response speed or pull voltage levels
`away from the intended logic states. Precharging can thus
`easily defeat the gains to be derived by design for asym(cid:173)
`metrical circuit response and precharging, particularly
`where precharging proceeds in a sequence of steps. Further,
`providing a high impedance state of one or more transistors
`may increase susceptibility of the circuit to noise from any
`of several sources which would be especially deleterious to
`the operation of a precharged circuit.
`It should also be noted that the above asymmetrical
`response speed design concept and precharging cannot reli(cid:173)
`ably be used in circuits which receive signals from a circuit
`which is not driven solidly to logic level voltages (e.g. power
`supply and ground). If such a circuit is precharged and
`supplied with an ambiguous input voltage, the output may be
`in error since precharged logic circuits, by their nature, have
`little noise tolerance and thus may result in outputs having
`voltages which are even more ambiguous as well as includ(cid:173)
`ing effects of noise sources and power supply variation (e.g.
`"bounce") when common-mode currents are drawn; possi-
`65 bly being of sufficient severity to cause erroneous operation
`or triggering of a precharged circuit. When such a circuit
`(including dynamic logic circuits) is erroneously triggered
`
`10
`
`15
`
`30
`
`1. Field of the Invention
`The present invention generally relates to a sense ampli(cid:173)
`fier and bit decoder usable, for example, in electronic
`random access memories and, more particularly, to a sense
`amplifier with an integrated latch function combined with a
`bit decoder for memories which have extremely short access
`and propagation times and which may be operated in a
`pipelined mode to include, for example, a write-only access
`during a portion of a memory cycle as well as to perform
`other functions within the memory such as the concatenation
`of sense amplifier output fields read out over multiple
`memory operation cycles.
`2. Description of the Prior Art
`Electronic data processing, at its most basic level, usually
`involves a fetch of an instruction and/or data signal from
`memory, performance of an operation on or in response to
`that signal and storage of a resulting signal. The speed at
`which a data processing operation or instruction can be
`executed is therefore highly dependent on the cycle time 25
`required for a memory operation to retrieve and/or store a
`digital signal in memory. Digital signal storage can be done
`in many diverse media; each having characteristic proper(cid:173)
`ties, advantages and access times.
`Static memories include a bistable memory element.
`Dynamic memories require refreshing since their memory
`elements rely on stored charge. Both static and dynamic
`memories typically use sense amplifiers to detect and
`amplify small signal voltage differences produced by the 35
`memory cells. Sense amplifier are designed to minimize
`noise sources: transistor parametric variations, charge shar(cid:173)
`ing, signal coupling, and power supply noise.
`Whether the memory is of the static or dynamic type,
`certain additional structure is necessary in order to access a 40
`particular memory cell, to determine its contents and to
`develop and deliver an output which is stable and reliably
`timed, Whether in the form of latches, gates inverters or
`other types of circuits, such structures generally perform
`logical functions within the memory device. In the past, such 45
`logic circuitry has been of generally the same design as
`would be used to perform logic functions in a processor or
`any other form of digital circuit. That is, the response of the
`circuit was generally designed to be approximately sym(cid:173)
`metrical relative to an input voltage level. Thus, when the 50
`input voltages, often including a clock signal, became rela(cid:173)
`tively stable, a stable output and sufficient noise margins
`were generally assured and recovery from noise distur(cid:173)
`bances were possible within the same clock cycle. (These
`forms of logic circuit will be referred to hereinafter as static 55
`logic to more readily distinguish from so-called precharged
`logic circuits, occasionally referred to as dynamic logic,
`which follows.)
`More recently, several significant advantages over static
`logic circuits have been realized by the development oflogic
`circuit designs which are highly asymmetrical in response to
`both input voltage levels and response speed. The basic
`theory of the response speed improvement in such devices is
`that propagation time of a logic element will be minimized
`if the circuit can be brought to a logic state from which it
`may rapidly be switched to another logic state before data is
`applied to it. Then, when data is applied, switching of the
`
`60
`
`Ex. 1005.015
`
`

`
`5,481,500
`
`4
`SUMMARY OF THE INVENTION
`
`It is therefore an object of the present invention to provide
`a memory including a sense amplifier including a latch and
`multiplexer and using asymmetrical response speed circuits
`5 with precharging which is capable of directly driving static
`and precharged types of logic circuits.
`It is another object of the invention to provide a sense
`amplifier for a memory which has a high degree of noise
`immunity.
`It is further object of the invention to provide support
`circuits for a memory to enable performance of both a read
`operation and a write operation within a single operating
`cycle delineated by a clock.
`It is yet another object of the invention to provide a
`latching function of a sense amplifier such that data read
`from memory can be selectively maintained over a plurality
`of memory cycles in order to support additional memory
`operations such as concatenation of data fields.
`In order to accomplish these and other objects of the
`invention, a precharged sense amplifier arrangement is pro(cid:173)
`vided including a bistable differential amplifier, an arrange(cid:173)
`ment for enabling sensing of a differential voltage by the
`bistable differential amplifier including an arrangement for
`causing latching of outputs of the differential amplifier, and
`an arrangement for precharging at least the arrangement for
`enabling sensing and inputs of the differential amplifier in
`sequence, including an arrangement for resetting the
`arrangement for causing latching of outputs of the differen(cid:173)
`tial amplifier.
`In accordance with another aspect of the invention, a
`sense amplifier support circuit is provided including a
`decoder, an arrangement for gating a reset of the decoder, an
`arrangement for precharging the decoder in response to a
`logic state of an output of the decoder subsequent to a reset
`of said decoder, and an arrangement for simultaneously
`disabling all outputs of said decoder.
`In accordance with a further aspect of the invention, a
`method of operating a memory including a sense amplifier
`including a bistable differential amplifier selectively con(cid:173)
`nectable to a plurality of bit lines is provided including the
`steps of precharging the sense amplifier in response to a
`precharge signal, enabling the bistable differential amplifier
`to amplify a voltage difference connected to inputs thereof
`in response to a sense amplifier enable signal, latching an
`output of the bistable differential amplifier, and terminating
`the latching step in response to a precharge signal.
`In accordance with yet another aspect of the invention, a
`50 method of operating a memory device including at least two
`sense amplifiers, each of said at least two sense amplifiers
`including means for precharging a respective one of said
`sense amplifiers in response to a precharge signal is provided
`including the steps of performing a read operation concur(cid:173)
`rently with the at least two sense amplifiers, interrupting a
`precharge signal to at least one of the at least two sense
`amplifiers, and performing a further read operation with at
`least another of the at least two sense amplifiers in the same
`cycle as the interrupting step.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`10
`
`3
`after precharge, it is virtually impossible and certainly
`highly impractical to provide for recovery prior to the next
`operation cycle.
`In view of the above design considerations, it is often
`attractive to mix dynamic and static types of logic circuitry
`to optimize both the design efficiency and performance of a
`particular digital processor arrangement or logic directly
`responsive to memory output. For example, it is known to
`add a static latch to a sense amplifier to extend the time
`period during which a bit read from memory will be avail(cid:173)
`able beyond the end of a particular memory cycle.
`As is known, sense amplifiers generally operate by ini(cid:173)
`tially bringing a bistable circuit to a balanced condition
`between its stable states; from which condition, the sense 15
`amplifier can be unbalanced and made to assume one of its
`stable states by an extremely small voltage difference.
`Therefore, a sense amplifier must be precharged. Precharg(cid:173)
`ing must be completed prior to the development of the small
`voltage difference (which represents the memory cell state) 20
`on the sense amplifier internal nodes. A small voltage must
`exist at the inputs of the sense amplifier in order for proper
`operation of the sense amplifier to occur.
`By the same token, since precharge of the sense amplifier 25
`also balances the voltages on the output nodes, data is not
`available from the sense amplifier once precharging of the
`sense amplifier has begun. Additionally, in known designs
`which add a static latch to the sense amplifier, the static latch
`must be reset or precharged prior to a subsequent enabling 30
`of the sense amplifier. Therefore, some aspects of timing
`may remain critical when extremely high speed of operation
`is required.
`It should also be understood that, at the present state of the
`art, substantial design effort may be expended to obtain a 35
`seemingly small percentage increase in response speed. An
`improvement of 10%, for example, is considered to be a very
`large improvement. One reason for the difficulty in obtaining
`larger improvements is that each design strategy, such as
`precharging of circuits with asymmetrical response speeds,
`also requires a finite amount of time to carry out and some
`finite time margin to reach a stable operating state of the
`circuit in response to such an operation. For example, if
`precharging does not occur sufficiently early in a memory 45
`cycle to be completed before a memory cell is accessed to
`couple the memory cell output to the sense amplifier, mal(cid:173)
`function of the sense amplifier may occur because the
`precharge network will retard the development of a differ(cid:173)
`ential voltage on the sensing nodes.
`Other uses of a sense amplifier within a memory device,
`such as multiplexing inputs thereto to provide additional
`operations within a single cycle can also cause an erroneous
`write to memory unless precautions are taken. As alluded to
`above, much design effort has been expended in seeking to 55
`obtain several operations within a single clock cycle. One
`such technique is referred to as pipelining, in which several
`operations, which may be of different types (such as read
`and write) regularly occur at different phases of the same
`clock cycle. For example, a memory which provides two 60
`read-write operations and one write-only operation in a
`single processor cycle of 15 nanoseconds is disclosed in "A
`200 MHz Internal/66 MHz External 64 kB Embedded
`Virtual Three Port Cache SRAM" by G. Braceras et al., 1994
`International Solid State Circuits Conference, ISSCC94/ 65
`Session 15/Static memory for High-Bandwidth Systems/
`Paper FA15.3, which is hereby incorporated by reference.
`
`40
`
`The foregoing and other objects, aspects and advantages
`will be better understood from the following detailed
`description of a preferred embodiment of the invention with
`reference to the drawings, in which:
`FIG. 1 is a generalized depiction of a dual slope sense
`amplifier,
`
`Ex. 1005.016
`
`

`
`5,481,500
`
`5
`FIG. 2 is a circuit disclosed in U.S. Pat. No. 5,204,560
`which is useful in understanding of some aspects of the
`present invention,
`FIG. 3 is a circuit disclosed in U.S. Pat. No. 4,843,264
`which is useful in understanding of additional aspects of the 5
`present invention,
`FIG. 4 is a schematic diagram of the core sense amplifier
`circuit of the present invention,
`FIG. S is a logic diagram of the sense amplifier support
`circuit in accordance with the present invention,
`FIG. 6 is a timing diagram illustrating the operation of the
`invention,
`FIG. 7 is a schematic diagram of a bit decoder usable in
`the circuit of FIG. 6,
`FIG. SA illustrates another bit decoder allowing single
`cycle read and write operations,
`FIG. SB is a variation of the bit decoder of FIG. SA,
`FIG. 9 is a timing diagram illustrating the operation of the 20
`invention to provide single cycle read and write operations,
`and
`FIG. 10 is a simplified schematic diagram showing a
`circuit for providing read and write accesses within a single
`clock cycle.
`
`25
`
`DETAILED DESCRIPTION OF A PREFERRED
`EMBODIMENT OF THE INVENTION
`
`6
`where nodes Nl and N2 are close to the same voltage ·
`(differing only by a voltage due to voltage difference of the
`memory cell and both transistors lS, 19 of the sense ampli-
`fier are in a conductive state).
`This mode of operation reduces the possibility of falsely
`triggering the inactive output of the sense amplifier which
`ultimately permits the sensing of small differences in input
`voltage. Further, any noise or rise at the inactive output
`10 could falsely trigger dynamic logic gates which are driven
`by the sense amplifier and which have reduced noise mar(cid:173)
`gins compared with static circuits.
`Also shown in FIG. 1 is a multiplexor or bit switch Cl
`which serves to selectively connect the bit lines BL or other
`15 signals to the differential input nodes Nl, N2 of the sense
`amplifier. The multiplexor Cl of FIG. 1 is often provided in
`two portions: a first portion, often referred to as a bit line
`switch which receives bit line decode signals to connect a
`particular bit line to the sense amplifier, and a second
`portion, also commonly referred to as a multiplexor (but
`distinct from the bit line switch) for alternatively providing
`connection to other signals when the bit line switch is
`inactive. It is common practice for this second multiplexor
`portion (hereinafter referred to by the abbreviation "mux" to
`distinguish the term from multiplexor Cl) to be used to
`clamp other circuitry to the sense amplifier for purposes of
`memory testing, such as is shown in U.S. Pat. No. 5,204,560
`to Bredin et al.; a schematic diagram of which is shown in
`30 FIG. 2.
`In the circuit shown in FIG. 2, it can readily be appreci(cid:173)
`ated that bit line switching is done in the circuit enclosed by
`chain line 11 and the mux is enclosed by dashed line 2S. The
`mux is enabled during testing procedures by an additional
`clock signal Ac in addition to clock signal Be which is used
`to gate the output signal. The Ac clock is only asserted in the
`testing mode when the bit line switching circuit 11 is idle.
`Conversely, mux 2S is disabled by the absence of the Ac
`phase clock pulse during system operation. It should be
`40 further noted that the mux 2S of Bredin cannot be used
`during system mode operation since there is no provision for
`assuring an absence of selection in the bit line select
`switching circuit when the mux 2S is enabled, as is neces-
`sary for SRAMs.
`Referring now to FIG. 3, a known implementation of an
`integral latch with a sense amplifier is shown as disclosed in
`U.S. Pat. No. 4,843,264 to Galbraith. In this circuit topology,
`a pre-amplifier is formed by transistors MS and M6, together
`with transistor M7 prior to a cross-coupled differential
`amplifier formed by M3 and M4. The differentially applied
`input signals IN and IN B are thus amplified by transistors
`MS and M6 before they reach the latching nodes Nl' and N2'
`(primes being added to node reference numbers in FIG. 3 to
`distinguish from the node reference numbers used to explain
`the invention). Further, when the enable signal is asserted
`low during precharge of the sense amplifier circuit, the sense
`amplifier output nodes N6' and N7' are precharged high by
`a downward pulse on EQB through transistors MlS and
`Ml6. Since nodes Nl' and N2' are high, M9 and MlO are off.
`60 The remaining transistors Mll and Ml2 are off since their
`sources have been precharged high by M21. That is, during
`precharge, transistors MlS, M9, MU, Ml6, MlO and Ml2
`are all inactive prior to enable signal SE again being asserted
`high so that dynamically stored charge can be used to keep
`65 N6' and N7' high. However, the high impedance states of
`inactive transistors M9-Ml2 is susceptible to noise distur(cid:173)
`bances.
`
`35
`
`Referring now to the drawings, and more particularly to
`FIG. 1, there is shown a generalized depiction of a dual slope
`sense amplifier similar to that employed in the present
`invention. It is to be clearly understood that no admission is
`made that any portion of the depiction of FIG. 1 is prior art
`as to the present invention or that any particular known
`device is depicted. The depiction of FIG. 1 is intended to
`convey a general understanding of the design of a particular
`type of sense amplifier over which the present invention
`provides an improvement in order that certain features of the
`present invention may be more readily understood.
`The term dual slope sense amplifier derives from the
`design feature that the sense amplifier enable signal, SAE,
`first turns on a small transistor 21 oflow conductance to bias
`the cross-coupled differential amplifier lS, 19 after an initial
`voltage (typically 100-200 mV for 2.5 volt technology) 45
`develops across the active bit lines. Then, once sufficient
`voltage is developed across nodes Nl, N2, (typically
`500-1000 mV) transistor 31 is activated to rapidly complete
`the sensing operation. Specifically, this low conductance
`transistor 21 draws a small current from node N4 and 50
`tending to pull the voltage at N4 toward ground, permitting
`conductance of the sensing transistors lS and 19 connected
`to nodes Nl and N2, respectively.
`However, due to the cross-coupled connection of transis(cid:173)
`tors lS and 19, the conductance of one will increase while
`the other will decrease, depending on the differential voltage
`from the bit lines connected thereto. The sense amplifier
`enable signal is also delayed for a short period by the serial
`propagation times of inverters 11 and 12 at nodes NS and N6,
`respectively, before being applied to a second, high-conduc(cid:173)
`tance, transistor 31 which completes the sensing operation
`and brings node N4 and one of nodes Nl and N2 solidly to
`ground and the sense amplifier to a stable operating state at
`increased speed. This two-stage operation thus avoids a
`large common-mode current from being drawn through both
`sides of the cross-coupled sense amplifier circuit when the
`sense amplifier is in a relatively balanced conduction state
`
`55
`
`Ex. 1005.017
`
`

`
`5,481,500
`
`10
`
`7
`In contrast to the known arrangements illustrated in FIGS.
`2 and 3, a preferred embodiment of the invention, shown in
`FIG. 4, provides both an integrated latch and multiplexor for
`the sense amplifier depicted in FIG. 1. As an overview, the
`improved latching section of the sense amplifier separates 5
`the sense amplifier enable signal SAE from the precharge
`signal pen (precharge negative; the precharge signal being
`considered active when low) which allows fast and direct
`precharge of the latch such that precharge is accomplished
`before the address decoding is completed in the bit line
`select switching circuit. Further, the separation of the sense
`amplifier enable function and the precharge function allows
`data to be statically held by the latch beyond the termination
`of the sense amplifier enable signal SAE until the static latch
`is reset by another precharge signal pen.
`More specifically, the circuit of FIG. 4 may be initially 15
`considered as including three major functional elements: bit
`line switching is provided by the circuit enclosed in box Cl,
`the mux switching is provided by the circuit enclosed in box
`C2 and the sense amplifier, including an integral latch and
`precharge circuit, is enclosed in box C3. (reference numerals 20
`used in FIG. 1 correspond to the same elements in FIG. 4
`except that both bit line select circuit Cl and box C2 are
`included within box Cl of FIG. 1.)
`As shown in FIG. 4, the cross-coupled differential sense
`amplifier is preferably provided by a pair of cross coupled
`inverters comprising complementary transistors 16, lS and
`17, 19, respectively. Sensing nodes Nl and N2 are pre(cid:173)
`charged and equalized by transistors 13 and 15, which are
`connected to the power supply voltage, with transistor 14
`connected between the sensing nodes Nl and N2 so that
`transistors 13, 14 and 15, when simultaneously conductive,
`form a single node connected to the power supply voltage.
`Output buffer amplifiers, such as are formed by transistors
`32, 33, and 36, 37, each precharged by transistors 34 and 35,
`respectively, are preferably provided for each of the sense
`amplifier outputs but are only important to the practice of the
`invention to the extent that they repower the sense amplifier
`signal.
`The sensing transistors lS and 19 are connected to ground
`by transistors 21 and 31 which are operated in sequence as
`discussed above with reference to FIG. 1 to provide a dual
`slope function in the sensing operation. Note also that the
`function of transistors 16 and 17 is to return the high node,
`either Nl or N2 to the power supply voltage since inevitable
`common mode current through transistors lS and 19 will
`otherwise cause the high node