UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________________________
`
`Broadcom Corp.,
`Petitioner
`
`v.
`
`Progressive Semiconductor Solutions LLC,
`Patent Owner.
`
`Case No. ______
`
`
`
`DECLARATION OF STANLEY SHANFIELD, PH.D., IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 6,862,208
`UNDER 35 U.S.C. § 312, 37 C.F.R. § 42.104
`
`
`______________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________________________
`
`Broadcom Corp.,
`Petitioner
`
`v.
`
`Progressive Semiconductor Solutions LLC,
`Patent Owner.
`
`Case No. ______
`
`
`
`DECLARATION OF STANLEY SHANFIELD, PH.D., IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 6,862,208
`UNDER 35 U.S.C. § 312, 37 C.F.R. § 42.104
`
`
`
`
`
`Declaration of Stanley Shanfield, Ph.D.
`
`1.
`
`I, Stanley Shanfield, Ph.D., have been retained by O’Melveny & Myers,
`
`LLP, counsel for Broadcom Corp., and Broadcom Corr. (“Broadcom”).
`
`I understand that Broadcom has petitioned for inter partes review of U.S.
`
`Patent No. 6,862,208 (“the ‘208 patent”) and requests that the United
`
`States Patent and Trademark Office cancel Claims 1-32 of the ‘208
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`patent as unpatentable. The following discussion and analyses address
`
`the bases for Broadcom’s petition.
`
`I.
`
`BACKGROUND AND EXPERIENCE
`A. Qualifications
`2.
`I have more than 29 years of experience in integrated circuit design. In
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`particular, I devoted approximately 25 years of my professional career to
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`in depth research and development that involved the design, optimization
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`and application of semiconductor memory circuits.
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`3. My research has resulted in the publication of more than 20 scientific
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`articles in peer-reviewed journals, and more than 40 studies and reports
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`in the area of integrated circuit design, fabrication, and testing.
`
`4.
`
`I have authored or co-authored several publications that are directly
`
`related to integrated circuit design. These publications include:
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`• Shanfield, Stanley, "IC Technologies for Wireless Applications
`
`Beyond 2000", IEEE IC Symposium, October, 1997.
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`1
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`• Tkachenko, Y.A.; Lan, Y.; Whitefield, D.S.; Wei, C.J.; Hwang,
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`J.C.M.; Harris, T.D.; Grober, R.D.; Hwang, D.M.; Aucoin, L.;
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`• Shanfield, S., "Hot-electron-induced Degradation of Metal-
`
`Semiconductor Field-Effect Transistors”, GaAs Integrated Circuit
`
`Symposium, 1994, Technical Digest 1994, 16th Annual Volume,
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`Issue, 16-19 Oct. 1994, pp. 259.
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`• Shanfield, Stanley, "Design & Evaluation of Ultra-Fast Control
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`Electronics for Integrated Optical Multiplexer", 2002 (restricted
`
`report).
`
`5.
`
`I am an inventor or co-inventor of at least seven U.S. patents and pending
`
`patent applications, including U.S. Patent Numbers: 4,526,673;
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`5,362,526; 6,504,235; and 8,653,897 in the field of integrated circuits.
`
`6.
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`I have served as Division Leader of Advanced Hardware Development,
`
`and I am a Technical Director and Distinguished Member of Technical I
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`Staff at Draper Laboratory. I have held the above positions since 2003.
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`At Draper, I have been the author of a detailed analysis of state-of-the-art
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`integrated circuit memory, and have investigated all the important
`
`performance aspects of dynamic random access memory (DRAM) and
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`static random access memory (SRAM) design.
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`7.
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`From 2001 to 2003, I worked as a Director of Packaging and Integration
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`2
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`at Clarendon Photonics. During my time at Clarendon, I developed
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`control electronics in an add-drop multiplexing system by integrating
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`high speed memory into a custom-designed controller ASIC.
`
`8.
`
`From 1999 to 2001, I helped found and was Vice President of Operations
`
`at AXSUN Technologies. During my time at AXSUN, I led the
`
`development of the product control electronics, which included custom
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`integrated circuit design for an optical network monitoring system.
`
`9.
`
`From 1985 to 1999, I held various positions at Raytheon Corporation
`
`including: Section Manager, Semiconductors; Research Laboratory
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`Manager; and Manager of Semiconductor Operations. During my time at
`
`Raytheon, I worked in the design and fabrication of integrated circuits, in
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`many cases specifically involving SRAM and DRAM design and
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`development.
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`10. From 1981 to 1984, I was a Staff Scientist at Spire Corporation.
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`11.
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`I earned a Doctor of Philosophy in Physics from the Massachusetts
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`Institute of Technology in 1981.
`
`12.
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`I earned a Bachelor of Science in Physics, graduating cum laude, from
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`the University of California at Irvine in 1977.
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`13.
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`I have been an expert in the field of integrated circuits and memory
`
`devices since prior to 2003. I am qualified to provide an opinion as to
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`3
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`what a person of ordinary skill in the art would have understood, known
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`or concluded as of 2003.
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`14. Attached as Exhibit 1003 is my curriculum vitae setting forth my
`
`educational experience, employment history, professional affiliations,
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`B.
`15.
`
`and publications.
`
`Previous Testimony
`
`In the previous five years, I have testified as an expert at trial or by
`
`deposition or have submitted declarations in the following cases:
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`• American Technical Ceramics (ATC) vs. Presidio Components
`
`(Petitioner), Cases: IPR2015-01330; IPR2015-01331; IPR2015-
`
`01332
`
`• Samsung Electronics (Petitioner) vs. Flamm, IPR2015-01330
`
`• Progressive Semiconductor vs. Qualcomm, IPR2014 - 01504
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`• Bluestone Innovations, LLC vs. LG Electronics, No. 3:13-cv-01770
`
`(N.D. Cal. June 24, 2014);
`
`• Certain Microprocessors, Components Thereof, and Products
`
`Containing Same, Inv. No. 337-TA-781 (December 18, 2012);
`
`• Solannex, Inc. vs. Miasole, Inc., No. 5:11-cv-00171 (N.D. Cal.
`
`2013);
`
`• Spansion LLC v. Samsung Electronics Co., Ltd. et al., Case No.
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`4
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`1:10-cv-00881-LO-JFA (E.D. Va. 2011); and
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`• Certain Semiconductor Integrated Circuits and Products
`
`Containing Same, Inv. No. 337-TA-665, (January 29, 2010)
`
`(Final), aff'd, Qimonda AG, v. U.S. Int'l Trade Comm'n, 407
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`Fed.Appx. 449 (Fed. Cir. 2011).
`
`C. Compensation
`16.
`I am being compensated for my time at a rate of $385 per hour, plus
`
`actual expenses. My compensation is not dependent in any way upon the
`
`outcome of Broadcom’s petition.
`
`II. MATERIALS CONSIDERED
`17.
`I have considered and reviewed at least the documents labeled Exhibits
`
`1001, and 1004-1009 in connection with providing this declaration.
`
`III. THE ’208 PATENT
`18. The ‘208 patent (Ex. 1001), describes a memory device with a sense
`
`amplifier and a self-timed latch. The ‘208 patent was filed on April 11,
`
`2003, issued on March 1, 2005, and names Jeremiah T.C. Palmer and
`
`Perry H. Pelley, III as inventors.
`
`19. The ‘208 “relates in general to integrated circuits and in particular to
`
`memory devices.” Ex. 1001, ‘208 patent, 1:6-7. Memory devices include
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`a memory cell array comprising “a plurality of memory cells, each for
`
`5
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`storing a bit of data.” Id. at 1:12-15. The memory cells are organized in
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`the array by rows (called “word lines”) and columns (called “bit lines”),
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`and each memory cell of the array is “coupled to a pair of differential bit
`
`lines … [and] to a word line.” Id. at 1:15-19
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`20. As the ‘208 patent acknowledges, prior art memory devices “include
`
`sense amplifiers for providing a signal indicative of a value stored in a
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`memory cell of an array coupled to the sense amplifier.” Id. at 1:10-13.
`
`The ‘208 patent, as shown in the annotated FIGs. 1 and 2 of the ‘208
`
`patent below, conveys that the only difference between the admitted prior
`
`art and the claimed subject matter is using the self-timed latch 215 as
`
`opposed to using latch 115 with a clock signal. See id. at FIGs. 1-2. All
`
`other claimed elements are admitted as being prior art. See id. at FIGs. 1-
`
`2; see also 1:10-42.
`
`6
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`
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`21. Latches are basic circuit elements used in integrated circuit design to
`
`maintain a logic state so that it can be read by downstream logic circuits.
`
`For example, the Kong patent, Exhibit 1007, states that latches are “data
`
`storing devices [and] are the most basic elements for a VLSI [very large
`
`scale integration] system.” Ex. 1007, Kong at 1:11-13. In memory
`
`systems, latches may be used to reliably store the output of the sense
`
`amplifier so that it can be read out by other circuitry. See, e.g., Ex. 1005,
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`Reohr at 9:34-35 (“the latching function of the sense amplifier provides
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`stable outputs until the next cycle begins.”).
`
`22. Some latches are characterized as clocked latches because they receive a
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`7
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`separate clock or enable signal that controls when the data should be
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`captured. See, e.g., Ex. 1006, Johnson at1:21-23; Ex. 1007, Kong at
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`1:13-20.
`
`23. Other latches are known as self-timed latches because there is no clock or
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`enable signal controlling when data should be captured. See, e.g., Ex.
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`1007, Kong at 1:26-30 (a self timed latch “does not apply [a] clock
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`signal.”); Ex. 1006, Johnson at 1:61-64 (a self-timed latch “allows for the
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`automatic latching of data when the sense amp is evaluated without
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`requiring the generation of other timing signals.”); Ex. 1005, Reohr at 58-
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`61 (“The latching action of transistor 31 is evident since the output
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`voltages [of the sense amplifier] (out and out_n) are available once SAE
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`[sense amplifier enable] is asserted until the precharge of the next
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`cycle.”)
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`24. Figure 3 of the ’208 patent depicts a block diagram of an embodiment of
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`the claimed invention. Ex. 1001, ’208 patent, at 1:52-55. Colored
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`highlighting in the annotated version of Figure 3, reproduced below,
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`depicts some of the claimed features:
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`8
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`
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`25. BL 205 and *BL207, highlighted in red, are complementary bit lines that
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`connect to a particular memory cell. Ex. 1001, ’208 Patent at 2:46-55.
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`The isolation transistors 306 and 308 (highlighted in blue) are controlled
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`by a “column decode” (CD) signal to alternatively connect the bit lines to
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`the sense amplifier (shown in yellow) or isolate them from the sense
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`amplifier. Id. at 2:49-58. A precharge circuit (highlighted in purple) is
`9
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`used to precharge the local data lines (LDL and *LDL). Id. at 2:59-65.
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`The sense amplifier (highlighted in yellow) is comprised of two cross
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`coupled inverters formed from transistors 317 and 319, and 315 and 321.
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`Id. at 2:66-3:2. The sense amplifier is turned on when the “sense enable”
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`signal drives the gate of transistor 323 high, and it amplifies the voltage
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`difference between the local data lines. Id. at 3:2-8. The amplified signal
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`from the sense amplifier is then sent to a “self-timed latch” highlighted in
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`green. The self-timed latch comprises two cross-coupled inverters 331
`
`and 333 that maintain the output of the sense amplifier even after the
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`sense enable signal has been deasserted. Id. at 3:22-32.
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`26. Figure 4 of the ’208 patent, annotated below, is a timing diagram
`
`describing a memory read operation using the circuit of Figure 3. Id. at
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`3:33-35.
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`10
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`
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`27. As seen above, the precharge is deactivated (signal goes high) at about
`
`the time the column decode (CD) signal (trace 405) goes low to turn on
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`transistors 306 and 308. This connects the selected bit lines and memory
`
`cell to the sense amplifier via the local data lines (LDL and *LDL). Ex.
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`1001, ’208 patent at 3:48-50, 53-56. The logic state stored in the selected
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`memory cell (a “1” in this example) begins to pull the *LDL signal to a
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`lower voltage, and a differential voltage develops between LDL and
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`*LDL, as shown at trace 406. Ex. 1001, ’208 patent at 3:63-67; Fig. 4.
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`28. Next, “[a]t about the time that the SENSE ENABLE signal is asserted,
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`the CD signal is driven high to isolate the local data lines LDL 305 and
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`11
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`*LDL 307 from bit lines BL 205 and *BL 207, respectively.” Ex. 1001,
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`’208 patent at 4:9-12; Fig. 4 (compare rising edges of CD and SENSE
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`ENABLE). Because isolating the sense amplifier from the bit lines and
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`memory cell reduces the overall capacitance coupled to the sense
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`amplifier, the sense amplifier is able to quickly amplify the differential
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`signal on the local data lines. Ex. 1001, ’208 patent at 4:12-18. When
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`the SENSE ENABLE signal is deasserted, the differential voltage on the
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`local data lines dissipates. Ex. 1001, ’208 patent at 4:31-35. “However,
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`because of the latch function of the self-timed latch 215, the voltage level
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`of the DATA OUT signal remains latched at the low voltage level.” Ex.
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`1001, ’208 patent at 4:35-37. Thus, the self-timed latch maintains the
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`output of the sense amplifier even after the SENSE ENABLE signal has
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`been deasserted. The latch is “self-timed” because it latches the output of
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`the sense amplifier after SENSE ENABLE is asserted without requiring
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`any additional timing signal. This “allow[s] for the latch to latch a value
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`immediately after the sense amplifier provides an amplified data signal as
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`opposed to a clocked latch which has specific setup and hold time
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`requirements to be maintained in order to capture and retain the data of
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`the amplified data signal.” Ex. 1001 at 5:26-32.
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`12
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`Ex. 1002
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`
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`IV. SUMMARY OF OPINIONS
`29. Claims 1-4, 6-9, and 22-32 are unpatentable under 35 U.S.C. § 103 as
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`Declaration of Stanley Shanfield, Ph.D.
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`obvious over U.S. Patent No. 5,481,500 (“Roehr”) in combination with
`
`U.S. Patent No. 5,297,092 (“Johnson”).
`
`30. Claims 5 and 10-21 are unpatentable under 35 U.S.C. § 103 as obvious
`
`over Roehr in combination Johnson and further in view of U.S. Patent
`
`No. 6,163,193 (“Kong”).
`
`V. LEGAL STANDARDS
`31.
`I understand that for the purposes of construing claims in an inter partes
`
`review, claim terms will be given their broadest reasonable interpretation
`
`in light of the specification. I understand that claim terms are presumed
`
`to have their ordinary and customary meaning.
`
`32.
`
`I am informed that 35 U.S.C. § 103 governs the determination of
`
`obviousness. According to 35 U.S.C. § 103:
`
`A patent may not be obtained though the invention is not
`identically disclosed or described as set forth in section 102 of
`this title, if the differences between the subject matter sought to
`be patented and the prior art are such that the subject matter as a
`whole would have been obvious at the time the invention was
`made to a person having ordinary skill in the art to which the
`subject matter pertains.
`
`33.
`
`I am further informed that the first three factors to be considered in an
`
`obviousness inquiry are: (1) the scope and content of the prior art; (2) the
`
`differences between the prior art and the claims; and (3) the level of
`13
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`Ex. 1002
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`
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`ordinary skill in the pertinent art.
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`Declaration of Stanley Shanfield, Ph.D.
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`VI. LEVEL OF ORDINARY SKILL IN THE ART
`34.
`I am informed that obviousness is analyzed from the perspective of a
`
`hypothetical person of ordinary skill in the art at the time of the alleged
`
`invention.
`
`35.
`
`In my opinion, one of ordinary skill in the field of memory devices would
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`be someone with (a) a bachelor’s degree or higher in electrical
`
`engineering, physics, or a similar field, plus at least three years of
`
`experience in circuit design or memory design; (b) a master’s degree or
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`higher in electrical engineering, physics, or a similar field, plus at least
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`one year of experience in circuit design or memory design; or (c) an
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`equivalent education an and amount of relevant work and/or research
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`experience.
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`36. My opinions concerning the ’208 patent claims are from the perspective
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`of a person of ordinary skill in the art, as set forth above.
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`VII. THE INVALIDATING PRIOR ART
`A. U.S. Patent No. 5,481,500 (“Reohr”)
`37. Reohr discloses a “memory and sense amplifier with latched output.”
`
`Ex. 1005, Reohr at Abstract. Figure 4A/4B, annotated below, depicts the
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`architecture of the memory read circuity and shows bit lines (in red)
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`selectively coupled to or isolated (by isolation circuits highlighted in
`14
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`blue) from a sense amplifier. The sense amplifier (in yellow) is coupled
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`to a latching circuit (in green) that maintains the output of the sense
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`amplifier even after the sense enable signal has been deasserted. Ex.
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`1005, Reohr at Fig. 4. The precharge circuit (in purple) formed from
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`transistors 13, 14, and 15 precharges the sense lines N1 and N2 by
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`connecting them to each other and to VDD. Ex. 1005, Reohr at 7:28-33.
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`
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`38. A “cross-coupled differential sense amplifier is preferably provided by a
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`pair of cross-coupled inverters comprising complementary transistors 16,
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`18, and 17, 19, respectively.” Ex. 1005, Reohr at 7:25-28. The sense
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`15
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`enable signal (SAE) turns on transistor 21 to connect the sense transistors
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`18 and 19 to ground, turning on the sense amplifier so that it begins to
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`amplify the differential signal on the input nodes N1 and N2. Ex. 1005,
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`Reohr at 7:40-43. “Transistors 25 and 26, connected as an inverter to the
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`input of transistors 27 and 28 of inverter I2, are small, low conductance
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`transistors which are used to latch the SAE signal voltage on node N6 for
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`transistor 31.” Ex. 1005, Reohr at7: 57-60. “[I]t is important to an
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`understanding of the invention that transistor 31 provides a latching
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`function for the sense amplifier outputs.” Ex. 1005, Reohr at 8:8-10.
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`This high level on N6 maintains transistor 31 in an active,
`conductive state to maintain the sense amplifier output.
`Therefore, the SAE signal can be reduced to a very short pulse
`which need be of only sufficient duration to allow the onset of
`amplification of the voltage differential developed . . . and
`applied to the sense amplifier from the bit lines. . . .
`Accordingly, the data in the sense amplifier can be maintained
`well into the next clock cycle . . .
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`Ex. 1005, Reohr at 8:17-28. Thus, the latch formed by cross-coupled
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`inverters comprising transistors 25, 26, 27, and 28 maintains transistor 31
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`in a conducting state, which keeps the sense amplifier on, latching the
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`amplified output data, which is output through inverting buffers 32, 33
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`and 37, 36, as signals “OUT” and “OUT_N,” respectively. Ex. 1005,
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`Reohr at 7:34-36. “The latching action of transistor 31 is evident since
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`the output voltages (out and out_n) are available once SAE is asserted
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`16
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`until the precharge of the next cycle.” Ex. 1005, Reohr at 10:58-61. No
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`additional timing or enable signal is needed to latch the sense amplifier
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`output, and it is a self-timed latch, in the context of the ’208 patent.
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`39. The timing of a read operation is depicted in Figure 9 of Reohr, which is
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`shown below in annotated form:
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`40. As Reohr describes, “[S]hortly after the end of the PCN [precharge]
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`17
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`pulse, the bit decode outputs are enabled and a voltage differential begins
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`to form on the bit lines . . . . As soon as a voltage differential which is
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`reliably detectable by the sense amplifier has been developed, the SAE
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`[sense enable] signal is asserted . . .” Ex. 1005, Reohr at 10:45-51.
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`41. When the “BIT DEC” signal is deasserted, the memory cell and bit lines
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`are isolated from the sense amplifier, as can be seen from Figures 9 and
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`4A/B (signals DEC1 - DEC4 selectively connect bit lines BL1-BL4 and
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`BR1-BR4 to sense nodes N1 and N2 or isolate them from the bit lines).
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`At about the same time, the sense enable signal is asserted. This is
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`shown in Figure 9 by the curved arrow connecting the rising edge of SAE
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`and the rising edge of BIT DEC OUTPUT.
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`B. U.S. Patent No. 5,297,092 (“Johnson”)
`42. Johnson also discloses a circuit for reading a memory cell that includes a
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`sense amp, isolation circuits, and a self-timed latch. Johnson’s Abstract
`
`states:
`
`A sense amp and latch for sensing and latching data on a
`plurality of bit and inverse bit lines is provided. A sense amp
`power line which connects the sense amp to a ground line also
`decouples the bit lines from the sense amp during the
`evaluation process. The circuit allows for automatic latching of
`the data which the sense amp evaluated without requiring the
`generation of other timing signals.
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`Ex. 1006, Johnson at Abstract.
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`18
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`43. Figure 3 of Johnson discloses an embodiment of a sensing circuit, which
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`has been annotated below to indicate the various components:
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`
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`44. The precharge circuit (shaded purple) is formed from the three transistors
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`
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`driven by the precharge line (35a). This circuit equalizes and precharges
`
`the bit lines by connecting them to each other and to VDD. “In the initial
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`part of a bit line evaluation cycle, the PC lines 35a are driven low 72.
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`This causes both the left and right sides of the sense amp 30 to begin
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`charging and equalizing.” Ex. 1006, Johnson at 3:32-35. The sense
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`amplifier (30) is shaded yellow and includes transistors 52a, 54a, 52b,
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`and 54b arranged as cross-coupled inverters. Ex. 1006, Johnson at 3:57-
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`19
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`Ex. 1002
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`Declaration of Stanley Shanfield, Ph.D.
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`59 (“When a voltage is sent down the SAP [sense enable] lines, gain is
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`obtained from the cross-coupled inverters (54a, 54b, 52a, 52b).”) The
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`SAP line both enables the sense amplifier by turning on transistor 60 and
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`also isolates the bit lines from the sense amplifier by opening isolation
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`transistors 62a and 62b. Ex. 1006, Johnson at 3:46-49 (“[W]hen the SAP
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`line 35b becomes high 76, transistors 62a and 62b become substantially
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`non-conducting and, substantially simultaneously, transistor 60 connects
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`node 56 to the ground line 58.”)
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`45. Sense amplifier nodes 51a and 51b are connected to the inputs of latch
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`36. “Latch 36 includes cross-coupled NAND gates 66a, 66b with two
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`input lines 68a, 68a, and a single output line 70. The first latch input line
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`68a is coupled to the sense amp node 51a. The latch input line 68a is
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`attached to the sense amp node 51b.” Ex. 1006, Johnson at 3:23-26.
`
`“The circuit allows for the automatic latching of data when the sense amp
`
`is evaluated without requiring the generation of other timing signals such
`
`as a latch-enable signal.” Ex. 1006, Johnson at 1:61-64.
`
`46. Figure 4, annotated below, shows a timing diagram of a memory read
`
`operation.
`
`20
`
`Ex. 1002
`
`
`
`
`
`Declaration of Stanley Shanfield, Ph.D.
`
`
`
`When the difference in voltage between the two nodes 51a, 51b
`reaches a sufficient value 78, for example, 100 mV, then SAP
`goes high, after which the sense amp evaluates that the bit line
`was in a logical ‘1’ state. The output latch 36 then retains this
`evaluation.
`
`Ex. 1006, Johnson at 4:3-8. The SAP signal that enables the sense amplifier
`
`also isolates the memory cells from the sense amplifier. Because this
`
`reduces the capacitance connected to the sense amp, it is able to switch more
`
`quicky:
`
`transistors 62a and 62b are substantially non-
`Because
`conducting, the bit lines are not directly coupled to the sense
`amp 30 and latch 36 during the latching process. Because sense
`amp 30 is effectively cut off from the bit lines, no charging of
`the bit lines will occur. Thus, the sense amp 30 is exposed to a
`much lower capacitance than it otherwise would be, and thus
`evaluates more quickly.
`
`Ex. 1006, Johnson at 3:49-56.
`
`21
`
`Ex. 1002
`
`
`
`
`
`Declaration of Stanley Shanfield, Ph.D.
`
`47. The latch disclosed in Johnson is self-timed, as it automatically latches
`
`the data as soon as the sense amplifier amplifies it. Ex. 1006, Johnson at
`
`1:61-64. See also id. at claim 4 (“said output latch is perpetually enabled,
`
`such that said status signal may be output without the need for first
`
`receiving an enablement signal.”)
`
`C. U.S. Patent No. 6,163,193 (“Kong”)
`48. Kong discloses a “self-timed latch circuit for a VLSI [very large scale
`
`integration] system.” Ex. 1007, Kong at 1:8-9. Kong notes that latches
`
`synchronized by clock signals can introduce complexity because of
`
`variable time delay that can cause clock skew “which leads to serious
`
`problems such as, for example, false output latching.” Id.at 1:22-25.
`
`“Accordingly, generally a self-timed latch circuit is used for solving such
`
`problems. Since the self-timed latch circuit does not apply the clock
`
`signal, the clock skew problem and the clock dispersion costs can be
`
`reduced.” Id. at 1:27-30.
`
`49. Kong points out that self-timed latches comprising cross-coupled NAND
`
`gates, as disclosed in Johnson, were well known in the art: “FIGS. 1A
`
`and 1B are diagrams respectively illustrating a conventional active-low
`
`and active-high self-timed latch circuits.” Id. at 3:13-15. The
`
`“conventional” latch Kong discusses in Figure 1A is a standard NAND-
`
`22
`
`Ex. 1002
`
`
`
`
`
`Declaration of Stanley Shanfield, Ph.D.
`
`gate set-reset flip flop, identical to the latch disclosed in Johnson (Fig. 3,
`
`element 36), as can be seen below:
`
`
`
`50. Kong notes that the conventional self-timed latch used in Johnson “has
`
`
`
`several problems due to the back-to-back connection. More specifically,
`
`a critical path formed by the feedback connection considerably decreases
`
`a processing speed of the latch circuit.” Ex. 1007, Kong at 2:18-22.
`
`Accordingly, Kong provides “ a self-timed latch circuit that reduces the
`
`power consumption and increases the operation speed of the circuit by
`
`removing a back-to-back connection and a serial connection of transistors
`
`which lead to decrease of the operation speed.” Id. at 2:48-52. Figure
`
`2A, annotated below, discloses an “active-low self-timed latch circuit . . .
`
`comprised of a couple of inverters 100, 101, a couple of main drivers
`
`102, 104 and a static latch 103.” Ex. 1007, Kong at 3:35-40; Fig. 2A.
`
`23
`
`Ex. 1002
`
`
`
`
`
`Declaration of Stanley Shanfield, Ph.D.
`
`“The static latch 103 is comprised of two cross-coupled inverters.” Id. at
`
`3:55-56. The new latch circuit uses less power than the cross-coupled
`
`NAND gates in part because the amount of charge required to make the
`
`latch change state is reduced. Id. at 6:64-7:4.
`
`
`
`51. Kong, therefore, provides an improved latch that could be used in place
`
`of the latch disclosed in Johnson.
`
`VIII. GROUNDS FOR INVALIDITY
`A. Ground 1: Reohr and Johnson render obvious claims 1-4, 6-9, and
`22-32
`1.
`Reasons to Combine Reohr and Johnson
`52. As discussed above, both Reohr and Johnson disclose circuits nearly
`
`24
`
`Ex. 1002
`
`
`
`
`
`Declaration of Stanley Shanfield, Ph.D.
`
`identical to those claimed in the ’208 patent. Reohr and Johnson are both
`
`directed to reading data from memory cells and disclose circuitry
`
`including a sense amplifier formed from cross-coupled inverters, (Ex
`
`1005, Reohr Fig. 4 (16, 17, 18, 19); Ex. 1006, Johnson Fig. 3 (30)), a
`
`precharge circuit for equalizing and precharging the bit lines (Ex 1005,
`
`Reohr Fig. 4 (13, 14, 15); Ex. 1006, Johnson Fig. 3 (64a, 64b)), an
`
`isolation circuit for selectively isolating bit lines from the sense amplifier
`
`(Ex 1005, Reohr Fig. 4 (DEC1 - DEC4); Ex. 1006, Johnson Fig. 3 (62a,
`
`62b)), and a self-timed latch for latching the output of the sense amplifier
`
`(Ex 1005, Reohr Fig. 4 (25, 26, 27, 28, 31); Ex. 1006, Johnson Fig. 3
`
`(36)).
`
`53. A small difference between the circuit of Reohr and those of the ’208
`
`patent and Johnson is that the self-timed latch of Reohr operates by
`
`maintaining transistor 31 (Reohr Fig. 4) in a conducting state, which
`
`keeps the sense amplifier powered and operating, even after the sense
`
`enable signal has been deasserted. Ex. 1005, Reohr at 7:34-36, 10:58-61.
`
`This latch design maintains the sense amplifier output as required but
`
`would likely exhibit relatively high power consumption because the
`
`sense amplifier remains on for as long as the output needs to remain
`
`latched. In a typical memory circuit, where “a large number of bit lines
`
`25
`
`Ex. 1002
`
`
`
`
`
`Declaration of Stanley Shanfield, Ph.D.
`
`are evaluated at once, it is important to minimize current and power
`
`consumption.” Ex. 1006, Johnson at 2:66-69. One of ordinary skill
`
`would have recognized the need to minimize current consumption and
`
`would have been motivated to seek a design solution that would allow the
`
`sense amplifier to be disabled while still latching the data read from the
`
`memory cell.
`
`54. Johnson provides a latch circuit that addresses this problem. The self-
`
`timed latch of Johnson (Fig. 4 (element 36)) captures the output data of
`
`the sense amplifier and allows the sense amplifier to be switched off for
`
`the remainder of the data read cycle. See Ex. 1006, Johnson at Fig. 4
`
`(output 80 in Fig. 4D stays latched even after sense enable signal SAP in
`
`Fig. 4B has been deasserted, opening transistor 60 and turning off sense
`
`amplifier 30). One of ordinary skill would have recognized that the self-
`
`timed latch of Reohr could be replaced with the self-timed latch of
`
`Johnson in order to reduce power consumption. The cross-coupled
`
`NAND gate latch of Johnson was a circuit that was well-known in the art,
`
`and integrating it with the sense amplifier circuit of Reohr would have
`
`been well within the skill level of one of ordinary skill in the art,
`
`especially because the sense amplifier of Reohr is essentially identical to
`
`that of Johnson.
`
`26
`
`Ex. 1002
`
`
`
`
`
`Declaration of Stanley Shanfield, Ph.D.
`
`55. Thus, it is my opinion that one of ordinary skill would have been
`
`motivated to improve Reohr’s circuit by replacing its latch circuitry with
`
`that of Johnson at least because it would have provided a solution that
`
`consumed less power.
`
`Claim limitation “at about the same time as”
`
`2.
`I was asked to evaluate whether Johnson and Reohr each disclose the
`
`56.
`
`limitation “decoupling the selected one of the plurality of memory cells
`
`from the sense amplifier at about the same time as the assertion of the
`
`sense enable signal,” which appears in claim 1 of the ’208 patent.
`
`Similar language also appears in claims 12 and 22.
`
`57.
`
`I was informed that in prior litigation in which Progressive sued another
`
`party, a district court construed this term to mean “after a differential
`
`signal is generated but before the sense enable signal is deasserted,
`
`occurring within a single clock cycle.” It is my opinion that each of
`
`Reohr and Johnson discloses this limitation under the prior district
`
`court’s construction. It is also my opinion that each of Reohr and
`
`Johnson discloses this limitation under the plain meaning of “at about the
`
`same time as,” which simply means that two events occur at
`
`approximately the same time.
`
`58. Below is a table in which I compare the claim language as construed by
`
`27
`
`Ex. 1002
`
`
`
`
`
`Declaration of Stanley Shanfield, Ph.D.
`
`the prior district court to the timing diagrams of Reohr and Johnson that I
`
`discussed above. The color coding of the claim language is matched to
`
`the colored annotations in the figures. In the figures below, the time
`
`window shaded in red depicts the time from when the differential signal
`
`is generated until the sense enable signal is deasserted. The decoupling
`
`event happens within this window for both the Reohr and Johnson
`
`Prior art disclosure
`
`Ex. 1005, Reohr at Fig. 9 (annotated):
`
`systems.
`
`Construction from
`Qualcomm litigation
`decoupling . . . from the
`sense amplifier after a
`differential signal is
`generated but before the
`sense enable signal is
`deasserted, occurring
`within a single clock
`cycle
`
`28
`
`
`
`Ex. 1002
`
`
`
`Declaration of Stanley Shanfield, Ph.D.
`
`Ex. 1005, Johnson at Fig. 4 (annotated, depicting “the
`
`initial part of a bit evaluation cycle” (3:32-34), i.e., a
`
`portion of a single clock cycle):
`
`
`decoupling . . . from the
`sense amplifier after a
`differential signal is
`generated but before the
`sense enable signal is
`deasserted, occurring
`within a single clock
`cycle
`
`
`
`59. As the table above shows, both Reohr and Johnson disclose the timing
`
`relationship even under the prior district court’s narrow construction. It
`
`is also clear from the figures above that the sense enable
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