Apple 1017
`
`U.S. Pat. 6,470,399
`
`
`
`Apple 1017
`U.S. Pat. 6,470,399
`
`

`
`
`
`mu_V__,_w__.,,“.23.;3-it.......,.._,.W...
`
`
`
`
`
`
`
`Published by the Press Syndicate of the University of Cambridge
`The Pitt Building, Trumpington Street, Cambridge CB2 1RP
`32 East 57th Street, New York, NY 10022, USA
`296 Beaconsfield Parade, Middle Park, Melbourne 3206, Australia
`
`© Cambridge University Press 1980
`
`First published 1980
`Reprinted 1981(thricel, 1982, 1983 (twice), 1984 (twice)
`
`Printed in the United States of America
`
`Typeset by Science Press, lnc., Ephrata, Pennsylvania
`Printed and bound by Hamilton Printing Company, Rensselaer, New York
`
`Library of Congress Cataloging in Publication Data
`
`Horowitz, Paul, 1942-
`
`The art of electronics.
`
`1. Electronics. 2. Electronic circuit design.
`I. Hill, Winfield, joint author. II. Title.
`TK7815.H67
`1980
`621.381
`79-27170
`ISBN 0 521 23151 5 hard covers
`
`ISBN 0 521 29837 7 paperback
`
`2..-11'
`
`
`
` .35..e_....__......-__.._.—~—_———§8*~—~——§I———
`
`

`
`FlELD—EFF!5CT TRANSISTORS
`FET switches
`
`246
`
`In the second circuit, an enhancement-
`mode MOSFET does the switching. Here the
`gate circuit
`is simplified, and the circuit
`works with signals of either polarity.
`If the
`output is known to be of positive polarity
`only, the gate signal can go from ground to
`some positive voltage, with the body termi-
`nal grounded.
`See Section 6.18 for an interesting circuit
`modification that eliminates the effects of
`
`leakage currents in the FET.
`
`Multiplexers
`
`A nice application of FET switches is the
`‘‘multiplexer'' (or MUX), a circuit that allows
`you to select any of several inputs, as speci-
`fied by a digital control signal. Since a FET
`that is ON looks like a small resistor (RON),
`such a circuit is an analog (or linear) multi-
`plexer, and it will faithfully pass through to
`the output the actual voltage present on the
`selected input. Figure 6.41 shows the basic
`
`Figure 6.41
`
`address
`
`scheme. Each of the switches SWO through
`SW3 is a CMOS transmission gate of the
`type discussed in the preceding section; The
`“seleat
`logic" atecodes the address and
`‘‘enables''
`éiargon for
`"turns on")
`the
`
`addressed switch only, disabling the remain-
`ing switches. Such a multiplexer will usually
`be used in conjunction with digital circuitry
`that will generate the appropriate addresses.
`A typical situation might
`involve a data-
`acquisition instrument in which a number of
`analog input voltages must be sampled in
`turn, converted to digital quantities, and
`recorded (or become the input
`to some
`on-line computations done by associated
`computing apparatus).
`Since transmission gates are bidirection-
`al, an analog multiplexer such as this is aéso
`a "demultip|exer": A signal can be fed into
`the “output" and will appear on the selected
`“input." When we discuss digital circuitry in
`Chapters 8 and 9, you wilé, see that an
`analog multiplexer such as this can also be
`used as a “digital multiplexer/demultip|ex—
`er," since logic levels are, after all, nothing
`but voltages that happen to be interpreted
`as 1 s and Os.
`
`Typical of analog multiplexers are the
`506, 507, and 508 series and the lH6108
`and lH6116 types, 8- or 16—input MUX
`circuits that accept TTL or CMOS logic levels
`for
`the address inputs and operate with
`analog voltages up to 35 volts. The 405!-
`4053 devices in the CMOS digital family are
`analog multiplexers/demultiplexers with up
`to 8 inputs, but with 15 volt pp maximum
`signal levels.
`
`Sample-and—hoId circuits
`
`FET switches are the basic ingredients of
`“samp|e—and—ho|d"
`and “peak-detector"
`circuits. Figure 6.42 shows the idea. lC, is a
`follower to pzovide a low—img)edance repéica
`ot the input. 01 passes the signaé through
`
`dgnm
`input
`
`+15V
`
`FETinput
`
` Z +15V
`
`output
`
`
`
`+15
`wmpw
`_15 .1-1- hmd
`
`Figure 6.42
`
`
`
`

`
`247
`
`the connection shown makes it
`C,, but
`easier to eliminate offsets, at
`the risk of
`
`lC2 should be a FET—input
`reduced stability.
`op-amp, and D, should be a low-leakage
`diode, to minimize droop.
`
`6.1 5
`
`Limitations of FET switches
`
`Speed
`
`FET switches have ON resistances HON of 25
`to 200 ohms. In combination with substrate
`
`resistance
`this
`and stray capacitances,
`forms a low—pass filter that limits operating
`speeds to frequencies of a few megahertz or
`less. FETs with lower RON tend to have larger
`capacitance (up to 50pF with some MUX
`switches), so no gain in speed results.
`
`ON resistance
`
`CMOS switches operated from a relatively
`high supply voltage (15V, say) will have low
`RON over the entire signal swing, because
`one or the other of the transmission FETs
`
`will have a forward gate bias at least half the
`supply voltage. However, when operated
`with lower supply voltages, the switch's RON
`value will rise, the maximum occurzing when
`the signal
`is about halfway between the
`supply and ground (or halfway between the
`supplies,
`for dua|—supp|y voltages). Figure
`6.44 shows why. As V0,,
`is reduced,
`the
`
`n-channel
`
`p channel
`
`I
`
`
`
`
`parallel
`resistance
`
`V00
`
`0
`‘/33
`
`signal
`voltage
`
`Figure 6.44
`
`during ‘‘sample'' and disconnects it during
`"hold." Whatever signal was present when
`0, was turned OFF is held on capacitor C.
`ICZ is a high—input—impedance follower (FET
`inputs), so that capacitor current during
`‘‘hold''
`is minimized. The value of C is a
`
`compromise: Leakage currents in 0, and the
`follower cause C’ s voltage to “droop"
`during the “hold" interval, according to
`dV/dT = lmkaga/C. Thus C should be large to
`minimize droop. But 01's ON resistance
`forms a low—pass filter in combination with
`C, so C shouéd be small if high—speed signals
`are to be followed accurately.
`IC, must be
`able to supply C's charging current
`I =
`CdV/dT and must have sufficient slew rate
`to follow the input signal.
`in practice,
`the
`slew rate of the whole circuit will be limited
`
`by lC,'s output current and 01's ON resis-
`tance. See Section 6.18 for an improved
`sample—and-hold eircuit.
`
`EXERCISE 6.7
`
`Suppose lC, can supply 10mA of output
`current, and C = 0.01uF. What is the maxi-
`mum input slew rate the circuit can accu-
`rately follow? If 0, has 50 ohms ON resis-
`tance, what will be the output error for an
`input signal slewing at 0.1V/us? If the com-
`bined leakage of O, and ICZ is 1 nA, what is
`the droop rate during the “hold" state?
`
`FETs are useful in peak—detector circuits,
`in which the highest value of a waveform is
`held on a capacitor. Figure 6.43 shows one
`
`DUI
`
`H5_l"l._
`-15
`
`Figure 6.43
`
`FET input
`
`|
`
`_15
`E s
`
`possibility. IC, drives C, to the highest point
`reached by the input waveform since the last
`reset pulse applied to O,'s gate. ICZ buffers
`the output. IC, could take its feedback from
`
`FETs begin to have significantly higher ON
`resistance at V65 = 0.5 VDD,
`since for
`enhancement-mode FETs V, is at least a few
`volts, and a gate—source voltage of as much
`
`,
`
`

`
`FIELD-EFFECT TRANSISTORS
`Some additional FET circuit ideas
`
`254
`
`
`
`of 1% in each section would result in an
`overall feedthrough of 0.01% %—80dB!
`in
`the open state.
`If RON is 100 ohms,
`the
`signal is essentially unattenuated (99.7% of
`its input amplitude) when the switch is
`closed, which tneans that variations of RON
`with signal
`swing contribute negligible
`nonlinearity. To get equivalent feedthrough
`performance with a
`single stage would
`require a load resistor of 1.0k, which. would
`result
`in unsatisfactory attenuation in the
`closed state (10% attenuation), not
`to
`mention nonlinearity due to changing RON
`with signal level.
`The second circuit does the same sort of
`
`thing, using ET switches to short the signal
`to ground.
`in this case the use of several
`stages allows you to keep the series resis-
`tors reasonably small.
`to use a pair of
`A third possibility is
`switches, one in series with the signal and
`one between the output and ground, as
`shown in the third circuit in gigure 6.54. By
`alternately enabling the two switches, you
`get the best of both worlds, i.e., low feed-
`through in the OFF state and good linearity
`with negligible attenuation in the ON state.
`CMOS SPDT switches with controlled break-
`
`before—make are available commercially in
`singte packages; in fact, you can get a pair of
`SPDT switches in a single package. Exam-
`pies are the DG188, iH5042, and I!-l5142,
`as well as the DG191, lH5043, and %H5143
`(dual SPDT unéts). Because of the availability
`of such convenient SMOS switches,
`it
`is
`
`easy tc use this SPDT configuration to
`achieve excellent performance.
`
`Another !ook at the integratar
`
`In the integrator circuits in Section 6.14,
`drain—source leakage sinks a small current
`from the summing junction when the FET is
`OFF. With an ultra—low—input—current op-
`amp and |ow—leakage capacitor, this can be
`the dominant error in the integrator. Figure
`6.55 shows a clever circuit sotution. Both
`
`n—channe% F553 are switched together, but it
`may be desirable to switch 01 with gate
`voltages of zero and +15 volts so that all
`the gate leakage eftects are eliminated
`during the OFF state (zero gate voltage).
`In
`the ON state the capacitor is discharged as
`before, but with twice RON. In the OFF state,
`
`Figure 6.55
`
`02's smatl leakage passes to ground through
`R2 with negligible drop. There is no leakage
`current at
`the summing junction because
`01's source, dtain, and substrate are all at
`the same voltage. Compare this circuit with
`the “zero—leakage" peak detector in Section
`3.15.
`
`EXERClSE 6.8
`
`Assume that 0, and C22 in Figure 6.55 be-
`have like 10,000M resistors when OFF. Cal-
`culate the rate at which the integrator's out-
`put will drift, due to EET leakage, for both
`this configuration and the simple EET reset
`switch circuit (Fig. 6.40), when the integta—
`tor's output is at + 10 volts.
`
`Another look at sample-and—hoId
`circuits
`
`Figure 6.56 shows an improved sample-
`and=hold circuit. 02 and 03 are parallel
`complementary switches, ntaintaining low
`ON resistance for
`all signal
`levels. 0,
`is
`turned on during HOLD to prevent saturation
`in the input op-amp, with its usual problems
`of s|ew—rate—limited recovery time. £2, could
`be replaced by a pair of back—to—back diodes.
`The second op—amp should have a FET input
`for low droop.
`The same trick used to eliminate the
`
`effects of drain—source leakage in the inte-
`grator (Fig. 6.55) can be used to advantage
`here. There's a hint in Exercise 6.9.
`
`

`
`
`
`255
`
`limuu
`
`out
`
`
`
`
`trim offset
`
`control input
`
`FET input
`
`+15
`track
`-15 IL. hold
`
`Figure 6.56
`
`EXERCISE 6.9
`
`Modify the sample—and-hold circuit to elimi-
`nate droop caused by source—drain leakage
`in 02 and 03. Hint: You have to bootstrap
`the junction of series FETs at the capacitor
`voltage; however, don't take your bootstrap
`voltage directly from the capacitor! V
`
`6.19
`
`BiFET integrated circuits
`
`Integrated circuits that combine bipolar tran-
`sistors and FETs are known as BiFET lCs.
`
`They offer the best of both worlds, combin-
`ing traditional linear lC technology (op—amps,
`comparators, etc.) with the ultralow input
`current of FETs. We will rather arbitrarily
`divide BiFETs into “BiJFET" and BiMOS.
`
`p—ChanneI—JFET-input op-amps
`
`lt turns out that p—channel JFETs are the
`easiest to fabricate in the same process with
`
`V+
`
`100yA
`
`inputs{
`
`Figure 6.57
`
`to second stage
`
`bipolar transistors. They are low—pinch—off
`FETs, with a VP of 1
`to 2 volts. The 355-
`357 series of FET op-amps provides popular
`examples of this kind of chip. The input
`stage consists of a pair of p—channel JFETs
`with their sources returned to V+ with a
`current source (Fig. 6.57). There are a
`couple of interesting points about the input
`circuit. First, it turns out that there is a value
`of drain current for JFETS at which ID versus
`V53 has zero temperature coefficient
`(See
`Fig. 6.11). This is typically in the range of
`25uA to 200uA, and it
`is the current at
`which the input FETs are cleverly operated in
`the 355-357, to keep drifts of offset voltage
`minimized. The resulting temperature coeffi-
`cient of offset voltage, 5/.cV/°C (typ),
`is
`quite good even by bipolar transistor stan-
`dards (it’s a lot better than that of the 741,
`for instance).
`The second point to note is that these
`low values of drain current are really close to
`pinch-off, which means that
`the gate is
`positive by a volt or so relative to the source.
`As a result, the common—mode input range
`typically extends to the positive supply rail,
`and even a bit beyond. This is a useful virtue
`in a number of applications, e.g., constant-
`current supplies with sensing at
`the high
`side.
`
`The rest of the op—amp is constructed
`with bipolar transistor circuitry: a differential
`stage with Miller compensation capacitor,
`
`

`
`421
`
`CMOS MU)‘
`
`SAMPLE/HOLD
`NSC LF398
`
`
`
`Harris
`HI-506
`
`_|_1ooop1=
`"‘ CH
`
`I
`
`SAMPLE
`I
`
`HOLD
`
`.
`
`_,‘2|120
`
`21
`22|23
`24
`
`
`
`analog __{.|25
`Input
`25
`signals
`11
`(HOV)
`10
`9.
`——8
`7
`6
`5'
`4
`
`3
`Sig
`GND
`
`Jg
`Sig
`in
`
`4
`
`5
`
`19 20 35 36
`
`analog devices
`ADC~12QZ-003
`
`CONVERT
`
`STATUS
`
`33
`
`READY
`
`MSB —j——data————— LSB
`
`72 7Ts7 65 63 51 58 56 54 52 50 48
`
`I
`
`.
`.
`digital output
`
`12 bits, offset binary
`
`14 15 13 17
`
`'
`
`\
`II
`Y
`
`
`
`E
`
`A
`
`l
`
`::,‘3'r‘:S:'
`
`_
`signal
`common
`
`I
`l
`4:
`c<_>r1ne_ct to
`digital GND
`at SOUFCG
`
`Figure 9.47
`
`START
`
`A 12-bit 16-channel successive—approximation A/D
`converter system (50/.Ls/conversion).
`
`ations of this type when shopping for linear
`switches. They sometimes involve a com-
`promise. For example, “break-before—make"
`results in a slower switching-time specifica-
`tion, since the “make" must be delayed to
`allow the switch to open.
`The multip£exer’s single analog output
`drives an LF398 sample/hold IC. The LF398
`settles in 4;Ls with a 1000pF hold capacitor
`and droops
`less than 10uV during the
`subsequent 40p.s A/ D conversion. The
`device controlling this circuit normally
`
`asserts an address and gives a START pulse.
`The one—shot
`then generates
`a
`10/.13
`SAMPLE pulse (long enough for the S/H
`output to stabilize), at the end of wraich the
`A/
`gegins its conversion. The conversion is
`compii e 40;.Ls later, at which time READY
`goes HIG .Iotal elapsed time is 50/.Ls/in-
`put, or 20,000 conversions per second.
`Since the A/D module has been strapped for
`20 volt offset mode, the input range is — 10
`to +10 volts, with — 10 volts input giving
`an output of 0 counts, zero volts input giving