United States Patent [19]
`Compton
`
`US005442465A
`Patent Number:
`[111
`[45] Date of Patent:
`
`5,442,465
`Aug. 15, 1995
`
`[54] APPARATUS AND METHOD FOR
`S‘IgwCIfEOLLING A LINEAR IMAGING
`
`[56.]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`>
`[75] Inventor: John T. Compton, LeRoy, NY.
`.-
`
`_
`[73] Asslgnw Eastman Kodak Company,
`Rochester, NY.
`
`21 A 1. N .1 29s 25
`[
`1
`pp
`°
`’7
`
`_
`.
`[22] Flled‘
`
`Aug‘ 31’ 1994
`
`............ _. H04N 1/03; H04N 1 / 191
`[51] Int, Cl.6
`[52] US. Cl. .................................. .. 358/482; 358/483;
`358/494; 250/208.1; 348/294; 348/295;
`348/297; 348/298; 348/324
`Field of Search ............. .. 358/483, 482, 494, 471,
`358/443, 445, 444, 447, 513, 514; 250/2081;
`348/294, 295, 297, 298, 324
`
`[58]
`
`4,969,053 11/1990 Cuta et a1. ........................ .. 358/471
`5,029,019 7/1991 Yoshihare et a1. ................ .. 358/447
`5,113,454 5/1992 Marcantonio et a1. .
`5,130,819 7/1992 Ohta .................................. .. 358/445
`5,191,443 3/1993 Nagaoka ..... ..
`.. 358/444
`5,239,388 8/1993 Matsumoto ....................... .. 358/44-4
`,
`_
`Przmary Examzner-Scott A. Rogers
`Attorney, Agent, or Firm-—Francis H. Boos
`[57]
`ABSTRACT
`
`A CCD linear imager is dynamically controlled on a
`pixel-by-pixel basis by a line-related map of control
`words stored in memory with individual control words
`addressed by a pixel counter operating in synchronism
`with processing of each imaging pixel in the CCD.
`Multiple control word maps may be stored in memory
`for programmed selection “on the ?y” to vary the oper
`ating control of the CCD on a line-by-line basis.
`
`6 Claims, 2 Drawing Sheets
`
`LINEAR IMAGER IO
`
`20
`
`REFERENCE _
`S/H
`
`LINER
`MOTION BETWEEN
`SUBJECT AND IMAGER
`
`67
`
`68
`
`O
`
`D
`
`6!
`
`CWL
`ES
`
`CONTROL
`WORD
`
`FIFO
`MEMORY
`
`ADC
`
`.
`
`45
`
`STATE DECODER
`
`5C
`CLEAR COUNT our
`S TATE COUNTER
`CLOCK
`CK
`
`54
`
`LATCH
`
`MAP LATCH
`
`55
`57
`
`MEMORY
`ADDRESS IN
`
`CLEAR
`
`COUNTOUT
`PIXEL COUNTER
`DATA
`
`53
`
`FF
`BU ER
`
`04m
`sus
`J1 PROCESSOR
`
`Apple 1027
`U.S. Pat. 9,189,437
`
`

`
`U.S. Patent
`
`Aug. 15, 1995
`
`Sheet 1 of 2
`
`5,442,465
`
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`U.S. Patent
`
`Aug. 15, 1995
`
`Sheet 2 of 2
`
`5,442,465
`
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`
`1
`
`5,442,465
`
`APPARATUS AND METHOD FOR CONTROLLING
`A LINEAR IMAGING DEVICE
`
`FIELD OF THE INVENTION
`The invention relates generally to the ?eld of ?lm
`scanners and, in particular, to apparatus and method for
`controlling the operation of linear imaging devices in
`such scanners.
`
`15
`
`20
`
`BACKGROUND OF THE INVENTION
`Modern ?lm scanners typically employ a linear imag
`ing device such "as a charge-coupled-device (CCD) for
`scanning ?lm images to generate digital signals repre
`sentative of the image information. A linear charge
`coupled device (CCD) imager contains a linear array of
`light detecting sites (hereafter “imaging pixels”) which
`accumulate charge depending on the light energy pro
`jected onto them. After some charge accumulation
`time, the charges in the light detecting imaging pixels
`are transferred to a charge shifting structure so that the
`charges may be shifted out of the CCD and measured
`by some means in order to form a representation of the
`image projected onto the CCD. There are a number of
`signals which control the operation of the imager: clock
`25
`signals which cause the charge to be shifted out of the
`imager, a transfer signal which causes the charge from
`the imaging pixels to be transferred to the shift struc—
`ture, and one or more signals which electronically con
`trol exposure.
`Typically, the control signals for the imager will be
`generated by a programmable logic device (PLD) or an
`application speci?c integrated circuit (ASIC). A
`counter circuit with a decoder is used to indicate when
`the charge clocking and transfer signals should be oper
`35
`ated during the scan line. A counter with a reload value
`is used for each exposure control. These structures
`consume signi?cant resources within a PLD or ASIC.
`Additionally, since they are embedded in the PLD pro
`gram or the design of the ASIC, the structures are ei
`ther in?exible or ?exibility is gained at the cost of in
`creased complexity and more resources.
`If it is desired to make a change in the timing of con
`trol signals to a CCD imager, and the timing is embed
`ded in the design of a PLD or ASIC, then the PLD or
`ASIC component must be physically removed from the
`system and replaced with an updated component. If this
`change is required as a ?eld upgrade, the costs to up
`grade will be signi?cant. Additionally, if the component
`is an ASIC, signi?cant costs may be incurred in modify
`ing the design. There is therefore a need for an alterna
`tive, less costly and more ?exible manner of controlling
`linear imaging devices when the control events occur
`during a line and this invention satis?es this need.
`
`40
`
`45
`
`SUMMARY OF THE INVENTION
`In accordance with the invention, therefore, there is
`provided apparatus for controlling operation of a linear
`imaging device having a line of light-responsive imag
`ing pixels, wherein the apparatus comprises pixel
`counter means for supplying pixel counts correspond
`ing to individual pixels in the imaging device; and
`means for supplying a map of operating control words,
`the control words each comprising programmably vari
`able bit content de?ning pixel-by~pixel operating char
`acteristics of the line of imaging pixels. The apparatus
`further includes memory means for storing the map of
`control words at memory addresses corresponding to
`
`55
`
`60
`
`65
`
`2
`the pixel counts; and means for outputting the control
`words from the memory to the imaging device in syn
`chronism with the pixel counts to control the operation
`of the imaging device on a pixel-by-pixel basis in accor
`dance with the bit content of each control word.
`The method of the invention comprises providing a
`map of operating control words each of which com
`prises programmably variable bit content de?ning pixel
`by-pixel operating characteristics of a line of imaging
`pixels in a linear imaging device; storing the control
`words in imaging pixel related address locations in a
`memory and accessing said control words from the
`memory on a pixel-by-pixel basis and using the accessed
`control words to control operation of the imaging de
`vice on a pixel-by-pixel basis.
`It will be appreciated that, by utilizing a list of control
`words in a memory for pixel-by-pixel control of the
`operation of a linear imaging device, ?exibility is gained
`and PLD or ASIC resources and size are reduced at the
`same time.
`These and other aspects, objects, features and advan
`tages of the present invention will be more clearly un
`derstood and appreciated from a review of the follow
`ing detailed description of the preferred embodiments
`and appended claims, and by reference to the accompa
`nying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`In the drawings:
`FIG. 1 is a block diagram of a ?lm scanner system
`including imaging device control apparatus of the pres
`ent invention.
`FIG. 2 is a timing diagram useful in explaining the
`operation of the system of FIG. 1.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`FIG. 1 shows an arrangement of circuit elements in
`the signal processing circuitry of a CCD based linear
`scanner. A linear CCD imaging device 10 integrates the
`charges produced by each imaging pixel in the CCD for
`a period of time and then transfers the charges to a
`shifting structure so that the charges can be shifted out
`of the CCD in a serial fashion. The signal produced by
`the CCD for each imaging pixel comprises two phases:
`a reference phase followed by a video phase. The refer
`ence phase provides a reference level against which the
`video phase that follows may be compared. The video
`phase represents the magnitude of charge accumulated
`at the imaging pixel. The serial signal coming from the
`CCD 10 is ampli?ed by ampli?er 11, the output of
`which goes to a subtracter circuit 22 and a reference
`sample-and-hold circuit 20. The reference sample-and
`hold 20 samples the signal from the CCD during each
`image pixel’s reference phase. The subtracter 22 re
`moves the sampled and held reference signal from the
`subsequent video phase. Hence, the output of the sub
`tracter 22 is normalized to the reference level. This
`normalized signal is sampled by a video sample-and
`hold circuit 23 during the video phase of the signal
`provided by the imager.
`The sampled-and-held normalized video signal at the
`output of video S/H 23 is operated on by a multiplier
`circuit 25 and a summer circuit 27. These two circuits
`provide gain and offset compensation for variations in
`the video signal caused by such factors as variations in
`imaging pixel sensitivity, non uniformity of illumina
`
`

`
`5,442,465
`3
`tion, variations in signal offset and the like. The digital
`to-analog converter 26 provides the gain correction
`value for multiplier 25 and the digital-to-analog con
`verter 28 provides the offset correction value for sum
`mer 27. Data representing the offset and gain compensa
`tion values are provided to the two analog-to-digital
`converters 25 and 27 on a pixel-by-pixel basis with the
`arrival of the normalized video signal for each imaging
`pixel of CCD 10 by means of pixel counter 50, RAM
`memory 52, and gain/offset data latch 29. The pixel
`10
`counter 50 increments synchronously with readout of
`the imaging pixel signals from the CCD 10. The output
`of pixel counter 50 is used to provide an address to
`memory 52 which holds gain and offset values for each
`imaging pixel. The gain and offset data output from the
`memory is latched by data latch 29 which provides the
`data to digital-to-analog (D/A) converters 26 and 28. A
`buffer circuit 53 allows a microprocessor 100 to gain
`access to memory 52 in order to change the gain and
`offset values as the result of a calibration process. The
`20
`output of summer circuit 27 is coupled to analog-to
`digital converter 30 wherein the normalized and gain/
`offset-corrected video signal is converted to a numeric
`value which is then written to the FIFO memory 45 for
`readout and subsequent utilization by microprocessor
`100. The single CCD output and related signal process
`ing circuits as just described would provide a mono
`chrome video signal. For a three color video signal, the
`CCD 10 would comprise three in-line CCD’s each pro
`vided with a separate color ?lter, such as red, green and
`blue, and the outputs of each linear CCD would be
`coupled to separate processing circuits.
`Timing of the various CCD and signal processing
`functions is determined by state control signals pro
`vided from state decoder 55. These state control signals
`are illustrated in FIG. 2 showing a sequence of twenty
`operating states occurring during the processing of each
`imaging pixel in CCD 10. Referring jointly to FIGS. 1
`and 2, a clock signal CK from clock generator 58 causes
`state counter 54 to produce a sequential count data
`40
`signal SC applied to the input of state decoder 55 which
`operates to decode the state count SC to produce the
`state control signals. The phase control raw (PCR)
`signal is applied to AND circuit 61 during states 11
`through 0 (next sequence) to perform transfer of the
`image pixel signal out of the CCD. Actual timing of the
`phase control signal operation is determined by the
`phase enable (PE) signal from a control word latch 60
`as will be described in more detail subsequently. The‘
`reference sample-and-hold operation is performed by
`50
`the RH state signal during states 6-9 and the video
`sample-and-hold is performed by the VH state signal
`during states 16—19. The GOL state signal causes latch
`ing of the gain and offset data from memory 52 into data
`latch 29 during state 7. State control signal ADC ena~
`bles analog-to-digital converter 30 to convert the ana
`log image pixel signal during state 4 and the FIFO write
`raw (FWR) state control signal is applied to AND cir
`cuit 62 to allow writing of pixel data into FIFO memory
`45 when enabled by a FIFO write enable (FWE) signal
`60
`from control word latch 60. It will be appreciated that
`because of the serial nature of the signal processing, the
`illustrated state operations are not being performed on
`the same pixel data. For example, during a given pixel
`processing twenty state period, the enabled state signal
`PCR+PCE results in the transfer of pixel signal “n” out
`of CCD 10. In turn, state signal GOL latches gain/off
`set data for pixel “n” which state signals RH and VH
`
`Bit
`
`0
`
`25
`
`1
`
`2
`
`Name
`
`Function
`
`LP
`
`FWE
`
`PCE
`
`Last Pixel - Reset pixel counter 50 when the
`last state signal LS is provided by state
`decoder
`FIFO Write Enable - Allow FIFO write raw
`signal FWR from state decoder 55 to write data
`from A/D converter 30 into FIFO memory 45
`Phase Clock Enable - Allow phase clock raw
`signal PCR from state decoder 55 to be sent to
`linear imager 10
`Transfer Gate - Transfer charge from the light
`detecting sites to the charge shifting
`structure of linear imager l0
`Exposure End - End the exposure cycle in
`linear imager l0
`Exposure Start - Start the exposure cycle in
`linear imager 10
`
`4
`are currently sampling. State signal ADC causes A/D
`converter 30 to convert the previously sampled/com
`pensated signal 'for pixel “n- l” and the enabled state
`signal FWR+FWE writes previously converted pixel
`data for pixel “n- 1” into FIFO memory 45.
`Having described the general structure and operation
`of the CCD signal processing circuit, there will now be
`described the apparatus for controlling the operation of
`the linear CCD 10 in accordance with the invention.
`Means for supplying a bit map of control words to be
`used in controlling the operation of CCD 10 includes
`microprocessor 100 and buffer 53. The control words
`each comprise programmably variable bit content de
`?ning pixel-by-pixel operating characteristics of the
`CCD 10. The architecture of a 6-bit control word is set
`forth in Table I which summarizes the functions of the
`bits within the control word. As will be seen, for a CCD
`having a line of 530 imaging pixels, a bit map of 530 of
`these control words is used to control the operation of
`the CCD for one entire scan line of the CCD.
`TABLE I
`
`The apparatus of the invention further includes mem
`ory means, including memory 52 for storing the bit map
`of control words at memory addresses corresponding to
`individual imaging pixels in CCD 10. Address means,
`including pixel counter 50, is provided for supplying a
`sequence of pixel counts corresponding to the individ
`ual imaging pixels in the CCD for use in accessing the
`stored bit map of control words on a pixel-by-pixel
`basis. To provide microprocessor 100 access to the
`memory 52, the pixel counter 50 is disabled from count
`ing and an address is loaded directly into pixel counter
`50 by microprocessor 100; then buffer 53 is enabled so
`that the microprocessor 100 can write data to memory
`52 at the memory location speci?ed by the address
`previously loaded into pixel counter 50. To provide for
`multiple bit maps, two of the most signi?cant bits
`(MSB) of the address data are provided from the micro
`processor 100 to state decoder 55 via map latch 56 and
`latch 57 for use in selecting from within memory 52 the
`control word bit map to be used in controlling the oper
`ation of the CCD during generation of the next line of
`signal data in CCD 10. It is noted that the “last state” bit
`(LS) of the state control signal from state decoder 55 is
`used to advance the count of the pixel counter 50 and
`the combination of a “last pixel” (LP) signal from latch
`60 with the “last state” signal (LS) is used to clear the
`pixel counter and latch the MSB address data for the bit
`map to be used in pixel-by-pixel control of the next line
`of signal data generation in CCD l0.
`
`55
`
`65
`
`

`
`6
`TABLE II-continued
`Control
`Word Bits
`543210
`
`Line Events
`
`Pixel
`Type
`
`000110
`1001 10
`000110
`
`000110
`010110
`000110
`
`000110
`000110
`000100
`
`000100
`
`000100
`
`000000
`
`001000
`
`001000
`
`000001
`
`100100
`
`Imaging
`Imaging
`Imaging exposure start
`Imaging
`Imaging
`Imaging
`Imaging exposure end
`
`Imaging
`Imaging
`Test &
`dummy
`Test & write to FIFO disabled
`dummy
`
`Test &
`dummy
`Test &
`dummy
`Test & phase clock disabled
`dummy
`Test & transfer charge to
`dummy shifting structure
`Test &
`dummy
`Test & transfer charge to
`dummy shifting structure disabled,
`reset pixel counter
`
`Pixel
`Counter
`
`248
`249
`250
`
`373
`374
`375
`
`488
`489
`490
`
`491
`
`498
`
`499
`
`500
`
`501
`
`502
`
`503
`
`25
`
`5,442,465
`5
`Control word data latch 60 in conjunction with the
`control word latch (CWL) state signal from state de
`coder 55 comprises means operating in sequence with
`the pixel counter 50 for outputting the control words
`from the memory 52 to the imaging CCD 10 on a pixel—
`by-pixel basis to control the operation of the imaging
`device in accordance with the bit content of each con
`trol word.
`Considering now the operation of the apparatus of
`the invention, a control word latch 60 receives a map of
`10
`operating control words from memory 52 which are
`outputted on a pixel‘by-pixel basis to the imager 10 to
`control the operation of the imager 10 in accordance
`with the bit content of each control word. The control
`words in each map, which are supplied by microproces
`sor 100 via buffer 53, each comprise programmably
`variable bit content de?ning pixel-by-pixel operating
`characteristics of the imager 10. The map of control
`words is stored in memory 52 at memory addresses
`corresponding to the pixel counts provided by pixel
`counter 50. Multiplemaps of control words may be
`stored in memory 52. Appropriate map location address
`information is provided by two bit address code from
`microprocessor 100 stored in map latch 56. At the end
`of each processed line of pixel data from the CCD 10,
`the map address code in latch 56 is latched into latch 57
`to provide two of the most signi?cant bit MSB map
`address information via state decoder 55 to memory 52
`which serves to select the control word map for use in
`the next line of imager processing. It may be noted that
`the state decoder 55 may provide alternative MSB map
`address information during certain states of each pixel
`in order to provide access to a table of gain/ offset data
`values stored in memory 52. The output of pixel counter
`50 provides the least signi?cant bits LSB in the address
`information which serves to address the individual con~
`trol words on a pixel-by-pixel basis for transfer to con
`trol word latch 60.
`Table II, below, presents an example control word
`map based on the bit functions from Table I. In the
`timing of state decoder outputs as shown in FIG. 2, the
`control word is latched by state control signal (CWL) at
`the end of each pixel time; hence, the control word for
`a given pixel count actually takes effect during the next
`pixel. Additionally, since the signal for a given pixel is
`actually A/D converted during the next pixel time,
`writing the given pixel’s data to the FIFO memory
`should take place after conversion is complete in the
`next pixel as previously explained. Noting these laten-v
`cies and pipeline effects, a description of the example
`control word map can be provided.
`TABLE II
`
`In the example control word map in Table II, the ?rst
`ten pixels (pixel counts from 0 to 9) of the linear imager
`are test or dummy pixels. The phase clock is enabled by
`the PCB bit in bit position 2 of the control word applied
`via AND circuit 61 in order to shift the signal from
`these test and dummy pixels out of the linear imager.
`Note that the PCB bit which affects the pixel for pixel
`count 0 is actually set in the last control word in the
`map (pixel counter=503). The next 480 pixels (pixel
`counts from 10 to 489) are actual imaging pixels. The
`phase clock is still enabled by the PCB bit in bit position
`2 of the control words to shift the signal from these
`actual pixels out of the imager. Additionally, the signal
`is converted and written to the FIFO memory for these
`pixels. Hence, the control word for pixels counts from
`10 to 489 has the FWE bit in bit position 1 set so that
`writes to the FIFO memory will take place during pixel
`counts 11 through 490 after A/D conversion takes
`place. After the imaging pixels come another ten test or
`dummy pixels; and the phase clock continues to be
`enabled for pixel counts 490 through 499. The control
`words for pixel counts 499 through 502 has the F WE bit
`cleared so that the phase clock is disabled for pixel
`counts 500 through 503. The TG bit in bit position 3 is
`set in the control word for pixel counts 500 and 501 so
`that the accumulated charges in the light detecting sites
`can be transferred to the charge shifting structure dur
`ing pixel counts 501 and 502. Pixel 502 has the LP signal
`in bit position 0 set so that the pixel counter will be reset
`to zero at the end of pixel count 503. Hence, at the end
`of pixel count 503, the readout of the control map con
`tinues at pixel count 0 of the next ensuing control word.
`The exposure signal for the imaging pixels may be
`turned on at any time except when charge is being trans
`ferred from the imaging pixels to the charge shifting
`structure in the CCD. In the example control word map
`in Table II, the exposure for the next scan line begins
`with pixel count 0 by setting the ES bit in bit position 5
`
`50
`
`Pixel
`Counter
`
`Control
`Word Bits
`543210
`
`Pixel
`Type Line Events
`
`0
`
`1
`
`2
`
`9
`
`10
`11
`123
`124
`125
`
`000100
`
`000100
`
`000100
`
`000100
`
`000110
`000110
`000110
`010110
`000110
`
`Test & exposure start, phase
`dummy clock enabled
`Test &
`dummy
`Test &
`dummy
`
`Test &
`dummy
`Imaging
`Imaging write ti FIFO
`
`Imaging Imaging
`Imaging
`Imaging exposure end
`
`55
`
`60
`
`65
`
`

`
`5,442,465
`7
`of pixel count 503 from the last control word in the bit
`map for the previous scan line. The control word for
`pixel count 124 has the EB bit set at bit position 5 in
`order to stop the exposure at the beginning of pixel
`count 125. The control word at pixel count 249 has the
`ES bit set at bit position 4 in order to begin another
`exposure cycle at the beginning of pixel count 250; the
`control word at pixel count 374 has the BE bit set in
`order to stop the exposure at the beginning of pixel
`count 375. Hence, there are two complete exposure
`cycles controlled by this map; exposure is actually
`turned on during 50 percent of each exposure cycle.
`In FIG. 1, the actual exposure signal to the linear
`CCD imager 10 is provided by D-type ?ip ?op 66
`which is controlled by AND circuit 67 and OR circuit
`68. Table III is a truth table showing the operation of
`AND circuit 67 and OR circuit 68. It is evident from the
`truth table that D-type ?ip ?op 66 will retain its current
`state unless commanded to become a logic 1 by the
`exposure start signal ES or commanded to become a
`logical zero by the exposure end signal EE; addition
`ally, it is evident that the exposure end signal EE takes
`precedence over the exposure start signal ES if both are
`logical 1. Following is a detailed description of the
`operation of D-type ?ip ?op 66, AND circuit 67, and
`OR circuit 68.
`
`Exposure
`Exposure
`End Signal Start Signal
`EE
`ES
`0
`0
`O
`0
`0
`1
`1
`X
`
`X = Don't Care
`
`TABLE III
`D-Type
`D-Type
`Flip Flop Exposure
`Flip Flop
`Output 0 Input D Function
`O
`0
`not exposing
`1
`1
`exposing
`X
`1
`start exposure
`X
`0
`stop exposure
`
`35
`
`Note that the exposure signal could be controlled
`directly by a single bit from the control word (in much
`the same way the TG signal works). However, if this
`arrangement were used in the control word bit assign
`ments of Table I and the example control word map of
`Table II, then, in order to change the exposure from 50
`percent to 25 percent, the single exposure bit would
`have to be cleared in 125 control words. By using two
`bits, one to start exposure (ES) and one to stop exposure
`(EE), changing exposure is greatly simpli?ed. In order
`to change exposure using this scheme requires clearing
`the BE bit and setting a different EE bit for each expo
`sure cycle. Hence, only 4 control words would be re
`quired to be changed in this example control word map
`which has two exposure cycles.
`Note also that the total duration of the line, the num
`ber of test and dummy pixels, the number of imaging
`pixels, and the number of exposure cycles can be
`changed very simply in this scheme. It may be desirable,
`for example, to extend the total duration of a line in
`order to allow additional time for exposure (i.e., accu
`mulation of charge in the light detecting sites). This can
`be accomplished very simply by adding more control
`words during the test and dummy pixels following the
`imaging pixels and by adjusting the exposure cycles to
`cover this longer line duration. Since writes to the
`FIFO memory are suppressed during. this additional
`time, the rest of the system is unaffected by the longer
`line duration.
`In the preferred embodiment shown in FIG. 1, there
`is a map latch 56 to which the microprocessor 100 can
`write two bits. These two bits are subsequently latched
`by latch 57 at the end of a line and provided to the state
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`15
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`20
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`25
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`8
`decoder 55 for incorporation into the MSB’s sent to the
`memory 52 which contains the control word map. This
`allows the microprocessor to select from among a plu
`rality of different control word maps in the memory 52.
`The number of available bit maps is determined by the
`size of the memory. The latch 7 is updated at the end of
`the line so that transition from one control word map to
`another occurs at a known point in the control word
`map, namely at a pixel count of 0. This ability to change
`control word maps “on the ?y” without signi?cant
`additional circuit complexity provides signi?cant bene
`?ts. It may be desired, for example, to write data from
`every other pixel into the FIFO memory during some
`modes of operation and to write data from all pixels
`during other modes of operation. Or it may be desired
`to be able to quickly change exposure from one preset
`value to another without stopping the signal processing
`operation in order to write new exposure control bits
`into the memory 52. Or it may be desired to switch from
`a map where pixel data is written to the FIFO memory
`(an active mode) to a map where no pixel data is written
`to the FIFO memory (an idle mode). The map latch 56
`and latch 57 permit the operation of these useful fea
`tures.
`The memory containing the control words may be an
`erasable programmable read only memory (EPROM)
`which could be removed and reprogrammed to allow
`different arrangements of control bits, or the memory
`could be a read/write memory so that the control bits
`could be changed in the system. This latter arrangement
`would be preferable if the control bits were being used
`for exposure control asit would allow the exposure to
`be changed in real time.
`The control structures which generate the signals to
`the imager are greatly simpli?ed in this scheme. As an
`example, each exposure signal in a previous PLD con
`trol device required eight logic cells for a counter, eight
`logic cells for a reload register, and a logic cell for the
`control output in addition to several logic cells control
`ling when to reload the counter based on the pixel
`count. In the arrangement of the invention, a single
`logic cell provides the exposure control to the CCD; it
`is set by the start exposure bit and cleared by the stop
`exposure bit in the control word. Hence, a minimum of
`sixteen logic cells per exposure signal are eliminated.
`With the previous PLD control device, the number of
`exposure cycles per line and the total duration of the
`line were ?xed; with this control scheme, both things
`are easily changed by the placement of the bits control
`ling exposure and reset of the counter.
`The invention has been described with reference to a
`preferred embodiment. However, it will be appreciated
`that variations and modi?cations can be effected by a
`person of ordinary skill in the art without departing
`from the scope of the invention.
`PARTS LIST
`10 linear CCD imager
`11 ampli?er
`20 reference sample-and-hold
`22 subtractor circuit
`23 video sample-and-hold
`25 multiplier circuit
`26 gain D/A converter
`27 adder circuit
`28 offset D/A converter
`29 gain/offset data latch
`30 video signal A/D converter
`
`

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`cordance with the bit content of each control
`wordv
`2. The apparatus of claim 1 in which said means for
`supplying bit map control words supplies a plurality of
`maps of control words de?ning different operating
`characteristics of said imaging device for different lines
`of imaging and wherein there is included map address
`means for selecting one of said map of control words for
`an ensuing line of imaging operation.
`3. Apparatus according to claim 1 wherein said map
`of control words includes a ?rst bit controlling start of
`exposure of said imaging pixels and a second bit control
`ling end of exposure of said imaging pixels, whereby
`exposure cycle of a line of imaging pixels may be inde
`pendently controlled as a function of map bit content.
`4. A method of controlling operation of a linear imag
`ing device comprising the steps of:
`providing a map of operating control words each of
`which comprises programmably variable bit con
`tent de?ning pixel-by-pixel operating characteris
`tics of a line of imaging pixels in the linear imaging
`device;
`storing the control words in imaging pixel related
`address locations in a memory;
`accessing said control words from the memory on a
`pixel-by-pixel basis; and
`using the accessed control words to control operation
`of the imaging device on a pixel-by~pixel basis.
`5. The method of claim 4 wherein a plurality of differ
`ent maps of control words are stored in the memory and
`the selected map of control words to control operation
`of a next ensuing line of imaging pixels is changed at the
`end of a current line of imaging pixels.
`6. The method of claim 4 wherein the map of control
`words is supplied with a ?rst bit position which initiates
`an imaging pixel exposure cycle and a second bit posi
`tion which ends the imaging pixel exposure cycle.
`* * * * *
`
`45 FIFO memory
`50 pixel counter
`_52 memory
`53 buffer
`54 state counter
`55 state decoder
`56 map latch
`57 latch
`58 clock
`60 control word latch
`61 AND circuit
`62 AND circuit
`65 AND circuit
`66 D-type ?ip ?op circuit
`67 inverting AND circuit
`68 OR circuit
`100 microprocessor
`What is claimed is:
`1. Apparatus for controlling operation of a linear
`imaging device having a line of light-responsive imag
`ing pixels, the apparatus comprising:
`pixel counter means for supplying pixel counts corre
`sponding to individual pixels in the imaging device;
`means for supplying a map of operating control
`words, the control words each comprising pro
`grammably variable bit content de?ning pixel-by
`pixel operating characteristics of said line of imag
`ing pixels;
`memory means for storing said map of control words
`at memory addresses corresponding to said pixel
`counts; and
`means for outputting said control words from said
`memory to said imaging device in synchronism
`with said pixel counts to control the operation of
`the imaging device on a pixel-by-pixel basis in ac
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`25
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`35
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`45
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`55
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`60
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`65