United States Patent
`
`[19]
`
`Sangveraphunsiri et al.
`
`[11] Patent Number:
`
`5,590,375
`
`[45] Date of Patent:
`
`Dec. 31, 1996
`
`|||||||ll||Ill|l|||||||||I||||||||||||I||||||I|||||H||||Illlllllllllll||||
`US005590375A
`
`[54] APPARATUS FOR PERFORMING
`CONCURRENT SEEKS ON PLURAL
`INTEGRATED DRIVE ELECTRONICS (IDE)
`DISK DRIVES WITHOUT ADDITIONAL
`DEVICES
`
`[75]
`
`Inventors: Vic Sangveraphunsiri, San Clemente;
`Felix Pinai, Fountain Valley; Thomas
`Shu, Lake Forest; Cameron Spears,
`Diamond Bar, all of Calif.
`
`[73] Assignee: Advanced Logic Research, Irvine,
`Calif.
`
`[21] Appl. No.: 353,336
`
`[22]
`
`Filed:
`
`Dec. 5, 1994
`
`Related U.S. Application Data
`
`[63] Continuation of Ser. No. 935,713, Aug. 27, 1992, aban-
`doned, which is a continuation—in—part of Ser. No. 926,675,
`Aug. 10, 1992, abandoned.
`
`Int. Cl.6 ....................... G06F 7/00; G06F 13/00
`[51]
`[52] U.S. Cl.
`. 395/841; 395/44.1; 364/DIG. 1;
`364/236.2; 364/243; 364/243.7; 364/248.1;
`_
`364/256.8
`[58] Field of Search ....................... 369/14-15; 371/10.1,
`371/11.1, 51.1; 395/275, 425, 575, 800,
`840, 841, 441, 182.04, 182.05
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`................... .. 340/172.5
`11/1971 Balakian et al.
`3,623,006
`7/1975 Sordello
`.. 360/73
`3,893,178
`.. 318/338
`12/1980 White ........
`4,240,015
`360/98
`5/1981 Crawford ..
`4,270,154
`360/99
`11/1983 Wcnner
`4,414,591
`. 395/457
`.
`4,415,970 11/1983 Swenson et
`1/1985 Greer ............
`395/880
`4,494,196
`7/1985 Dean etal.
`4,528,626
`395/848
`..
`4,590,559
`5/1986 Baldwin etal.
`364/414
`4,638,189
`1/1987 Geannopoulos et al
`307/465
`2/1987 Allebest et a1.
`..
`4,644,515
`369/32
`
`4,670,714
`6/1987
`4,688,198
`8/1987
`
`
`
`
`
`367/70
`369/32
`95/185.07
`
`.
`
`
`
`9/1987 Sengupta ...............
`4,694,438
`4,701,896 10/1987 Allebest et al.
`4,817,035
`3/1989 Timsit
`.......
`8/1989 Kazama ........
`4,858,038
`
`(List continued on next page.)
`OTHER PUBLICATIONS
`
`Dell Computer Corporation, Dell, Summer 1991, p. 35.
`Dr. Jerry Lake, “Systems Effectiveness", Defense Systems
`Management College, Systems Engineering Management
`Department Fig. 1 (Jul. 1992).
`Murray Sargent & Richard Shoemaker, “The IBM Personal
`Computer from the Inside Out” p. 398 (Rev. Ed. 1986).
`Jerry M. Rosenberg, “Dictionary of Computers, Information
`Processing, and Telecommunications” p. 628 (2d ed. 1987).
`
`Primary Examiner—Lance Leonard Barry
`Attorney, Agent, or Firm—Popham, Haik, Schnobrich &
`Kaufman, Ltd.
`
`[57]
`
`ABSTRACT
`
`An interface allows a given CPU (Central Processing Unit)
`to communicate concurrently with a large number of disk
`drivesvin a high—performance, low-cost system. Plural seek
`operations can be performed concurrently, to serve a com-
`mon processor. Also, heterogeneous physical drives—oI any
`physical or logical configuration (storage capacity, number
`of heads, and so forth)—can be combined into one or more
`“logical” drives as seen by a host operating system. An
`“on-board” embodiment provides an “enhanced” IDE (Inte-
`grated Drive Electronics) disk drive that is an extension of
`the industry-standard IDE drives, allowing an arbitrary
`number of independently seeking IDE drives on a conven-
`tionally single-seeking,
`two—drive—maximum bus.
`In a
`“paddle board” embodiment, low-cost IDE drives of arbi-
`trary physical size, storage capacity and geometry, can be
`combined simply and inexpensively into a high-perfor-
`mance storage device. For example, a 3.5"80 MB (mega-
`byte) drive cau be transparently combined with a 2.5" 60
`MB drive. The inventive concept can thus be embodied with
`either a “paddle board” controller (with standard IDE
`drives), or with no additional controller
`(employing
`“enhanced” IDE drives).
`
`12 Claims, 17 Drawing Sheets
`
`PROCESSOR
`l"‘BOARD
`
`
`
`Apple 1040
`
`U.S. Pat. 9,189,437
`
`Apple 1040
`U.S. Pat. 9,189,437
`
`

`
`5,590,375
`Page 2
`
`11/1992 Kaplinsky .......................... .. 307/272.2
`5,164,612
`3/1993 Anderson ............................... 371/51.1
`5,191,584
`7/1993 Hillis et a1.
`........................ 395/182.04
`5,202,979
`4/1993 Guimdon at al
`600/16
`5205 810
`8/1993 Parks etal. .......................... 361/729
`5,239,445
`5271012 12/1993 B1
`31
`182 04
`51274307 12/1993 Lea“‘“ 9‘
`---------- 395’360}39
`»
`~
`9 -- --- --- ----- ---
`v- ----
`§1;;=n°Y:1ta1- v
`3332:?
`
`
`
`395/182.03
`395/841
`............................. 395/404
`
`-
`eet
`4/1994 Isman et al.
`4/1995 Parks ..........
`12/1995 Parks et a1.
`
`'
`
`,
`»
`5,301,310
`5.404.454
`5,473,761
`
`U.S. PATENT DOCUMENTS
`51 2
`/1
`9 989 B““.‘”““ °“‘1' """""""""" 39 ’ 3 -05
`3/1990 Arm etal.
`360/69
`4/1990 CW2 "
`364/602
`6/1990 Fnssell ...........
`360/78.04
`1/1991 Dunphy,Jr.etal.
`. 395/182.05
`7/1991 H bart
`tal. .... ..
`.. 372/107
`8/1991 Lgwis
`307/475
`
`
`
`395/822
`.. 395/402
`.. 395/439
`395/834
`
`5,058,004 10/1991 Ravid ........ ..
`5,097,439
`3/1992 Patriquin etal.
`5,127,088
`6/1992 Takaxi
`.......... ..
`5,150,465
`9/1992 Bush et al.
`..........................
`
`4
`487
`°’6 3
`’
`4,910,614
`4’92°’5°6
`4,935,828
`4,989,206
`5,033,061
`5,043,606
`
`

`
`U.S. Patent
`
`Dec. 31, 1996
`
`Sheet 1 of 17
`
`5,590,375
`
`
`
`
`IDE |NTERFACE/
`
`CONNECTOR
`
`PRIOR ART
`
`F/6‘./
`
`ISA/EISA BUS
`
`L__ _ _ _ _ _ _ _ PROCESSOR BOARD
`B/A|ULTl‘SEEK IDE
`00
`PADDLE BOARD R
`
`I
`
`I
`
`-— - ————-———..-——,
`
`:II
`
`___..l.__
`
`“*1
`I
`E
`,
`.
`L _ _,___1
`l|8~’
`
`IDE
`DRIVE 1
`
`IDE
`DRIVE 2
`
`IDE
`DRIVE 3
`
`I
`|DE
`DRIVE 4
`
`HO
`
`||2
`
`H
`
`H
`
`F/G. 2/I
`
`

`
`U.S. Patent
`
`Dec. 31, 1996
`
`Sheet 2 of 17
`
`5,590,375
`
`MULT|’SEEK
`IDE CONTROLLER
`
`T PC SYSTEM
`/486 TM
`
`
`
`HOST PC
`
`TEM
`
`
`
`

`
`U.S. Patent
`
`Dec. 31, 1996
`
`Sheet 3 of 17
`
`5,590,375
`
`
`
`PROCESSOR
`I~’BOARD
`
`I
`
`I
`I
`I
`I
`I
`I
`,
`I
`I
`
`I I
`
`I
`I
`I
`I
`
`
`
`HARD DISK
`#2
`
`HARD DISK
`#3
`
`HARD DISK
`4|
`
`I
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`I
`
`I
`I
`I
`I
`I
`
`A SA/EISABUS
`PROCESSOR BOARD
`
`- — _ _ _ — - -L_I3R—OC_IE—SS—C)—R_S—YS—1'-EM _ _ _ — _— ———
`
`F/G. 2E
`
`

`
`l||n|IlnIl|lI|I|||I|.|n||||..|ulu|II|l|I|l~I||.IIIIIIr|
`
`
`
`om<om_mommmuommx.
`
` U.S.Patent
`
`
`
`
`
`mam35.28mmmmE8<<mm_\<m_om
`
`omm
`
`mo.-
`
`26.-
`
`Dec.31,1996
`
`o_m
`
`mm>_mumz<E
`
`mam«:3<m_m\<m__
`
`won
`
`Om__w>mm>_m5_uoDuOmOQ
`
`Sheet_4of17
`
`
`<om>m-
`ol vm¢lIEHmo_-
`mo“.moZmzz8mmoouwoEu.90cmEomlmmfi«N
`
`
`
`
`
`zzouN<..o.mmmcm
`
`.E<mo:_E
`
`5,590,375'
`_.|IIIIIIIIIIIIIIIIIIIIII
`
`omm
`
`
`
`
`
`mm>_mom><,._m\mm:m<2mmm
`
`
`

`
`Llwn
`
`eD
`
`c
`
`1
`
`1.9
`
`6
`
`LleehS
`
`71cl.0
`
`5
`
`WomvamW._wéE<2om.m<m_o
`
`
`
`D...mm.._m2<E<2om._m<zm
`
`
`
`.."4...a3mm.52:mamS4":1..<_2E.m..::moo./<m_m2m_
`
`3
`
`5
`
`wI
`
`mmmm8<_
`
`5.
`
`ownzw<5,u.H-E29-.<
`«M.n¥.aaufl=.m.mmE«m.aIEmmmm
`
`
`9...._..<..r<_2.43.2IE0IlfimfiIi9.mmo8uo
`
`mwm—
`
`
`

`
`3U
`
`et
`
`D
`
`%Um
`
`U.m6am
`
`5»
`
`H
`
`
`
`om._<zo_m.5528:9.mo_.N<-o<
`
`
`
`
`
`Ma.53moin.wMb\K
`
`
`
`mm_uEE»z_E=$mfiz_
`
`wmam5.8
`
`S.
`
`mamawewon
`
`
`
`}.5528ma.
`
`

`
`f..mfiofizmoamo.
`xmmm-:..5s_.Pn_.o<:amo_
`
`AWo_m
`
`
`%H9_
`
`_.uuuuuuuI'LMmz:em_:»
`...o5%.
`1,_mam«:3we1_vowJ.mamm"SE28moD_mom_m_.oE<B>.E..r._
`
`57
`
`_m_-o<EBo_
`
`t_.1«._\weW_.o.2h_....uS.u..o...._
`_____BEE.U__..55..
`r__.,.m..myM_amomzmoL,.mobmzzou
`
`_.ll|»|I.LIII.I.“cmm>_mo_
`
`~.os.<8e5E.5,9m
`3,EBQ4..10.E8959:0,©\In\
`BEE
`.\.O=N8
`
`
`

`
`U.S. Patent
`
`Dec. 31, 1996
`
`Sheet 8 of 17
`
`5,590,375
`
`IDE CONTROL BUS
`
`
`
`
`I DE DATA BUS
`
`
`
`
`_—.1—..:_—.—__.———-_-.—-——
`
`IDE CONNECTOR
`
`PROCESSOR__BOARD
`
`|
`
`
`
`
`
`MASTER
`
`MULT|‘SEEK IDE
`MULTI'SEEK IDE
`DRIVE
`DRIVE
`W2
`
`
`
`
`
`SLAVE
`
`F/6? 7
`
`I I I I
`
`PHYSICAL DRIVE STATUS
`LOGICAL REQUESTS AND DATA
`
`
`I
`0
`I
`I IIOO
`' '2
`I HOST 05
`I I4...
`I
`I
`I
`
`
`
`
`I I I I I I I
`
`
`
`LOGICAL DATA AND STATUS
`
`PHYSICAL DRIVE COMMANDS
`
`
`
`LOGICAL PARAM.
`OS SPECIFIC INFO.
`
`PHYSICAL DRNE FARAM.
`DRIVE NUMBER
`
`CONFIGURATION INFO.
`
`H ARDWARE
`
`"20
`
`
`
`TRANSLATION TABLES
`
`F/G. 8
`
`

`
`U.S. Patent
`
`Dec. 31, 1996
`
`Sheet 9 of 17
`
`5,590,375
`
`I252
`
`PORT
`SELI§E§_'°”
`
`I }
`
`I
`,
`I
`I
`
`I
`
`I
`I
`'
`I
`
`I
`I
`
`I254
`INTERRUPT
`CONTROL
`
`REG‘
`
`l
`STANDARD
`IDE REG.
`I25
`
`I255
`DRIVE
`COMMNDS:
`I
`
`~
`
`I202
`
`DRIVE ID
`
`1253
`“W5 ‘D
`
`I
`'
`I
`
`LOGICAL SECTOR
`
`i REQUEST(READ)
`
`I
`:
`I
`IIOO I
`
`HOST '
`Os
`I
`I
`:
`;
`I
`
`I26‘
`
`DRIVE STATUS
`
`‘304
`
`II
`
`LOGICAL STATUS
`I (READ COMPLETE)
`
`I206
`
`I270
`
`
`
`INTERRUPT
`STATUS
`REG.
`
`I26
`
`HI
`
`|
`I
`
`I I I
`
`I I I
`
`HARDWARE
`
`I I E
`
`I
`
`DATA TRANSFER AREA
`
`F/6‘. 9
`
`

`
`U.S. Patent
`
`Dec. 31, 1996
`
`Sheet 10 of 17
`
`5,590,375
`
`I352
`
`I :
`
`I35I
`
`DRIVE ID
`
`I
`
`,
`
`I
`
`I
`:
`
`I
`
`I
`'
`:
`I
`
`I353
`°“'“E'°
`
`I355
`
`DRIVE
`
`COMMANDS:
`
`I
`_,
`I
`'
`'
`
`'36‘
`DRIVE STATUS
`
`PORT
`
`SELREE .'°”
`
`|354
`'E‘3E$I‘§8ET
`REG.
`
`
`
`STANDARD
`
`[05 R53
`
`.
`
`I356
`
`IN-rERRUp1'
`STATUS
`R55
`
`I360
`
`‘
`
`I
`I
`
`LOGICAL SECTOR
`I REQUESTIWRITEI
`
`502
`
`I
`
`I
`I
`liq-Q :
`”8§T I
`
`I
`
`I‘
`
`I
`I
`I
`
`.
`
`I304
`
`II
`
`LOGICAL STATUS
`' (WRITE COMPLETE)
`
` HARDWARE
`
`DATA TRANSFER AREA
`
`F/G.
`
`/O
`
`

`
`&U
`
`Llm%
`
`mD
`
`9D%
`
`H.mua.mS
`
`5
`
`573,
`
`
`
`m><E<PE:mmm»z_ezazmamansV55
`
`6So:
`
`
`mm>_m_QmZO_._.UDm.—.mZ__2m»m>m
`...O:OO:
`
`
`
`
`00,m._mS
`
`5,oz_&<_2mofimm
`
`
`
`
`
`._<u_m>:.n_4t._<u_oo._%\\.0\I.\
`
`

`
`U.S. Patent
`
`Dec. 31, 1996
`
`Sheet 12 of 17
`
`5,590,375
`
`ASSOC
`HOST
`PRIORITY STATUS INT
`
`RW BUFFPTR
`
`TRANSACTION o
`
`
`
`TRANSACTION I
`
`'
`
`TRANSACTION 2
`
`

`
`U.S. Patent
`
`Dec. 31, 1996
`
`Sheet 13 of 17
`
`5,590,375
`
`RECEIVE
`ST
`
`RE UE0
`
`TRANSLATE
`LOGICALTO
`PHYSICAL
`
`2500
`
`2505
`
`
`
`
`RECEIVE
`LOGICAL
`
`SECTOR
`
`REQUEST
`
`
`
`
`
`
`TRANSLATE
`TO PHYSICAL
`SECTORS
`
` SELECT
`TARGET
`(PHYSICAL)
`
` SEND
`
`STANDARD
`COMMAND(S)
`
`
`F/G /6
`
`F/G. /5
`
`ENABLE
`I NTERRUPT
`
`25|O
`
`SEND
`COMMAND
`TO DRIVE
`
`-
`
`2530
`
`2540
`
`2570
`
`2575
`
`25 80
`
`SET BITZ
`‘DRIVE
`-TRANSACT ION
`
`
`
`PROCESS
`I NTERRUPT
`
`I RESETPT
`NT RRU
`BIT
`
`YES
`
`2590
`
`COMPLETE
`
`

`
`U.S. Patent
`
`Dec. 31,‘ 1996
`
`Sheet 14 of 17
`
`5,590,375
`
`‘bHANNEu%o
`
`200
`
`SELECT THE CHANNEL
`
`210
`
`3220
`
`in
`
`YES
`
`
`
`3230
`NO IS
`THERE MORE
`
`» CHANNE
`
`326 0
`
`ET REQUEST FROM
`QUEUE
`
`
`
`3250
`
`3270
`
`3240
`
`UPDATE TASK
`
`F/G. /7
`
`
`
`3280
`
`ENABLE CHANNEL
`I NTER RUPT
`
`$ND COMMAND T0
`CHANNEL
`
`

`
`U.S. Patent
`
`Dec. 31, 1996
`
`Sheet 15 of 17
`
`5,590,375
`
`33IO
`
`3320
`
`READ INTERRUPT STATUS
`
`REGISTER
`
`SELECT INTERRUPTING
`CHANNEL
`
`
` IS IT DM ‘
`
`DATA REQ INT
`
`3330
`
`NO
`
`YES
`
`IOXN8I
`
`P
`
`
`
`PROCESS DMA DATA REQ
`INT ACK
`
` DMA REQ
`OMP INT’
`
`RETURN To03'PROCESSDMA REQ
`
`COMP INT ACK
`
`3380
`
`3360
`
`PROCESS DRIVE
`INTERRUPT
`
`

`
`U.S. Patent
`
`Dec. 31, 1996
`
`Sheet 16 of 17
`
`5,590,375
`
` SELECT DRIVE n
`
`4H3
`
`LOCK DMA FOR DRIVE n
`
`3360
`
`
`
`
`
`3420
`
`PROGRAM H$T DMA
`0 1
`I 0
`I
`
`
`
`LET DMA START
`
`A A .
`
`RETURN TU 03
`
`3380
`
`
`
`F/G. /9
`
` SCHEDULE NEXT REQUES
`
`FROM DRIVE n
`
`RETURN TO OS
`
`3380
`
`F76. 20
`
`

`
`U.S. Patent
`
`Dec. 31, 1996
`
`Sheet 17 of 17
`
`5,590,375
`
`3370
`
`SELECT DRIVE n
`
`36lO
`
`READ TRANSFER STATUS
`FROM DRIVE n
`
`%
`
`620
`
`PROCESSING INTERRUPT
`
`CLEANING
`
`SCHEDULE NEXT REQUEST
`
`FOR DRIVE n
`
`

`
`1
`APPARATUS FOR PERFORMING
`CONCURRENT SEEKS ON PLURAL
`INTEGRATED DRIVE ELECTRONICS (IDE)
`DISK DRIVES WITHOUT ADDITIONAL
`DEVICES
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This is a continuation of U.S. patent application Ser. No.
`07/935,713, filed Aug. 27, 1992 now abandoned, which was
`a continuation-in-part of Ser. No. 07/926,675, filed Aug. 10,
`1992 now abandoned.
`
`10
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to interfaces between pro-
`cessors and peripheral devices. More specifically, the inven-
`tion relates to interfaces between processors and disk drives
`which allow a larger number of disk drives to be controlled
`by a single processor and an existing disk controller, thereby
`allowing concurrent seeks on more than one drive.
`2. Related Art
`
`Various patents disclose control schemes for storage
`media.
`
`For example, U.S. Pat. No. 3,623,006 (Balakian et al.)
`shows an early example of a “disk file optimizer” which
`selects a most optimum request for execution based on
`minimum latency time. U.S. Pat. No. 3,893,178 (Sordello)
`provides synchronized rotation of several disks to minimize
`latency time, when switching from one disk to another. U.S.
`Pat. No. 4,270,154 (Crawford) discloses a system in which
`several heads (or stacks of heads) are provided to minimize
`latency time.
`In U.S. Pat. No. 4,494,196 (Greer), a controller 20 is
`disposed between a central processor unit 10 and N periph-
`eral data storage units 12-1 through 12-N. The Greer con-
`troller focuses on controlling data storage devices having
`different data transfer rates, using a corresponding number
`of instruction storage units.
`U.S. Pat. No. 4,858,038 (Kazama) discloses a set of disk
`drive selector circuits for a disk drive controller which allow
`different “types” of disk drives to be selected.
`U.S. Pat. No. 4,910,614 (Arai et al.) discloses a disk
`controller which is disposed between a host processor and
`several disk drives of diiferent types. The focus of the Arai
`et al. patent is the presence of two types of memories: a first
`type of memory in one-to-one correspondence with the disk
`drive units, and a second set of memories defining the types
`of disk drives.
`
`U.S. Pat. No. 4,935,828 (Frissell) discloses a seek multi-
`tasking disk controller in which a disk control unit 102
`(Frissell’s FIG. 2) is disposed between a CPU 201 and
`several disk drives 104, 106. As explained with reference to
`Frissell’s FIGS. 6 and 7, during a time when a data transfer
`command is deferred in one disk drive, a seek command
`may be addressed to another disk drive. The Frissell multi-
`tasking controller depends heavily on the relative location of
`the head and sectors on one of the disk drives.
`
`Finally, U.S. Pat. No. 5,097,439 (Patriquin et al.) is
`directed to interfacing several disk drives to an ATTM-based
`host computer. The Patriquin et al. patent focuses on a
`“subsystem” which is an interface between the host com-
`puter’s buses and many disk drive “clusters” the subsystem
`allowing substantial expansion. The Patriquin et al. system
`
`20
`
`30
`
`35
`
`45
`
`50
`
`60
`
`65
`
`5,590,375
`
`2
`
`may carry out seeks concurrently in more than one disk
`drive.
`
`From the foregoing patents, it is apparent that various
`schemes for handling more than one recording medium are
`known in the art. However, the known system possess one
`or more disadvantage which are of concern from either or
`both a cost or performance standpoint. For example, it is
`known in the art that additional drives may be added to a
`given computer system, but only through costly addition of
`additional software drivers. Alternatively, a known solution
`is to adapt a given disk drive to such a system, but this
`adaptation of the disk drive’s interface is also costly. More-
`over, the addition of a larger number of disk drives to a
`system has often slowed the performance of the overall
`system, even in those which conceivably could perform
`concurrent seek operations in different disk drives.
`FIG. 1 illustrates an ISA/EISA (Industry Standard Archi-
`tecture/Extended Industry Standard Architecture) bus 100
`connected in a standard configuration to first IDE (Inte-
`greated Drive Eklectronics) drive 110 and a second IDE
`drive 112 via an IDE interface/connector 104. The ISA/EISA
`bus 100 is controlled by a processing unit such as CPU
`(Central Processing Unit) 102.
`On a standard IDE interface, at most two drives can be
`connected to the ISA/EISA bus. In the known arrangement
`illustrated in FIG. 1, the CPU selects one of the drives 110,
`112 by setting bit 4 of I/O register 1F6H to 0 or 1. This bit
`enables I/O (Input/Output) decoding to the address ranges
`1FOH-1F07H and 3F6H—3F7H, as well as to select the
`source of interrupt line IRQ14 used for disk 1/0 in ISA/EISA
`systems. In this known arrangement, only one IDE disk
`drive can be selected at any given time. One operation must
`be completed on a first disk drive, before another operation
`can begin with respect to another drive. Therefore, concur-
`rent multi-seek operations carmot be performed at all in two
`disk drives in the arrangement illustrated in FIG. 1.
`The FIG. 1 arrangement including an existing IDE inter-
`face with a maximum of two disk drives is adequate for
`operating systems such as MS-DOSTM, because the envi-
`ronment requires only sequential disk accesses. However, in
`other operating systems, such as “lVIICROSOFI"’TM “WIN-
`DOWS”TM, “NOVELL”TM “NETWARE”TM, or “UNIX”TM,
`concurrent requests may be pending due to multi-tasking
`and multi-user capability. If an operating system desires
`access to more than one disk drive at a time, or if commands
`are desired to be sent to different disk drives simultaneously, ,
`concurrent seeking on more than one disk drive is required.
`If this can be achieved, faster data acquisition is possible,
`and the system would have higher performance than one
`with a sequential request access.
`As described to some extent in the above-listed patents, as
`well as in the SCSI (Small Computer System Interface)
`controllers, seeks can be perfonned on more than one disk
`drive at a time. However, the cost of the SCSI controller is
`high, and the SCSI protocol interface involves substantial
`overhead. To date,
`there is no known system in which
`multi-seek operations can be performed while nrinimizing
`both cost and overhead. It is especially desirable to provide
`this multi-seek capability on disk drives which do not
`require special interface hardware or software, but may
`employ a conventional (for example, IDE) interface arrange-
`ment.
`
`Therefore, there is a need in the art to provide means for
`interfacing a processor with more than one disk drive at the
`same time, thereby allowing concurrent multi-seek capabil-
`ity even when both drives are standard IDE drives, in a
`
`

`
`3
`
`4
`
`5,590,375
`
`low-cost, high performance system especially suitable for
`multi-tasking.
`
`SUMMARY OF THE INVENTION
`
`The present invention overcomes the limitations of the
`system of FIG. 1 by providing an interface which allows a
`given CPU to communicate concurrently with a large num-
`ber of disk drives in a high-performance, low-cost system. In
`particular, the present invention allows more than one seek
`operation to be performed at the same time, in serving a
`common processor.
`
`10
`
`Additionally, the present invention can combine standard
`physical drives of any physical or logical configuration
`(storage capacity, number of heads, and so forth) into one or
`more “logical” drives. That
`is, heterogeneous physical
`drives can be combined into one or more homogeneous
`“logical” drives as seen by a host operating system.
`Advantageously, the present invention provides an inter-
`face which is downward compatible with the existing inter-
`face between the processor bus and the disk drives. Although
`the invention provides control for additional disk drives, no
`additional disk controller is required, resulting in consider-
`able improvements in system cost, performance, mainte-
`nance cost, flexibility, and reliability.
`The invention not only provides increased storage capac-
`ity, but also higher performance and improved price/perfor-
`mance ratios. The invention creates an environment,
`in
`which “standard” (lower performance) disk drives having
`standard interfaces not allowing concurrent seeks, may be
`placed,
`the environment allowing the various drives to
`independently perform concurrent seeks. In this manner,
`performance in accessing randomly located files is increased
`in a nearly proportional fashion, with n drives providing
`almost n times the performance of a single drive.
`Supplemental enclosures external to the computer chassis,
`additional power supplies, special cabling, and the like, are
`not required to implement the present invention. Rather,
`standard electrical and physical interfaces (connectors and
`cabling) may be employed in implementing the invention,
`while obtaining increased capacity and performance, main-
`taining a storage device addressing scheme which preserves
`the simplicity of the CPU’s addressing of data locations,
`achieving an improved price/perforrnance ratio, and main-
`taining low cost and a small parts list.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The invention is better understood by reading the follow-
`ing Detailed Description of the Preferred Embodiments with
`reference to the accompanying drawing figures, in which
`like reference numerals refer to like elements throughout,
`and in which:
`
`FIG. 1 is a block diagram illustrating a known arrange-
`ment of an ISA/EISA bus 110 operationally connecting a
`processor 102 and two disk drives 110, 112 using a conven-
`tional IDE interface.
`
`FIG. 2A is a high-level block diagram showing a “paddle
`boar ” implementation of the multi-seek unit of the present
`invention, the paddle board being disposed between bus 100
`and a larger number of disk drives 110, 112, 114, 116. FIG.
`2B is a perspective view of an embodiment of the multi-seek
`unit according to the paddle board embodiment, in which the
`multi-seek unit is on a paddle board installed in an ATTM-
`compatible personal computer.
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`FIG. 2C is a high-level block diagram showing an “on-
`board” implementation of the present invention, in which
`the multi-seek unit uses an ATTM-compatible computer’s
`standard IDE interface in conjunction with special Multi-
`seek IDE hard drives. FIG. 2D is a perspective view of the
`“on-boar ” embodiment, in which drives 210, 212, 214, 216
`are “daisy-chained”.
`FIG. 2E illustrates an embodiment of the invention in
`which multiple disk drives are mounted on a single printed
`circuit card, all the drives being capable of concurrent seek
`operations serving a common processor in accordance with
`the “paddle board” embodiment shown in FIGS. 2A—2B, it
`being understood that both the paddle board embodiment
`(FIGS. 2A-2B) and the on-board embodiment
`(FIGS.
`2C—2D) could be implemented on a single card.
`FIG. 3 illustrates in greater detail the interface in the
`known system of FIG. 1.
`FIG. 4 is a high-level block diagram of paddle board
`circuitry which allows an improvement in performance over
`the known system in FIG. 3.
`FIG. 5 illustrates a known interface to a standard IDE
`drive.
`
`FIG. 6 is a high-level block diagram illustrating an
`improved interface to a standard IDE drive, according to the
`on-board embodiment of the present invention.
`FIG. 7 is a block diagram illustrating connection of master
`and slave Multi-seek IDE disk drives in a configuration
`supported by the present invention.
`FIG. 8 is a context diagram schematically illustrating how
`the preferred software driver resides between the host oper-
`ating system and the disk drive hardware.
`FIG. 9 schematically illustrates the data flow between the
`host operating system and the disk drive hardware during a
`read operation, as managed by a software driver according
`to the present invention.
`FIG. 10 schematically illustrates the data flow between
`the host operating system and the disk drive hardware during
`a write operation, as managed by a software driver according
`to the present invention.
`FIG. 11 schematically illustrates exemplary software
`architecture according to a preferred embodiment of the
`present invention.
`FIG. 12 illustrates an exemplary task queue of the FIG. 11
`software architecture.
`
`FIG. 13 illustrates an exemplary sector mapping table
`according to the FIG. 11 software architecture.
`FIG. 14 illustrates an exemplary pending interrupt table
`according to the FIG. 11 software architecture.
`FIG. 15 is a flow chart illustrating the driver’s operation
`using the pending interrupt table of FIGS. 11 and 14.
`FIG. 16 is a flow chart illustrating a multi-seek driver
`executive according to a preferred embodiment.
`FIG. 17 is a flow chart illustrating channel request queue
`processing in more detail than FIG. 16.
`FIG. 18 is a high-level flow chart illustrating the operation
`of interrupt service routines, to be executed in response to
`completed executed command sequences.
`FIGS. 19, 20, and 21 are flow charts illustrating particular
`interrupt service routines for DMA (Direct Memory Access)
`data request interrupts, DMA request completed interrupts,
`and disk interrupts, respectively.
`DETAEED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`In describing preferred embodiments of the present inven-
`tion illustrated in the drawings, specific terminology is
`
`

`
`5
`
`6
`
`5,590,375
`
`employed for the sake of clarity. However, the invention is
`not intended to be limited to the specific terminology so
`selected, and it is to be understood that each specific element
`includes all technical equivalents which operate in a similar
`manner to accomplish a similar purpose.
`In addition to the more general problems addressed
`above, the multi-seek IDE embodiments described herein
`address problems of high cost and high overhead associated
`with interfaces such as the SCSI implementations. First, the
`need for an expensive SCSI controller is eliminated. In
`contrast, an IDE interface is standard on nearly all present-
`day PC/ATTM compatible systems. Second, IDE hard drives
`are more efficient than SCSI hard drives, requiring fewer I/O
`cycles per operation.
`More generally, an interface according to the present
`invention allows a given CPU to communicate concurrently
`with a large number of disk drives in a high-performance,
`low-cost system. In particular, more than one seek operation
`can be performed at the same time, in serving a common
`processor. Additionally, the present invention can combine
`standard (for example, IDE) physical drives of any physical
`or logical configuration (storage capacity, number of heads,
`and so forth) into one or more logical drives. That is,
`heterogeneous physical drives can be combined into one or
`more homogeneous “logical” drives as seen by a host
`operating system. When applying the invention to IDE
`drives, a first, “on-boar ” embodiment provides a “multi-
`seek IDE disk drive” that is an extension of the industry-
`standard IDE drives, allowing an arbitrary number of inde-
`pendently seeking IDE drives on the formerly single-
`seeking, two-drive-maximum bus. Low-cost IDE drives of
`arbitrary physical size, storage capacity and geometry, can
`be combined simply and inexpensively into a high perfor-
`mance multi-seek disk drive. For example, a 3.5" 80 MB
`drive can be transparently combined with a 2.5" 60 MB
`drive.
`
`The concept can be embodied in several implementations,
`such as one using a “paddle boar ” controller (with standard
`IDE drives), or another using no additional controller (but
`with enhanced IDE drives). These two implementations are
`shown respectively in block diagram form in FIGS. 2A and
`2C, and in perspective view in FIGS. 2B and 2D. The
`multi-seek paddle board (FIGS. 2A, 2B) allows use of
`unmodified, conventional IDE disk drives. In contrast, the
`on-board
`implementation
`(FIGS.
`2C,
`2D)
`employs
`“enhanced” (or “mu1ti-seek”) IDE drives.
`FIG. 2E illustrates an embodiment of the invention in
`which multiple disk drives are mounted on a single printed
`circuit card, all the drives being capable of concurrent seek
`operations serving a common processor in accordance with
`the “paddle boar ” embodiment shown in FIGS. 2A—2B. It
`is understood, however, that both the paddle board embodi-
`ment (FIGS. 2A—2B) and the on-board embodiment (FIGS.
`2C-2D) may be implemented on a single card.
`In FIG. 2E, the board is shown poised for connection to
`a standard«ISA/EISA bus. FIG. 2E drarnatizes the inven-
`tion’s ability to provide plural physical disk drives in a
`simple configuration that presents to the system CPU a
`single logical disk drive of substantial aggregate storage
`capacity. Moreover, performance in addressing randomly
`located files is nearly proportional to the number of physical
`drives in the system, despite the fact that multiple concurrent
`seeks are performed without the CPU’s specific supervision.
`A preferred embodiment of the multi-seek unit 200 is
`preferably implemented using a PLSITM 1032 Program-
`mable Large Scale Integrated Logic Device available from
`
`20
`
`25
`
`30
`
`35
`
`,
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`LATTICE SEMI—CONDUCTOR CORP., 555 N. E. Moore
`Court, Hillsboro, Oreg. 97214 (telephone l-800-LATTICE).
`As readily appreciated by those skilled in the art,
`the
`LATTICE PLSITM 1032 is a programmable high-density
`logic device having a large number of registers, I/O pins,
`clock input pins, and a “global routing pool” which allows
`complete interconnectivity between all of the elements. This
`chip, readily capable of programming by those skilled in the
`art, enables fairly complex logic functions to be imple-
`mented without using a large number of discrete elements or
`integrated circuits, providing the advantage of reduced size.
`By reference to the LATTICE data sheet such as that dated
`October 1991 as well as to the accompanying description of
`the present invention, those skilled in the art are readily
`capable of implementing this multi-seek unit in a workable
`computer system. The October 1991 LATTICE data sheet on
`the PLSITM 1032, being documentation of a type which is
`readily available to those skilled in the art, need not be
`further described herein.
`
`Referring to FIG. 2A, a high-level block diagram of a
`paddle board embodiment of the present invention is illus-
`trated. A paddle board multi-seek unit 200 embodying
`principles of the present invention is illustrated between
`ISA/EISA bus 100 and a plurality of IDE drives 110, 112,
`114, and 116. A larger number of drives may readily be
`supported, as indicated by element 118. Comparing FIG. 2A
`to FIG. 1 in view of the following discussion, those skilled
`in the art will readily appreciate that the present invention
`provides greater effective storage capacity that is readily
`accessible to CPU 102, in a high-perforrnance system not
`requiring additional software drivers associated with CPU
`102 or specialized interface software in IDE drives 110-118.
`FIG. 2B illustrates in perspective View a multi-seek unit
`in the form of a multi-seek paddle board 200. The paddle
`board 200 is shown plugged into the ATM bus connector
`card, and extending between the bus and a rear connector
`allowing communication with a plurality of disk drives 110,
`112, 114, 116, and so forth. In the illustrated arrangement,
`the various disk drives do not require any special software
`or hardware interface, but may include only the conven-
`tional IDE interface.
`
`FIG. 2C is a high-level block diagram showing an “on-
`board” implementation of the present invention, in which
`the multi-seek unit uses an ATTM-compatible computer’s
`standard IDE interface in conjunction with special multi-
`seek IDE hard drives 210, 212, 214, 216 and so forth.
`
`FIG. 2D illustrates in perspective view a multi-seek unit
`in the form of an “on-boar ” unit. An IDE cable connects the
`system processor board with a plurality of daisy-chained
`disk drives 210, 212, 214, 216, and so forth. The illustrated
`drives are preferably the “enhanced” IDE drives described
`with respect to FIG. 6.
`The operation of the paddle board embodiment is appre-
`ciated by referring to FIG. 4 and accompanying text below;
`the operation of the “on-board” embodiment is appreciated
`by referring to FIG. 6 and accompanying text below. More-
`over, a fundamental feature of the invention is that the host
`software for operating either embodiment remains the same
`(see FIGS. 11-21).
`Referring now to FIG. 3, the known interface arrangement
`of FIG. 1 is illustrated in greater detail. In particular,
`ISA/EISA bus 100 is illustrated as comprising an address
`and control bus 302 and a data bus 304. Data passes
`bi-directionally through a data transceiver 310, between
`ISA/EISA data bus 304 and a drive connector 350 that leads
`directly to the disk drive.
`
`

`
`7
`
`8
`
`5,590,375
`
`The transfer of data is governed by control and address
`lines passing through port decoder 320. Port decoder 320
`receives I/O read and I/O write control signals on paths 322
`and 324, respectively. An address enable control signal on
`path 326 enables the port decoder to recognize port address
`signals on paths 328. Port decoder 320 outputs hard drive
`channel select on paths 332, 334. The hard drive channel
`select signals are input to drive connector 350 to govern
`transfer of data between transceiver 310 and the hard drive
`connected to drive connector 350.
`
`As mentioned above, in the Background of the Invention,
`the known arrangement illustrated in FIGS. 1 and 3 allows
`only one of a maximum of two IDE disk drives to be
`accessed at any given time, in a configuration in which
`concurrent seek operations are not possible.
`Referring now to FIG. 4, the paddle board embodiment of
`the invention in FIG. 2A is illustrated in greater detail.
`ISA/EISA control bus 302, address bus 303 and data bus 304
`are connected to port decoder 320 and transceiver 310, in the
`same manner as in FIG. 3.
`
`According to the invention, each paddle board card may
`be implemented an I/O-mapped interface card. Each card is
`assigned a unique I/O address (such as 0x130, 0x170, x1B0,
`xlF0), a unique system interrupt (such as IRQIO, IRQ11,
`IRQ14, IRQ15), and a unique DMA Request (such as
`DRQO, DRQ5, DRQ6, DRQ7). A software driver, logically
`residing between the paddle board and the host processor,
`manages communication with the cards using each card’s
`unique values. In a particular preferred embodiment using a
`commonly available computer system,
`this arrangement
`allows up to four paddle board cards to be installed simul-
`taneously (in a single PC/ATTM system).
`Supplementing the conventional arrangement in FIG. 3,
`additional circuitry is provided i