United States Patent
`Salomon et al.
`
`[191
`
`[54] PROGRAMMABLE SCAN/READ
`CIRCUITRY FOR CHARGE COUPLED
`DEVICE IMAGING DETECTORS
`
`[75]
`
`Inventors: Phil M. Salomon, Tujunga; Kalman
`Smilowitz, Playa del Rey, both of
`Calif.
`
`[73] Assignee:
`
`The United States of America as
`represented by the Administrator of
`the National Aeronautics and Space
`Administration, Washington, D.C.
`
`[21] Appl. No.: 276,749
`
`[22] Filed:
`
`Jun. 24, 1981
`
`Int. Cl.3 ............................................. .. H04N 3/15
`[51]
`
`[52] U.S. Cl.
`. . . . . . . . . . . . . . . . .
`. . . . . .. 358/213; 358/125
`[58] Field of Search ...................... .. 358/213, 125, 126
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`.
`3/1977 Lorell et al.
`4,012,018
`4,251,834 2/I981 Hall ................................... .. 358/213
`4,314,279
`2/1982 Yoshida
`
`358/213
`.. 358/213
`3/1982 Bixby
`.
`. . . . . .. 358/213
`8/1982 Frame . . . . . . .
`4,343,021
`4,364,089 12/1982 Woolpson .
`358/126
`4,382,267
`5/1983 Angle ................................ .. 358'/213
`OTHER PUBLICATIONS
`
` 4,322,752
`
`“Charge-Coupled Device Trackers For High Accu-
`racy Guidance Applications”, Salomon, SPIE, vol. 203
`(1979), p. 130, originally presented Aug. 27, 1979.
`“Image Signal Processing In Sub—Pixel Accuracy Star
`
`[11]
`
`[45]
`
`4,430,673
`
`Feb. 7, 1984
`
`Trackers”, Salomon and Glavich, SPIE, vol. 252
`(1981), p. 64, originally presented Jul. 28, 1980.
`“Charge—Coupled Device Trackers For High Accu-
`racy Guidance Applications”, Salomon, Optical Engi-
`neering, Jan./Feb. 1981, vol. 20, No. 1, p. 135.
`
`Primary Examiner—Michael A. Masinick
`Attorney, Agent, or F1'rm——-Paul F. McCaul; Thomas H.
`Jones; John R. Manning
`
`[57]
`
`ABSTRACT
`
`for scanning and outputting the induced
`A circuit
`charges in a solid state charge coupled device (CCD)
`image detector (13) is disclosed in an image detection
`system (10) for use in a spacecraft attitude control sys-
`tem. The image detection system includes timing con-
`trol circuitry (25) for selectively controlling the output
`of the CCD detector (13) so that video outputs are
`provided only with respect to induced charges corre-
`sponding to predetermined sensing element lines of the
`CCD detector (13). The system also includs an analog
`to digital converter (29) for converting selected video
`outputs from the CCD detector (13). The timing con»
`trol circuit (25) and the analog to digital converter (29)
`are controlled by a programmed microprocessor (15)
`which defines the video outputs to be converted and
`further controls the timing control circuit (25) so that
`no video outputs are provided during the delay associ-
`ated with analog to digital conversion.
`
`19 Claims, 6 Drawing Figures
`
`//
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`U.S. Pat. 9,189,437
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`

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`U.S. Patent
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`Feb. 7, 1984
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`U.S. Patent
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`Feb. 7, 1984
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`U.S. Patent
`
`Feb. 7, 1984
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`

`
`1
`
`4,430,673
`
`PROGRAMMABLE SCAN/READ CIRCUITRY FOR
`CHARGE COUPLED DEVICE IMAGING
`DETECTORS
`
`BACKGROUND OF THE INVENTION
`
`2
`wherein only predetermined analog pixel voltages are
`outputted and wherein only selected ones of such pre-
`determined pixel voltages are A/D converted.
`
`SUMMARY OF THE INVENTION
`
`The foregoing objects and other purposes of the in-
`vention are achieved in a CCD image detector system
`having scan/read circuitry that includes programmable
`control circuitry that provides control parameters in-
`dicative of the pixel locations of interest, timing cir-
`cuitry responsive to the programmable control circuitry
`and the control parameters for providing timing signals,
`video circuitry responsive to the timing signals for driv-
`ing and clocking the CCD image detector in accor-
`dance with the timing signals, and a selectively enabled
`analog-to-digital (A/D) converter controlled by the
`programmable control circuitry for A/D converting
`only those predetermined CCD detector pixel output
`voltages of interest.
`the programmable control cir-
`More particularly,
`cuitry includes a programmed microprocessor which
`controls the clocking, outputting and A/D conversion
`of analog pixel voltages produced by the CCD image
`detector. By way of example, the disclosed preferred
`embodiment
`is incorporated in a spacecraft attitude
`control star tracker.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The advantages and features of the present invention
`can be readily understood and appreciated by persons
`skilled in the pertinent art from the following detailed
`disclosure when read in conjunction with the drawing
`wherein:
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`The invention described herein was made in the per-
`formance of work under a NASA contract and is sub-
`ject to the provisions of Section 305 of the National
`Aeronautics and Space Act of 1958, Public Law 85-568
`(72 Stat. 435; 43 U.S.C. 2457).
`The disclosed invention relates to the scanning and
`reading of solid state charge coupled device (CCD)
`image detectors, and is particularly directed to circuitry
`for selectively reading only predetermined CCD image
`sensing elements (pixels) so that read time can be mini-
`mized. In the preferred embodiment,
`the scan/read
`circuitry is incorporated in a star tracker for spacecraft
`attitude control systems. An example of the use of a star
`tracker in a spacecraft attitude control system is set
`forth in U.S. Pat. No. 4,012,018, issued to Lorell et al.
`on Mar. l5, 1977.
`A solid state CCD image sensor typically includes a
`rectangular array of discrete light sensing elements
`which are individually responsive to incident light en-
`ergy. Particularly, each pixel accumulates an amount of
`induced charge which is a linear function of the incident
`illumination intensity and of the time duration of expo-
`sure to the incident light (referred to as the “integration
`period”). Typically, the induced charge packets associ-
`ated with the pixels would be transferred to one or more
`analog transport registers for subsequent read-out. Re-
`gardless of the number of transport registers used, the
`analog voltages representative of the respective pixels
`are outputted serially from the image sensing detector.
`Prior art circuitry for scanning and processing the
`analog voltage outputs of CCD image detectors have
`typically outputted from the horizontal register each
`analog voltage associated with the respective CCD
`image sensing elements. Thus, the charges associated
`with each horizontal line are transferred to the horizon-
`tal
`register which is serially outputted before the
`charges of another line are transferred.
`Insofar as the analog voltage associated with each
`sensing element had to be shifted out, scanning the
`entire CCD array is relatively inefficient particularly
`where only certain predetermined pixels are of interest,
`such as in a star tracker.
`It is therefore an object of the invention to provide
`improved scanning, outputting, and selective reading of 50
`a CCD image detector.
`Another object of the invention is to provide im-
`proved control of the video output of a CCD image
`detector wherein only video outputs corresponding to
`predetermined pixel-induced charges are A/D con-
`verted for further processing.
`A further object of the disclosed invention is to pro-
`vide an improved scan/read circuit for CCD image
`detectors.
`_
`It is another object of the invention to provide a
`scan/read circuit for CCD image detectors wherein
`only predetermined pixels are processed.
`A further object of the invention is to provide an
`improved scan/read circuit for CCD image detectors
`wherein only predetermined analog pixel voltages are
`outputted from the CCD image sensor.
`Yet another object of the invention is to provide an
`improved scan/read circuit for a CCD image detector
`
`FIG. 1 is an illustrative block diagram of the dis-
`closed charge coupled device (CCD) image detector
`A system that incorporates the invention.
`FIG. 2 is a simplified block diagram of an exemplary
`CCD image detector.
`FIG. 3 is a schematic diagram of the elements of the
`timing module identified in FIG. 1.
`FIG. 4 through FIG. 6 illustrate flow charts that
`disclose the functions performed by the CPU/memory
`module shown in FIG. 1 and the timing module shown
`in FIG. 2.
`'
`
`40
`
`45
`
`DETAILED DESCRIPTION OF THE
`DISCLOSURE
`
`Illustrated in FIG. 1 is a CCD image detector system
`10 that includes a group of optical elements 11 which
`provides image forming charge inducing incident light
`to a CCD image detector 13. The optical group 11
`should typically include lens elements and other optical
`elements. For purposes of star tracking, where the fo-
`cused image of a star of interest might be smaller than
`the non-sensing boundaries between the individual light
`sensing elements of the CCD image detector 13, the
`optical image should be slightly defocused. That will
`insure that the image of a star of interest will always be
`sensed by the light sensing elements.
`The overall operation of the CCD image detector 10
`is controlled by a central processing unit (CPU)/mem-
`ory module 15. As shown, there are functional elements
`interposed between the CCD image detector 13 and the
`CPU/memory module 15 and such elements will be
`described further herein.
`The CPU/memory module 15 preferably utilizes a
`commercially available microprocessor of appropriate
`
`55
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`60
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`65
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`

`
`4,430,673
`
`3
`processing speed for the particular application. For the_
`disclosed star tracker use of the CCD image detector
`system 10, the Intel 8080 microprocessor is suitable.
`The CPU/memory module 15 further includes random
`"access memory (RAM) and read only memory (ROM)
`which are not shown. Also, the CPU/memory module
`15 includes appropriate interface and control circuitry,
`as required, such as a clock generator and driver. The
`specific implementation of the CPU/memory module
`15 will depend on many factors including the micro-
`processor used, and specific implementations will be
`readily apparent to persons skilled in the art.
`Associated with the CPU/memory module 15 is an
`address bus 17 and a data bus 19 for addressing other
`functional elements in the CCD detector system 10 and
`for communication between the CPU/memory module
`15 and such other elements. Also, a control bus 21 is
`provided for the communications of control informa-
`tion (such as read or write commands). Power supply
`connections and other well known details of micro-
`processor based systems are not shown.
`The CCD detector system 10 further includes an '
`attitude computer interface 23 for communicating with
`the attitude computer (not shown) that utilizes the dis-
`closed detector system 10. Thus, commands from the
`attitude computer are communicated via the interface
`23, and position information regarding the star or stars
`being tracked is provided to the attitude computer via
`the interface 23. As is shown, the interface 23 iscoupled
`to the address bus 17 and the data bus 19.
`~
`The CPU/memory module 15 further controls a tim-
`ing module 25 which provides the clock and control
`signals for outputting the integrated charge patterns of
`the CCD image detector 13. As will be more fully de-
`scribed below, the timing module 25 selectively con-
`trols, inter alia, the rate of transfer of the line charges to
`the horizontal shift register of the CCD detector 13 and
`whether the horizontal shift register outputs its charge
`packets. The clock rate of the output of the horizontal
`transport register is also controlled by the timing mod-
`ule 25.
`.
`
`10
`
`15
`
`20
`
`25
`
`, 30
`
`4
`on FIG. 2. The elements forming a row in the array 33
`are sometimes collectively referred to as a line or hori-
`zontal line. The elements forming a column are some-
`times collectively referred to as a vertical column. As is
`well known to persons skilled in the art, each pixel 31
`develops an induced charge packet having a charge
`level that is proportional to incident light intensity and
`duration of exposure to incident light prior to transfer of
`the charge packet. The duration of exposure is also
`referred to as the integration period.
`The integrated charges are clock outputted, and the
`integrated charges associated with an individual hori-
`zontal
`line are ultimately transferred to a horizontal
`transport register 35 which is shown in FIG. 2. An
`onchip amplifier 37 provides the video output from the
`CCD detector.
`By way of reference, a field can be considered as a
`collection of horizontal lines, and the field is’sequen-
`tially clocked into the horizontal transport register 35’
`line by line. Some CCD devices define all of the hori-
`zontal lines as one field (often referred to as a “frame”),
`while others define the odd horizontal lines as one field
`and the even horizontal lines as another, wherein both
`fields comprise the frame. In either case, after an inte-
`gration period the charges of the entire CCD array are
`transferred to the horizontal transport register one line
`at a time as controlled by appropriate clocking. Obvi-
`ously, where the entire array is divided into two fields,
`the charges associated with the lines of one field (for
`example, the odd lines) are sequentially transferred, on
`a line-by—line basis to the horizontal transport register,
`and then the charges associated with the other field (in
`the same example, the even lines) are transferred to the
`horizontal transport register line by line.
`’
`Where two fields are used to output the integrated
`charges of the entire array, generally the CCD image
`detector chip includes vertical transport registers (not
`shown on FIG. 2), with one vertical transport register
`for each vertical column of image sensing elements. In
`operation, at the end of the integration period, all the
`charges of the lines corresponding to the first field are
`transferred to the vertical transport registers. Then, the
`charges on the vertical registers are transferred one line
`at a time to the horizontal register. After all the charges
`of the lines of the first field have been transferred, the
`charges corresponding to the other field are transferred
`to the vertical transport registers for line by line transfer
`to the horizontal transport register.
`In those CCD detector devices wherein contiguous
`horizontal lines are sequentially transferred to the hori-
`zontal transport register, vertical transport registers are
`not used. Rather, the contents of each line is transferred
`to the adjacent line closer to the transport register upon
`appropriate vertical clock signals. Thus, the charges of
`respective lines are transported to the horizontal trans-
`port register on a line by line basis.
`I
`‘
`"
`It should be noted that the horizontal register of ‘the
`CCD image detector 13 is not cleared unless it is trans-
`ferred out by appropriate clocking. Thus, transferring
`the charges for a line into the horizontaltransport regis-
`ter without having serially outputted the charges from
`the previous line will result in charge accumulation, and
`the information corresponding to those -lines whose
`charges were accumulated is lost. That,‘however, does
`not matter where the information "associated with the
`charges of such accumulated lines is of no interest.
`The CCD detector 13 is a clocked device requiring
`vertical shift clock signals to transfer the linecharges to
`
`35
`
`40
`
`45
`
`50
`
`55
`
`The outputs of the timing module 25 are provided to
`a video circuit module 27 which contains appropriate
`driver circuitry for driving the CCD image detector 13.
`The video circuit module 27 further includes a pre-
`amplifier for the video output of the CCD horizontal
`register, and circuitry for sampling the pre-amplified
`signal. Video circuitry for driving and sampling CCD
`image detectors are known to persons skilled in the art.
`The sampled outputs from the video circuit module
`27 are provided to an analog-to-digital (A/D) converter
`29. Communication between A/D converter 29 and the
`CPU/memory module 15 is via the address bus 17, the
`data bus 19, and the control bus 21. In accordance with
`the principles of the disclosed invention, the A/D con-
`verter 29 operates only on those CCD video output
`samples that are of interest as defined by the CPU/-
`memory module 15. The A/D results are communi- I
`cated to the CPU/memory module 15 as data on the
`data bus 19.
`By way of example, the CCD image detector 13 can
`be one of the suitable commercially available detectors
`such as those available from RCA or FAIRCHILD.
`For ease of explanation, a simplified block diagram of a
`typical CCD image detector chip is shown in FIG. 2.
`As discussed previously, a typical CCD image detector
`includes discrete light-sensing elements 31 called pixels
`which are distributed in a rectangular grid 33, as shown
`
`'
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`65
`
`

`
`5
`the horizontal shift registers. On each vertical shift
`clock, each line being transferred advances one line and
`the line adjacent the horizontal transport register 35
`transfers into the horizontal transport register 35. The
`CCD detector further requires horizontal shift clocks 5
`for outputting the contents of the horizontal transport
`register. Specifically, the video output of a new charge
`packet is provided with a new horizontal shift clock.
`It shouldbe noted that in referring to vertical and
`horizontal shift clocks, persons skilled in the art will
`readily recognize that a CCD image detector will gen-
`erally include multiple inputs for multi-phase clock
`signals. The details of the multi-phase clocking require-
`ments of CCD image detectors are well known to per-
`sons skilled in the art.
`In the disclosed invention, the vertical shift clock
`(VCLOCK) is of a fixed period and is provided only
`after the horizontal transport register is fully shifted out
`or only when the horizontal shift register is not to be
`outputted. Thus, where no horizontal shift clocks are
`applied, VCLOCK is continually applied. Otherwise,
`VCLOCK is controlled so that it does not occur until
`after the horizontal clocks have ceased.
`The horizontal clocks (generally called HCLOCK
`herein) are of variable periodicity. A fast HCLOCK
`called HCLOCK1 is utilized in shifting charges associ-
`ated with image sensing elements outside a predeter-
`mined area of the CCD array called the field of View
`(FOV). Within the field of view, a slower HCLOCK
`called HCLOCK2 is utilized.
`
`10
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`15
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`20
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`25
`
`30
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`40
`
`45
`
`The field of view (FOV) referred to depends on the
`mode of operation of the detector system 10. By way of
`example,
`the disclosed invention is contemplated to
`include a target acquisition mode and a track mode. In
`the acquisition mode the FOV is 1° X 10° wherein the 1° 35
`dimension is in the horizontal line direction. In the track
`mode, the FOV is 10° X 10°. Both of these fields of view
`are considerably smaller than the entire field of view of
`the CCD detector 13 and will be discussed more fully
`below.
`i
`'
`Insofar as timing control of the CCD detector 13 is
`important to the operation of the disclosed detector
`system 10, the following definitionsin the context of
`timing are provided for a better understanding of the
`invention.
`A
`SCAN. As used with regard to the CCD detector 13,
`this term refers to the line by line transfer of charge
`packets into the horizontal transport register, regardless
`of whether the horizontal transport register is clocked.
`Thus, the overall operation of selectively clocking the
`CCD detector to ultimately clear all the pixels will be
`called scanning.
`READ. As used in conjunction with the video output
`from the amplifier 37, reading that output will refer to
`the sampling and A/D conversion of a particular video
`output from the amplifier 37. Thus, the horizontal trans-
`port register can be clocked, thereby providing video
`outputs, but such outputs are not necessarily read.
`When a video output is read, the horizontal shift clock
`signals
`(which will
`necessarily
`be
`the
`slower
`HCLOCK2) are not furnished to the CCD detector 13
`until A/D conversion is complete. This insures that
`subsequent charge packet data is not lost.
`HORIZONTAL ACCUMULATE MODE.’ In this
`mode of operation, charges associated with a horizontal
`line are transferred to the horizontal shift register with-
`out serially outputting the horizontal register contents
`from the previous horizontal line(s). VCLOCK is con-
`
`50
`
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`
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`4,430,673
`
`6
`tinually applied without any intervening HCLOCK,
`and information corresponding to horizontal lines thus
`accumulated is lost.
`
`,
`
`SERIAL DUMP MODE. In this mode of operation,
`the entire contents of the horizontal transport register is
`clocked out but not read (i.e. without A/D conversion)
`by application of the horizontal shift clock HCLOCK
`prior to transfer into the horizontal register of the
`charges of a subsequent line. The faster HCLOCK1 is
`utilized to shift out charges corresponding to those
`elements which are not within the controlling field of
`view and the slower HCLOCK2 is used to shift out
`charges corresponding to image detecting elements
`within the field of view. The vertical shift clock
`VCLOCK is not applied until after the horizontal trans-
`port register has been completely shifted out, and thus
`the horizontal
`transport register is cleared prior to
`transfer into the horizontal register of the charges of a
`subsequent line.
`SELECTIVE READ MODE. In this mode of oper-
`ation, the horizontal transport register is clocked with
`the appropriate horizontal shift clocks HCLOCK1 and
`HCLOCK2. When a video output is to be read, such an
`output is sampled and provided to the A/D converter,
`and the horizontal register is not clocked until that A/D
`conversion is completed. The A/D conversion delay is
`considerably longer than either of the horiziontal shift
`clock periods, and therefore charges associated with
`pixels not to be read can be outputted as fast as practica-
`ble since they do not have to be A/D converted.
`Thus,
`the disclosed invention minimizes the time
`required to scan the CCD detector 13 through the con-
`trol of the clocks applied. The image areas of interest
`are processed as required, while those areas not of inter-
`est are scanned expeditiously.
`Referring now to FIG. 3, illustrated therein is a block
`diagram of the timing module 25 of FIG. 1. Well known
`details such as input and output decoders, data bus buff-
`ers, and control lines are not shown. The timing module
`of FIG. 3 includes an element/line compare logic 39
`which compares the element count (ECOUNT) and
`line count (LCOUNT) of the current video output of
`the horizontal transport register of the CCD detector 13
`(FIG. 1) with position data provided by the CPU/mem-
`ory module 15. The position data from the CPU is
`loaded via the CPU data bus 19 upon an appropriate
`load data command. A CCD master clock MCLK,
`which is derived from the CPU master clock, is also
`provided to the element/line compare logic 39. The
`compare logic 39 provides an Equal Flag output that is
`active when the current video output coincides with the
`position data. The Equal Flag output is utilized by the
`CPU/memory module 15 to stop the CCD clocks to
`allow for A/D conversion.
`The line count and element count signals are pro-
`vided by scan control/count logic 41. The line count
`and element count are indicative of the CCD image
`element position associated with the video output from
`the horizontal transport register. As indicated, the ele-
`ment count and line count are also provided to the
`CPU/memory module 15. The CCD scan control/-
`count logic 41 also provides read control information.
`Inputs to CCD scan control/count logic 41 include a
`reset signal to synchronize the count logic to output of
`the CCD detector 13, and the CCD master clock
`MCLK. Further, an Accumulate On signal is provided
`to the scan control/count logic 41 that indicates when
`
`

`
`7
`the horizontal accumulate mode is on, thereby prevent-
`ing erroneous element counts.
`The CPU/memory logic 15 further provides start/-
`stop commands to the scan control/count logic 41 to
`indicate when the video output of the horizontal trans-
`port register is to be read (that is, A/D converted), and
`when the counting process should stop. The start/stop
`information is also provided in the read control infor-
`mation outputted by the CCD scan control/count logic
`41.
`The Accumulate On signal is outputted by an accu-
`mulate logic circuit 43 which compares the line count
`with CPU provided line limits LIM1 and LIM2. The
`first
`limit LlM1 indicates that all
`lines prior to line
`LIM1 are to be transferred to the horizontal register in
`the horizontal accumulate mode. The other limit LIM2
`indicates that line LIM2 and succeeding lines are to be
`transferred to the horizontal transport register in the
`horizontal accumulate mode. During those intervals
`when the horizontal accumulate mode is utilized, the
`Accumulate On signal is active, thereby indicating that
`the horizontal clock HCLOCK should not be supplied
`to the CCD detector 13.
`The line limits LIM1 and LIM2 are provided to the
`accumulate logic 43 from the CPU/memory module 15
`via the CPU data bus 19. That data is transferred in
`response to an appropriate load command from the
`CPU/memory module 15.
`The timing module of FIG. 3 further includes mode
`select logic 45 which provides as an output mode status
`information indicative of the mode of operation of the
`image detector system 10 (e.g.,
`target acquisition or
`track mode.) The mode of operation data is inputted
`from the CPU/memory module 15 to the mode select
`logic 45 via the CPU data bus 19 on an appropriate load
`command.
`The mode status information is provided to field of
`view (FOV) logic 47 which is also responsive to the
`element count from the CCD scan control/count logic
`41. The FOV logic provides FOV control information
`that indicates whether the element count is within the
`element count parameters of the particular FOV de-
`fined by the mode status.
`The FOV status (based on element count) is provided
`to CCD clock pulse logic 49 which also accepts the
`Accumulate On signal from the accumulate logic 43.
`Other inputs to the CCD clock pulse logic 49 include
`the read control information, the line count, and the
`element count from the CCD scan control/count logic
`4]. The CPU master clock is also inputted to the CCD
`clock pulse logic 49.
`‘
`On the basis of inputs it receives,
`the CCD clock
`pulse logic 49 provides
`the vertical
`shift clock
`VCLOCK and the horizontal shift clock HCLOCK to
`the video circuitry 27. It also provides the CCD master
`clock MCLK which is synchronized to the CPU master
`clock. Thus, appropriate VCLOCK’s and fast or slow
`HCLOCK’s are provided.‘Moreover, in response to the
`start/stop command from the CPU to the CCD scan
`control/count logic 41, the CCD clock pulse logic 49 is
`provided with read information indicating that A/D
`conversion is to be performed and the clock signals to
`the CCD detector 13 should be stopped.
`Further,
`the Accumulate On signal and the FOV
`status provide the CCD clock pulse logic 49 with infor-
`mation to provide HCLOCK1 and HCLOCK2 at the
`appropriate element and line counts. That is, the hori-
`zontal shift clock HCLOCK is applied between lines
`
`l0
`
`IS
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4,430,673
`
`8
`LIM1 and LIM2, and the appropriate clock rate
`HCLOCK1 and I-ICLOCK2 is utilized depending on
`the element count.
`,
`Referring now to FIG. 4, illustrated therein is a flow-
`chart defining the functions performed by the CCD
`image detector 13 in the target acquisition mode. In that
`mode, the field of view in terms of element count is
`defined by the FOV logic 47 in response to the mode
`status. The field of view in terms of line count is defined
`by the accumulate logic 43 in response to LIM1 and
`LIM2 as provided by the CPU/memory logic 15. Thus,
`the charges associated with the lines within the field of
`view are outputted, and the charges associated with
`elements within the field of view are outputted using
`the slower HCLOCK2. As shown by the function
`blocks 51 and 53 in FIG. 4, video outputs are provided
`for each of the charges associated with the CCD ele-
`ments in the field of view, and the element having the
`brightest image is determined.
`A decision is made in a decision block 55 as to
`whether the image intensity in that brightest element
`exceeds a predetermined analog threshold. If it does
`not, then the CCD detector array is again scanned. If
`the image intensity exceeds the predetermined thresh-
`old, information regarding the location of the element
`having the brightest image intensity is utilized to define
`an acquisition matrix of CCD elements to be read (i.e.,
`A/D converted) as shown by function block 57. In a
`star tracker system, that matrix would typically com-
`prise a six by six element array.
`On the basis of that matrix, the CCD detector 13 is
`scanned, and the video outputs associated with the de-
`fined matrix are A/D converted as shown in the func-
`tion block 59. The digital values representing the in-
`duced charges from the matrix elements are then uti-
`lized to calculate individual pixel intensities, as identi-
`fied in the function block 61.
`The calculated intensities are then compared with
`predetermined high and low intensity limits, as shown
`in the decision block 63. If none of the calculated inten-
`sities is between the predetermined limits, the detector
`system function returns to scanning the field of view for
`a target at the function block 51. If at least one of the
`calculated intensities is between the predetermined lim-
`its, then the calculated intensities are summed, as shown
`in the function block 65.
`The intensity sum is then compared with predeter-
`mined high and low total intensity limits, as shown in
`decision block 67. If the total intensity is not between
`the predetermined limits, then the detector system re-
`turns to scanning for another target beginning with the
`function block 51. If the total intensity is between the
`predetermined limits, then the matrix that was read, as
`represented by the individual calculated intensities,
`is
`analyzed to determine whether the image is an extended
`body. An extended body is an image that extends over
`more elements of the matrix than would be expected of
`a star, which would typically be defocused over a three
`by three matrix.
`As shown in decision block 69, if the image on the
`matrix is determined to be an extended body, then the
`image detector system returns to scanning for another
`target, starting at the function block 51. If the image is
`not an extended body, then it is regarded as an appropri-
`ate target star for tracking.
`The functions performed by the detector system in
`the track mode are set forth in the flowcharts of FIGS.
`5 and 6. In that mode of operation the matrix ofinterest
`
`

`
`9 ,
`within the appropriate field of view can be a three by
`three element tracking matrix that is determined from
`the intensity information derived in the acquisition
`mode. Further, although the tracking matrix can be
`anywhere within the 10°>< 10° tracking field of view,
`the line count limit LIM1 is set as a function of the
`tracking matrix so that the charges associated with a
`predetermined number of lines immediately prior to the
`first line that has an element of